JPH0831168A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable performing arithmetic processings and the movement processings of data in the inside of a memory without interposing a processor at high speed and with low electric power by amplifying information via a sense-amplifier after information of two memory cells are simultaneously read out on a data line. CONSTITUTION:A memory array MA is constituted of memory cells MC0 to MC3 arranged at intersected points between plural word lines W0 to W3 and plural data line pairs Dj, DjB and reference memories RC0 to RC3 for arithmetics arranged at intersected points between plural word lines RW0 to RW3, and plural data line pairs Dj, DjB. A reference word line driving circuit RXD is connected with word lines RW0 to RW3. A sense-amplifier SAA is constituted of plural sense-amplifiers SAj performing the precharges of data line pairs DjB and amplifying read out signals and input and output gates 1%. Since the of electric charges of memory cells MC0 and MC1 occurs on a data line Dj, the AND or the OR between two information is obtained via the sense- amplifier SAA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a function of performing a logical operation in parallel in a memory and a function of copying data at high speed between memory blocks.

[0002]

2. Description of the Related Art In order to perform high-speed graphics processing for personal computers, workstations, etc.,
Bit block transfer (BitBlt: bit block tran) that transfers data to a block area in display memory in bit units
sfer) function is important. This function is a function of copying a rectangular area on the screen by simply specifying the coordinates of the movement source, the width, the height, and the coordinates of the movement destination. At that time, along with the movement, logical operation processing such as AND and OR with the movement destination is required. When the CPU performs such arithmetic processing, the graphics VRAM (VRAM = Video Random Access Memor)
Since the reading and writing of the data of y) becomes enormous and the performance of the system is deteriorated, it is general to provide a graphics processor for reading and writing to the VRAM separately to reduce the load on the CPU. . For example, this type of configuration is described in Bite, November 1993, pages 229-236 (BYTE, November 1993, pp.229-236).

Further, by providing the VRAM with a logical operation function,
Examples are known in which the number of reads and writes between the graphics processor and VRAM is reduced. VR like this
As the AM, for example, Hitachi IC issued in September 1992
Memory data book (1) -SRAM, PSRAM,
Dedicated Memory, ECL RAM, pages 501-521
Page, product model name HM53462. In this conventional example, in order to perform a logical operation between information already stored in the VRAM and input data from the outside and write back to the VRAM, the same number of logical operation circuits as the input pins are provided between the input pin and the memory array. There is. At the time of the logical operation, a so-called read modified write operation of reading data from the memory array, performing a logical operation with the input data, and writing back to the memory array is performed. As a result, it is not necessary to read the data from the memory to the outside and perform the calculation in the graphics processor, and the number of data transfers between the VRAM and the graphics processor can be reduced. A technique for copying between memory cells on a memory array is disclosed in Japanese Patent Laid-Open No. 61-94290.

[0004]

However, according to the above-mentioned prior art, when a graphics processor for reading / writing the former VRAM is separately provided,
Since it is necessary to read out the information in the memory one by one every time the calculation is performed, there is a problem that the calculation speed is limited by the access time of the memory.

Further, in the latter conventional example in which the logical operation function is provided in the VRAM, since it does not have the copy function in the memory chip, the effect of reducing the load on the graphics processor for the bit blit transfer processing is small. There was a point.

Therefore, an object of the present invention is to provide a semiconductor having an arithmetic function and a data copy function capable of performing an arithmetic process in a memory and a data copy process at high speed and low power without the intervention of a graphics processor. A storage device is provided.

[0007]

In order to solve the above problems, a semiconductor memory device according to the present invention has a plurality of word lines, a plurality of data line pairs, a plurality of word lines and a plurality of data lines. A memory array having a plurality of memory cells arranged at desired intersections of a pair, a plurality of signal amplifying means connected to each data line pair of the plurality of data line pairs, and each data of the plurality of data line pairs A semiconductor memory device having a plurality of reference signal generating means connected to a line pair, further comprising word line selecting means for selecting a desired word line of the plurality of word lines, wherein the word line selecting means has the plurality of word line selecting means. Information from at least two memory cells are simultaneously read to one data line of one data line pair of the data line pair, and the one data line pair of the one data line pair is read by the signal amplifying means. Wherein the amplifying the signal appearing on line.

In the above semiconductor memory device, the reference signal generating means includes a reference memory cell array composed of reference memory cells arranged at respective intersections of the plurality of reference word lines and the plurality of data line pairs, and the reference word lines. It is preferable to be configured with a drive circuit.

In the above semiconductor memory device, the word line selecting means is a means for simultaneously and independently selecting at least two word lines.

Also, the semiconductor memory device according to the present invention includes a plurality of word lines, a plurality of data line pairs, and a plurality of memories arranged at desired intersections of the plurality of word lines and the plurality of data line pairs. In a semiconductor memory device having a memory array having cells, a plurality of reference signal generating means connected to each data line pair of the plurality of data line pairs, and a plurality of signal amplifying means each having two inputs, Means for connecting at least two of the plurality of data line pairs in parallel to two inputs of one signal amplifying means, and information from at least one memory cell for each of the plurality of data line pairs. And a word line selecting means for reading simultaneously, wherein the word line selecting means simultaneously inputs information from at least two memory cells to one of the inputs of the plurality of signal amplifying means. After reading, characterized in that to amplify the signal by the signal amplifying means.

In the above semiconductor memory device, the means for connecting at least two of the plurality of data line pairs in parallel to the two inputs of one signal amplifying means are arranged on both sides of the one-dimensionally arranged signal amplifying means. One of the data line pair of the first memory cell array and one of the data line pair of the second memory cell array are provided in two columns between the first and second memory cell arrays and the signal amplifying means. It is preferable that the two are switch means for simultaneously connecting to one signal amplifying means.

Further, the semiconductor memory device according to the present invention includes a plurality of word lines, a plurality of data line pairs, and a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs. And a plurality of memory blocks each comprising a memory array having a plurality of data line pairs, and a plurality of signal amplifying means connected to each of the plurality of data line pairs, and input / output for inputting / outputting data to / from the memory blocks. Line, a word line selection means for selecting a desired word line of the plurality of word lines, and a column address selection line and a column for selecting a signal amplification means connected to the input / output line from the plurality of signal amplification means. Copy condition setting means for setting a condition for copying a data group from the outside of the memory, and address generating means for generating a copy source and a copy destination of the data group. Characterized in that it further comprises a peak address generating means.

In the semiconductor memory device thus configured, the copy condition setting means sets the start address setting means for setting the start addresses of the copy source and copy destination of the data group and the data amount of the data group to be copied. At least data amount setting means.

In the semiconductor memory device, an input / output line for inputting / outputting data to / from the memory block,
It is preferable that the column address selection line and the column address selection means are duplicated.

Further, the semiconductor memory device according to the present invention is
A plurality of word lines, a plurality of data line pairs, a memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of data line pairs A plurality of memory blocks each composed of a plurality of signal amplifying means connected to each data line pair; a duplicated input / output line for simultaneously inputting / outputting data to / from the memory blocks; and a plurality of word lines Of word line selecting means for selecting a desired word line and a signal amplifying means connected to the duplicated input / output line from the plurality of signal amplifying means, and a duplicated column address selection line and a duplicated column address selection Means and are provided.

Further, in any of the above semiconductor memory devices, the memory array can be configured by a dynamic memory.

[0017]

According to the semiconductor memory device of the present invention, the word line selecting means for selecting a desired word line of the plurality of word lines has at least two data lines in one data line pair of the plurality of data line pairs. Obtaining the operation result of the at least two memory cells by simultaneously reading information from one memory cell and then amplifying the signal appearing on the one data line of the one data line pair by the signal amplifying means. You can

In the above semiconductor memory device, the plurality of reference signal generating means connected to each data line pair of the plurality of data line pairs are arranged at each intersection of the plurality of reference word lines and the plurality of data line pairs. The reference memory cell array including the reference memory cells and the drive circuit for the reference word line generate a reference signal for operation according to the operation mode.
At least two memory cells of one of the data line pairs are simultaneously driven and connected by, for example, at least two row decoders, which are word line selection means connected in parallel to each word line, and appear in one of the data line pairs. The calculation result corresponding to the calculation mode can be obtained by inputting the sum of the charge amounts of the memory cells and the reference signal appearing on the other side of the data line pair to the signal amplifying means, that is, the sense amplifier.

When the switch means connects between the first and second memory cell arrays sharing the signal amplifying means, that is, the data line pairs of the left and right memory cell arrays, the memory cell array on the left side is connected. The memory cell is connected to the left data line by the left row decoder, the memory cell in the right memory cell array is connected to the right data line by the right row decoder, and the left reference word line is driven. The reference memory is connected to the other data line on the left by the circuit, and the reference memory is connected to the other data line on the right by the drive circuit for the reference word line on the right. The connection between the memory cell and the reference memory cell on one side of the data line pair and the sum of the charges on the other side and the reference memory cell on the other side increase the shared signal. It is possible to obtain an operation result corresponding to the operation mode is inputted to the unit or common-connected sense amplifier. Therefore, calculation can be performed between two memory cell arrays that sandwich the sense amplifier.

As described above, in the operation between the memory cell group connected to the word line and the memory cell group connected to another word line, the reference memory cell group connected to the reference word line and the reference connected to another reference word line. Since the reference signals obtained between the memory cell group and the respective data line pairs to which the reference signals are connected are only compared by the sense amplifier, it is possible to perform them in parallel. Therefore, the logical operation can be performed without reading the information from the memory array.

In a memory having a plurality of memory blocks, a copy condition including setting means for setting the start addresses of the copy source and copy destination of the data group and data amount setting means for setting the data amount of the data group to be copied. By providing a setting means, a generation means for generating a copy source address and a copy destination address of the data group, and a copy control means for controlling the data group among the plurality of memory blocks, an instruction from the graphics processor can be obtained. By sending the information for copying to the memory, the condition setting for copying and the address of the copy source and the copy destination are generated in the memory to control the data group between the memory blocks. As a result of being able to perform copy processing without reading and writing between memories,
Data can be copied at high speed and low power.

Further, in a memory having a plurality of memory blocks, the input / output lines to the memory array are duplicated for reading and writing, and the column address selection signal and the column selecting circuit are also duplicated for reading and writing. By configuring the write I / O line to be switched and connected to the read common data line pair or the write common data line pair, in addition to normal memory operation, the data copy between the memory blocks in the memory can be read externally. It can be done without issuing.

[0023]

【Example】

<Embodiment 1> Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to FIGS. FIG. 1 is a block diagram of a memory with an arithmetic function showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, reference numeral MA
Is a memory cell array, SAA is a sense amplifier array, X
D1 and XD2 are X decoders, YD is Y decoder, A
MP is a reading amplifier, DOB is an output buffer, W
BUF indicates a write buffer.

The memory cell array MA is a memory cell arranged at an intersection of a plurality of word lines (only part of which is shown here) W0 to W3 and a plurality of data line pairs (only part of which is shown here) Dj and DjB. (Only a part is shown here) MC0-M
C3, a plurality of operation reference word lines (only part of which are shown here) RW0 to RW3, and a plurality of data line pairs Dj, DjB
Comprising arithmetic reference memory cells (only a part of which are shown here) RC0 to RC3 arranged at intersections with. Also,
A reference word line drive circuit RXD is connected to the plurality of calculation reference word lines RW0 to RW3. Note that reference numeral D
The letter "B" in jB and IOB is a pair D
Represents a negative relationship (or complementary relationship) between j and IO.

The sense amplifier array SAA includes a plurality of sense amplifiers SAj for precharging the data line pairs Dj and DjB and amplifying the read signals, and the data line pair DA.
It is composed of a plurality of input / output gates IOG for connecting j and DjB to the input / output line pairs IO and IOB. here,
The input / output gate IOG is composed of MOS transistors M1 and M2.
Is connected to the Y address selection signal YSj.

In the semiconductor memory device according to the present invention having such a structure, the memory cells MC0 to MC3 used in a general dynamic memory are 1
Although a T-1C type cell, that is, one MOS transistor and one storage capacitor is used, the present invention is not limited to this as long as it is configured to store charges by storing them.
In addition, the sense amplifier SAj has a data line pair Dj, DjB.
A known differential amplifying circuit can be used as long as it is a signal amplifying unit that amplifies a minute voltage difference between them, and of course, it may have the same circuit configuration as that used in a general dynamic memory. Therefore, the circuits other than the calculation reference memory cell and the reference word line drive circuit RXD can be configured by circuits used in general dynamic memories.

In the configuration shown in FIG. 1, two memory cells (for example, MC0 and MC1) connected to the data line Dj or two memory cells (for example, MC2 and MC3) connected to the paired data line DjB are provided. The calculation result of the stored information can be simultaneously obtained for the memory cells connected to the plurality of data line pairs Dj or DjB, respectively. Two
Two word lines, for example W0 and W1, are selected to obtain the operation result of one memory cell. Further, for example, two memory cells MC0 and MC1 connected to the data line Dj
When the stored information is calculated, the pair of data lines D
Two calculation reference memory cells RC0, R connected to jB
C1 is selected by the operation reference word lines RW0 and RW1. Similarly, when the word lines W2 and W3 are selected and the storage information of the two memory cells MC2 and MC3 connected to the data line DjB is calculated, the two calculation lines connected to the paired data line Dj are used. The reference memory cells RC2 and RC3 are selected by the operation reference word lines RW2 and RW3.

FIG. 2 shows a specific configuration example of the driving reference memory cell and the drive circuit RXD for the reference word line thereof. Here, only the configurations of the operation reference memory cells RC0 and RC1 are shown, but the operation reference memory cells RC2 and RC3 have the same configuration. In FIG. 2, reference numeral M
10 to M13 are N-channel MOSFETs (hereinafter referred to as NMO
C10 and C11 are storage capacitors, PL is a common plate electrode, and INV1 to INV3 are inverters. Here, the common plate electrode PL is fixed to a half potential of the high potential side power supply voltage VCC (not shown), that is, a potential of VCC / 2. The calculation reference memory cell RC0 has the same configuration as the memory cell MC0,
The value of the storage capacity C10 is also substantially the same as the value of the storage capacity of the memory cell MC0.

The reference memory cell for calculation RC1 has an NMOS transistor M12 added to the normal memory cell MC1 so that the potential of the storage node of the reference memory cell for calculation RC1 can be set from the outside. That is, when the operation mode setting signal SET is applied, the NMOS transistor M12 becomes conductive and the voltage VMA is written in the storage capacitor C11. Mode setting voltage signal V given from the outside
M is written to the input of the inverter INV2 by applying the mode setting signal MS which is a timing signal for mode setting. This voltage is applied to the inverters INV2 and I
A latch composed of NV3 holds it while the power is on. The input of the inverter INV1 is connected to the output of the inverter INV2, and the voltage VMA is output to the output of the inverter INV1.

Therefore, the value of the voltage VMA becomes one of the power supply voltages, that is, the high-potential-side power supply voltage VCC or the low-potential-side power supply voltage VSS (not shown), according to the mode setting voltage signal VM supplied from the outside. . Calculation reference word line R
By driving W1 at the same timing as the word line W1 of the memory cell, the operation result corresponding to the voltage difference between the data line pair Dj and DjB is obtained by the sense amplifier SAj. On the other hand, a high voltage is always applied to the calculation reference word line RW0 so that the NMOS transistor M10 remains conductive. The arithmetic reference memory cell RC0 is similar to the arithmetic reference memory cell RC1 in NMO.
The S transistor M12 may be connected, but in that case, the NMOS transistor M12 connected to the arithmetic reference memory cell RC0 may be kept non-conductive at all times.

In the memory with the arithmetic function of the present embodiment, when the arithmetic operation of the signal is performed, the two reference memory cells for arithmetic operation which are paired with the two memory cells are simultaneously selected. For example, when the information stored in the memory cells MC0 and MC1 is calculated, the reference memory cells RC0 and R0 for calculation are used.
Select C1 at the same time. Data line pair Dj, Dj at this time
FIG. 3 shows changes in the B voltages VDj and VDjB. In this case, since the sum of the charges of the memory cells MC0 and MC1 appears on the data line Dj, three kinds of voltages appear depending on the combination of the stored information. That is, when the voltages stored in the memory cells MC0 and MC1 are both high voltage “1” → Dj (1,1), when one is high voltage “1” and the other is low voltage “0” → Dj (0,
1) or Dj (1,0), both of which are low voltage “0” → Dj (0,0).

On the other hand, two types of voltages appear on the reference data line DjB according to the information stored in the arithmetic reference memory cell RC1. Because a high voltage is always applied to the operation reference word line RW0 as described above, the voltage stored in the operation reference memory cell RC0 is constant voltage VCC /
This is because the electric charge accumulated in No. 2, that is, the electric charge accumulated in the arithmetic reference memory cell RC0 is held at "1/2" which is an intermediate between "1" and "0". Therefore, when the voltage stored in the arithmetic reference memory cell RC1 is “high voltage“ 1 ”→ DjB (1,1 / 2),“ low voltage “0” → DjB (0,1 / 2) ) And two. The charges accumulated in the calculation reference memory cell RC0 are "1" and "
Since it is in the middle of 0 ″, the voltage of DjB (1,1 / 2) is Dj (1,1) and Dj (0,1) or Dj (1,2).
It is in the middle of 0). Further, the voltage of DjB (0,1 / 2) is Dj (0,0) and Dj (0,1) or Dj (0,0).
It is in the middle of (1,0).

Therefore, VDjB = DjB as reference information
When the sense amplifier is operated using (1, 1/2),
Only when the combination of information stored in the memory cells MC0 and MC1 is the combination of Dj (1,1), the data line Dj
Is amplified to a higher voltage, and other combinations result in a lower voltage. That is, the logical product AND of the storage information of the two memory cells MC0 and MC1 can be obtained. Also,
When the sense amplifier is operated using VDjB = DjB (0,1 / 2) as reference information, the data line Dj is amplified to a low voltage only in the combination of Dj (0,0), and is high in the other combinations. Become a voltage. That is, the logical sum OR of the storage information of the two memory cells MC0 and MC1 can be obtained.

As described above, by simply setting the reference voltage of the sense amplifier connected to the data line pair, it is possible to easily execute the AND and OR operation functions of the information stored in the memory cells. As can be understood from the above description, the newly provided drive circuit RXD for the reference word line for calculation keeps only one of the reference word lines for calculation always at the high level and performs the operation of the AND operation. This is a drive circuit that sets all other operation reference word lines to a high level, and sets all other operation reference word lines to a low level when performing an OR operation.

FIG. 4 is a timing chart showing an example of the operation timing of the memory with the arithmetic function shown in FIG. In this example, the amplitude of the data line pair Dj, DjB is 2V,
Word lines W0, W1 and reference word lines RW0, R for calculation
The case where the amplitude of W1 is 3.5 V is shown, but the value is not limited to these values.

In this example, the operation mode is set and the memory cell is written before the operation.
First, from time t0 to t1, the operation mode setting signal SET is set to a high level, and the operation reference memory cell RC1
"1" or "0" is written in. Now, it is assumed that the OR operation is performed, and "0" is written. From time t2 to t6, the word line W0 is set to the high level and the operation data is written in the memory cell MC0. This is a normal DRA
Similar to M, after performing the read operation once, the Y address selection signal YSj is set to the high level to input / output line pair IO and I.
Information from the outside is written in MC0 from the OB through the input / output gate IOG. Similarly, from time t7 to t11
The word line W1 is set to the high level, and the memory cell MC
The other calculation data is written into 1. The calculation reference word line RW0 is always kept at the high level. From time t12 to t15, the word lines W0, W
1. The reference word line RW1 for calculation is set to high level at the same time,
The accumulated charges are caused to flow from the memory cells MC0 and MC1 to the data line Dj, and from the calculation reference memory cells RC0 and RC1 to the paired data line DjB. That is, VDj is used as reference information for the paired data line DjB.
A voltage of B = DjB (0,1 / 2) appears, and the reference voltage of the sense amplifier SAj is set. After that, the normal DR
By amplifying by the sense amplifier SAj as in the case of AM, the operation result, in this case, the OR of information of MC0 and MC1
The result of the calculation can be obtained as the voltage difference between the data line pair Dj and DjB.

As described above, according to the memory with the arithmetic function of the present invention as shown in this embodiment, the memory cell MCn (n = 0, 1, ...) Is not provided with a new arithmetic circuit.
Reference memory cells RCn (n = 0, 1, ...
...) and its reference word line drive circuit RXD and reference signal generating means, and two X decoders XD1 and XD2 connected in parallel to the word line are only added to perform a logical operation in word line units in parallel. be able to. This makes it possible to significantly increase the calculation speed while minimizing the increase in power.

<Embodiment 2> With reference to FIG. 5, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the case where the information of two memory cells is calculated has been described. However, the memory with a calculation function according to the present invention can similarly calculate the information of three or more memory cells. In this embodiment, as an example, a case where information of three memory cells is calculated will be described. Note that the configuration is similar to that shown in FIG. 1, except that three X decoders are connected in parallel to word lines in order to select three memory cells independently at the same time. Therefore, the configuration diagram is omitted.

FIG. 5 is a diagram showing changes in the voltages of the data line pairs Dj and DjB when the information of three memory cells is calculated. Four kinds of voltages are generated on the data line Dj according to the information stored in the three memory cells. That is, all three memory cells have high voltage "
1 ”, one of the three memory cells has a low voltage“ 0 ”, two of the three memory cells have a low voltage“ 0 ”, and all three memory cells have a low voltage“ 0 ”. If,

On the other hand, one of the three reference memory cells for calculation has the reference word line kept at a high level in the same manner as the reference memory cell RC0 for calculation in the first embodiment. An electric charge "1/2" intermediate between "1" and "0" is obtained. Therefore, in the reference data line DjB,
Three types of voltages can appear depending on the information stored in the remaining two calculation reference memory cells. That is, '
If the remaining two are high voltage "1", 'either one
This is the case when one of them is a low voltage "0", and the case of "the remaining two are both a low voltage" 0 ".

Therefore, as can be seen from FIG. 5, the reference data line voltage VDjB = DjB (1, 1,
1/2) is used to operate the sense amplifier, the combination of information stored in the three memory cells becomes Dj
The data line Dj is amplified to a high voltage only in the case of the combination of (1, 1, 1), and becomes a low voltage in the other combinations. That is, the logical product A of the information stored in the three memory cells
ND can be calculated. In addition, VD as reference information
When the sense amplifier is operated using jB = DjB (0,0,1 / 2), the data line Dj is amplified to a low voltage only in the combination of Dj (0,0,0), and in other combinations. It becomes a high voltage. That is, the logical sum OR of the information stored in the three memory cells can be obtained.

In this way, when the logical product AND of the storage information of the three memory cells is taken, "1" may be stored in the remaining two of the three reference memory cells for calculation, and the logical sum is obtained. In the case of OR, "0" may be stored in the remaining two of the three calculation reference memory cells.

Also in the present embodiment, the memory cell MCn (n
= 0, 1, ...) and the same kind of reference memory cell RCn (n =
0, 1, ...) And a drive circuit RXD for the word line thereof, and an X decoder connected in parallel to the word line by the number of operation bits (in this embodiment, 3 connected in parallel). It is possible to perform a logical operation in parallel for each word line only by adding two X decoders). This makes it possible to significantly increase the calculation speed while minimizing the increase in power.

<Third Embodiment> With reference to FIG. 6, a memory with an arithmetic function showing a third embodiment of the semiconductor memory device according to the present invention will be described. FIG. 6 is a diagram showing operation timing for setting the calculation mode. In the first embodiment, the information of the reference memory cells connected to the reference word line is collectively set, but in the present embodiment, an example of operation timing when setting is possible for each Y address is shown. Although the circuit configuration is the same as that of FIG. 1 and is therefore omitted, the circuit configuration may be such that the SET signal line and the output VMA line of the drive circuit RXD of the arithmetic reference word line are omitted.
However, in the latter configuration, it becomes impossible to collectively set the reference memory cells connected to the reference word line. Also in this embodiment, the case where the amplitude of the data line pair Dj, DjB is 2V and the amplitude of the word lines W0, W1 and the operation reference word line RW1 is 3.5V is shown, but the values are not limited to these values. is not.

First, at time t20, the calculation reference word line RW1 is set to the high level. At the same time, the Y address selection signal YSj is set to high level, and writing is performed from the input / output line pair IO, IOB to the data line pair Dj, DjB. calculation control information corresponding to the type of calculation from t22 to t23,
That is, it corresponds to logical product AND and logical OR
The 1 "and" 0 "information is written from the input / output line pair IO, IOB to the data line pair Dj, DjB, and then t24.
In this case, by setting the operation reference word line RW1 to the low level, the operation control information is transferred to the operation reference memory cell RC1.
Is accumulated in In the calculation, as in the first embodiment,
From t25 to t28, the word lines W0 and W1 and the operation reference word line RW1 are changed to the high level, the sum of charges appears on the data line pair Dj and DjB, and is amplified by the sense amplifier SAj.

In this embodiment, unlike the first embodiment, the calculation mode is set from the data line pair without using the calculation mode setting signal SET. Therefore, there is an advantage that the calculation mode can be independently set for each data line pair. Further, as shown in this embodiment, the number of changes of the Y address selection signal YSj can be reduced by setting the operation mode continuously after writing the information into the memory cell, and the speed is increased. It is possible to reduce power consumption. In this embodiment, after writing the information in the memory cell, the writing in the reference memory cell for setting the operation mode is performed, but the order of this writing may be changed.

<Embodiment 4> A memory with an arithmetic function showing a fourth embodiment of the semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 7 is a block diagram of a memory with an arithmetic function of the present embodiment. In addition to the configuration of FIG. 1, the input / output lines to the memory cell array are duplicated for reading and writing, and a Y address selection signal and a Y address are provided. The selection circuit is also duplicated for reading and writing.

In FIG. 7, reference numerals MAL0 to MAL are used.
n and MAR0 to MARn are memory cell arrays, SA
A0 to SAAn are sense amplifier arrays, RYD is a read Y decoder, WYD is a write Y decoder, and RY.
Sj is a read Y address selection signal line, WYSj is a write Y address selection signal line, RYAC is a read Y address counter, WYAC is a write Y address counter, AREG is an address register, CLK is a clock signal, and RASB is a row address. Strobe signal, CA
SB is a column address strobe signal, WEB is a write enable signal, XDL0 to XDLn and XDR0 to X.
DRn is an X decoder, XLL0 to XLLn and XLR
0 to XLRn are X address latches, RIO and RIO
B is a read input / output line, WIO and WIOB are write input / output lines, IOS0 to IOSn are IO switches,
RCDL and RCDLB are read common data lines, WCDL and WCDLB are write common data lines, AMP is a read amplifier, DOB is an output buffer, and WBUF is a write buffer. The reference word lines RW0 to RWn for calculation shown in FIG.
The calculation reference word line drive circuit RXD is shown in FIG. 8 described later and is omitted in FIG. 7. Further, reference numerals RIOB,
The English letter "B" in WIOB, RCDLB and WCDLB is
RIO, WIO, RCDL, and WCDL that make a pair respectively
Represents a negative relationship (complementary relationship).

Here, a more detailed structure of the memory cell array and the sense amplifier array is shown in FIG. In FIG. 8, reference numeral RIOGj is a read gate and WIOG.
j is a writing gate, M20 to M23 are NMOS transistors, SHL is a left array selection signal, and SHR is a right array selection signal. In this example, in order to reduce the number of sense amplifiers SAj, two memory cell arrays MA on the left and right are provided.
One sense amplifier array SAA is shared by L and MAR. In a normal memory operation, either the left or right selected memory cell array MAL or MAR and the sense amplifier SAj are connected by an array selection signal SHL or SHR. In the operation mode, both the array selection signals SHL and SHR are set to the high level and the data line D
Lj and DRj and DLjB and DRjB are operated in a connected state. For example, by setting the word lines W0 and W2 and the operation reference word lines RW0 and RW2 to the high level, the memory cells MC0 and M0 can be changed as in the embodiment of FIG.
The calculation result of C2 can be obtained. With such a configuration, calculation can be performed between the two cell arrays MAL and MAR sandwiching the sense amplifier SAj. The letter "B" of the reference symbols DLjB and DRjB represents a negative relationship (complementary relationship) between the paired DLj and DRj.

With such a configuration, the memory with an arithmetic function of this embodiment can efficiently perform arithmetic between frames of a moving image. FIG. 9 is a timing chart showing the lapse of time when the interframe arithmetic processing is performed based on this configuration. In the square area of FIG. 9, the upper symbols indicate W, OP indicates calculation, and R indicates read operation. Further, in the square area of FIG. 9, the lower symbol indicates which of the two temporally consecutive frames A and B is to be processed, and each of the frames A and B has a value of 0 to n. It is divided into (n + 1) subframes. These correspond to the places to be accessed in the memory as they are, for example, subframes A0 to A
n indicates the left array, subframes B0 to Bn access the right array, and AB0 to ABn access the left array and the right array at the same time. The subscripts 0 to n are the plurality of sense amplifier arrays SAA0 to SAA shown in FIG.
It shows which location of AAn is to be accessed.

Before time t30, the memory cell array MAL and the sense amplifier SAj are first connected by the left array selection signal SHL, and the information of the frame A is transferred to the subframe A0.
Write to memory arrays MAL0 to MALn corresponding to ~ An. Further, after the time t30, the right array selection signal S
HR memory cell array MAR and sense amplifier SA
j to connect the information of the next frame B to the subframe B0
To Bn memory cell array MAR0 to MARn
Write in. In parallel with this, for example, when the information of the subframes A0 and B0 is complete at time t31, the array selection signals SHL and SHR are both set to the high level, and the data lines DLj and DRj and DLjB and DRjB are connected to each other. Then, the arithmetic mode is switched to the arithmetic mode, and the word lines of the memory cell array MAL0 and the memory cell array MAR0 and the arithmetic reference word line are set to the high level, whereby the arithmetic processing between the subframes A0 and B0 is performed. Further, at the time t32, when the arithmetic processing between the subframes A0 and B0 is completed, the read Y address selection signal line RYS is read.
j is set to a high level, and read I / O lines RIO and RI
At the same time as the calculation result is read from the OB, the calculation processing of the next subframes A1 and B1 is performed in the same manner. Less than,
By repeating this operation, calculation between frames of a moving image can be performed.

As described above, according to the present embodiment, since the memory cell arrays are different, it is possible to perform so-called pipeline processing for executing the write, read and operation operations in parallel. Therefore, the configuration of the present embodiment is suitable for a process involving continuous input / output of data, such as a moving image process.

<Fifth Embodiment> A memory with a copy function showing a fifth embodiment of a semiconductor memory device according to the present invention will be described with reference to FIG. 10 is almost the same as the configuration of FIG. 7 shown in the fourth embodiment, but in order to make it suitable for the copy processing in the memory, the fourth embodiment has the following three points.
The configuration is different.

(1) Read input / output lines RIO, RIO
B and read common data lines RCDL, RCDLB
Read preamplifiers AP0 and AP1 are provided between the read preamplifiers AP0 and AP1 and (2) write postbuffers WB0 and W0 for driving the write input / output lines WIO and WIOB.
B1 is provided, and (3) the write post buffers WB0 and WB1 are connected to the write common data line WC.
DL, WCDLB or common data line for reading RCD
That is, the changeover switches WSL0 and WSL1 for connecting to either L or RCDLB are provided.

Here, the preamplifier AP0 for reading,
The AP1 amplifies the signals of the read input / output lines RIO and RIOB up to the power supply voltage and outputs the read common data line RC.
It has the ability to drive DL and RCDLB at high speed. Further, the changeover switches WSL0 and WSL1 are the write post-buffers WB in the normal memory operation.
0 and WB1 are common data lines for writing WCDL and WC
The external write information, which is set to connect the DLB and is input from the data input terminal DIN via the write buffer WBUF, is transmitted via the write common data lines WCDL and WCDLB to the write post buffers WIO and WIOB. Work to tell. On the other hand, when performing the memory copy operation, the changeover switch W
SL0 and WSL1 are write destination post-buffers WB0 and WB1 for the copy destination, and read common data line RCD.
L, works to connect to RCDLB.

Hereinafter, the copy operation of the memory with a copy function of the present embodiment configured as described above will be described by taking the case where the memory cell array MAL0 is the copy source and the memory cell array MAL1 is the copy destination as an example. The components not shown in FIG. 10 are the same as the components in FIG. 8, so the reference numerals shown in FIG. 8 are used.

First, the operation during copying will be described with reference to the operation timing chart shown in FIG. In this example, the copy operation is set by a combination of signals that are not used in the normal read / write operation. That is, the time t when the row address strobe signal RASB signal input to the address register AREG changes to low level.
The column address strobe signal CASB and the write enable signal WEB at 0 are both set to low level, and the combination of the address signal Ai at that time causes
Enter the copy source address setting mode. The address at this time is set in the read Y address counter RYAC. Also, at the next t1, the copy destination address is set and the address is set to the write Y address counter WY.
Set to AC. Thereafter, at t2 to t5, the copy operation is performed while sequentially counting up the read Y address counter RYAC and the write Y address counter WYAC in synchronization with the clock signal CLK.

In this example, the copy source address and the copy destination address are set in one cycle each, but if the address signals are insufficient, each may be set in two cycles. Further, after setting the copy operation mode in the first cycle, the copy source address and the copy destination address may be set in the next two cycles. Further, the copy operation mode or the copy source address or the copy destination address may be set by a combination of signals other than these signals which are not used in the normal read / write operation.

Further, the copy operation will be described with reference to FIG. First, the left array selection signal SHL of the sense amplifier array SAA0 is set to the high level and the memory cell array MAL is set.
0 data line pair DLj, DLjB is connected to sense amplifier SAj
And the read Y address selection signal line RYSj is set to a high level to select the read gate RIOGj (indicated by X) to make it conductive, and the memory cell array MAL is connected.
Information of the memory cell indicated by a circle in 0 is placed on the read input / output lines RIO and RIOG. The read input / output lines RIO and RIOG are connected to the read preamplifier AP0.
Read common data lines RCDL, RCDL via
Connected to B. Therefore, the memory cell array MAL
The information of the memory cell indicated by a circle in 0 appears on the read common data lines RCDL and RCDLB.

On the other hand, in order to perform the copy operation, the changeover switch WSL1 works so as to connect the write post buffer WB1 to the read common data lines RCDL, RCDLB. Therefore, the sense amplifier array SAA1
Of the write I / O lines WIO1 and WIOB1 are connected to the write post buffer WB1 and the changeover switch WS.
Read common data lines RCDL, RC via L1
Connected to DLB. At this time, the write Y address selection signal line WYSk is set to high level to set the write gate WIOGk (indicated by X) to the conductive state, and the left array selection signal SHL of the sense amplifier array SAA1 is set to high level. The data line pair DLj, DLjB of the array MAL1 is connected to the write input / output lines WIO1, WI.
Connect to OB1. As a result, the memory cell array MAL on the read common data lines RCDL, RCDLB
The information of the memory cell indicated by a circle in 0 can be written onto the memory cell indicated by a circle in the memory cell array MAL1.

In this way, the memory cell array MAL is
The data read from 0 is read input / output line RIO0
→ Read common data line RCDL → Write I / O line WIO1 is written to the memory cell array MAL1. For the unselected memory cell array, if the voltage of the read input / output line RIO and the write input / output line WIO is set to the precharge level of the data line, for example, the intermediate value of the power supply voltage, the unselected memory Even if the input / output gates of the cell array are turned on, unnecessary DC current does not flow. If the write I / O line WIO of the copy source sense amplifier array is set to the same condition as the read I / O line RIO, the sense amplifier array is connected via the I / O gate that is made conductive by the write Y address selection signal line WYSk. Information is never reversed. From the above,
It is possible to perform the copy operation in the memory chip while ensuring the same stability as the normal memory read / write operation.

Further, in the case of the copy operation, one memory cell array performs the write operation and the other performs the read operation, but according to the configuration of the present embodiment, both of them can perform the write operation. In that case, the changeover switches WSL0 and WSL1 may be connected to the write common data lines WCDL and WCDLB.

Furthermore, the Y address selection signal line, the Y decoder, the input / output line, etc. are tripled so that reading and writing operations from the outside to another memory cell array can be performed in parallel with the copy operation. It is also possible.

By incorporating the copy function in the memory as in this embodiment, it is not necessary for the processor to repeatedly perform the operation of reading the data from the copy source of the memory and then writing the data to the copy destination, unlike the conventional case. Since the data movement is closed in the memory, the same processing can be performed at higher speed and lower power as compared with the related art.

The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various design changes can be made without departing from the spirit of the present invention. Is.

[0066]

As is apparent from the above-described embodiments, according to the semiconductor memory device of the present invention, the sum of the signal charges read from the plurality of memory cells selected by the word line is referred to for calculation. At the same time as comparing with the charges from the memory cells, the logical operation of the information of the plurality of memory cells can be performed without reading the information outside the memory.

Moreover, the data group between the memory blocks can be copied inside the memory without reading the data outside the memory.

Therefore, without the intervention of the processor, that is, without reading or writing data between the graphics processor and the memory, only the instruction and the information for copying are sent to the memory from inside the memory. The calculation processing and the data copy processing can be performed at high speed and low power, and the effective processing performance of the system is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory with an arithmetic function showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a configuration diagram of a calculation reference memory cell used in the memory with a calculation function shown in FIG. 1 and a drive circuit for a reference word line thereof.

FIG. 3 is a diagram showing changes in the data line voltage of the memory with an arithmetic function shown in FIG.

FIG. 4 is a timing chart showing an example of operation timing of the memory with an arithmetic function shown in FIG.

FIG. 5 is a diagram showing changes in the data line voltage of the memory with an arithmetic function of the second embodiment of the semiconductor memory device according to the present invention.

FIG. 6 is a timing chart showing an example of the operation timing of the memory with an arithmetic function of the third embodiment of the semiconductor memory device according to the present invention.

FIG. 7 is a configuration diagram showing a memory with an arithmetic function of a fourth embodiment of a semiconductor memory device according to the present invention.

8 is a configuration diagram of a memory cell array and a sense amplifier array of the memory with an arithmetic function shown in FIG.

9 is a timing chart showing an example of arithmetic processing between image frames of the memory with arithmetic function shown in FIG.

FIG. 10 is a configuration diagram of a memory with a copy function showing a fifth embodiment of the semiconductor memory device according to the present invention.

11 is a timing chart showing an example of operation timing of the memory with a copy function shown in FIG.

[Explanation of symbols]

MA ... Memory cell array MC0, MC1 ... Memory cell RC0, RC1 ... Operation reference memory cell RW0, RW1 ... Operation reference word line Dj ... Data line SAA ... Sense amplifier array SAj ... Sense amplifier IOG ... IO gate XD ... X decoder RXD ... Reference word line drive circuit YD ... Y decoder AMP ... Read amplifier DOB ... Output buffer XL0 to XLn, XLR0 to XLRn ... X address latch WBUF ... Write buffer RYD ... Read Y decoder WYD ... Write Y decoder RYAC ... Read Y address counter WYAC ... Write Y address counter IOS0 to IOSn ... IO switch RIOG ... Read IO gate WIOG ... Write IO gate AP0, AP1 ... Read preamplifier WB0, B1 ... write post buffer WSL0, WSL1 ... selector switch SHL ... left array selection signal SHR ... right array selection signal AREG ... address register CLK ... clock signal CASB ... column address strobe signal RASB ... row address strobe signal WEB ... write enable signal

Claims (10)

[Claims] 1. A plurality of word lines, a plurality of data line pairs,
A memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of signal amplifying means connected to each data line pair of the plurality of data line pairs. And a plurality of reference signal generating means connected to each data line pair of the plurality of data line pairs, further comprising a word line selecting means for selecting a desired word line of the plurality of word lines. Be equipped with
After the word line selecting means simultaneously reads information from at least two memory cells to one data line of one data line pair of the plurality of data line pairs, the signal amplifying means reads the information of the one data line pair. A semiconductor memory device characterized by amplifying a signal appearing on the one data line. 2. The reference signal generating means includes a reference memory cell array including reference memory cells arranged at respective intersections of a plurality of reference word lines and a plurality of data line pairs, and a drive circuit for the reference word lines. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises: 3. The semiconductor memory device according to claim 1, wherein said word line selection means is a means for simultaneously and independently selecting at least two word lines. 4. A plurality of word lines, a plurality of data line pairs,
A memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of reference signal generation connected to each data line pair of the plurality of data line pairs And a plurality of signal amplifying means each having two inputs,
At least two of the plurality of data line pairs are connected in parallel.
It further comprises means for connecting to two inputs of one signal amplifying means, and word line selecting means for simultaneously reading information from at least one memory cell for each of the plurality of data line pairs. , The word line selection means has at least two inputs to one of the inputs of the plurality of signal amplification means.
A semiconductor memory device, wherein information is read out from one memory cell at the same time and then the signal is amplified by the signal amplifying means. 5. At least two of said plurality of data line pairs
Means for connecting two in parallel to two inputs of one signal amplifying means is provided between the signal amplifying means and the first and second memory cell arrays arranged on both sides of the one-dimensionally arranged signal amplifying means. 5. The switch means is provided in two columns and is for simultaneously connecting one of the data line pairs of the first memory cell array and one of the data line pairs of the second memory cell array to one signal amplifying means. The semiconductor memory device according to 1. 6. A plurality of word lines, a plurality of data line pairs,
A memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of signal amplifying means connected to each data line pair of the plurality of data line pairs. A plurality of memory blocks, an input / output line for inputting / outputting data to / from the memory block, a word line selecting means for selecting a desired word line of the plurality of word lines, and a plurality of signals. A copy condition setting for setting a condition for copying a data group from outside the memory, which has a column address selection line and a column address selection means for selecting a signal amplification means connected to the input / output line from the amplification means A semiconductor memory device further comprising: means and a copy address generating means for generating a copy source address and a copy destination address of the data group. 7. The copy condition setting means includes at least a start address setting means for setting start addresses of a copy source and a copy destination of a data group, and a data amount setting means for setting a data amount of a data group to be copied. Claim 6
The semiconductor memory device according to 1. 8. The semiconductor memory device according to claim 6, wherein an input / output line for inputting / outputting data to / from said memory block, a column address selection line, and a column address selection means are duplicated. 9. A plurality of word lines, a plurality of data line pairs,
A memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of signal amplifying means connected to each data line pair of the plurality of data line pairs. A plurality of memory blocks each including a plurality of memory blocks, a dual I / O line for simultaneously inputting and outputting data to and from the memory blocks, and a word line selecting means for selecting a desired word line of the plurality of word lines. , A semiconductor memory comprising: a duplicated column address selection line and a duplicated column address selection means for selecting a signal amplification means connected to the duplicated input / output line from the plurality of signal amplification means. apparatus. 10. The semiconductor memory device according to claim 1, wherein the memory array is a dynamic memory.