JPH0831168A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPH0831168A
JPH0831168A JP6160904A JP16090494A JPH0831168A JP H0831168 A JPH0831168 A JP H0831168A JP 6160904 A JP6160904 A JP 6160904A JP 16090494 A JP16090494 A JP 16090494A JP H0831168 A JPH0831168 A JP H0831168A
Authority
JP
Japan
Prior art keywords
memory
data line
data
word lines
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6160904A
Other languages
Japanese (ja)
Inventor
Yoshinobu Nakagome
儀延 中込
Takao Watabe
隆夫 渡部
Original Assignee
Hitachi Ltd
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, 株式会社日立製作所 filed Critical Hitachi Ltd
Priority to JP6160904A priority Critical patent/JPH0831168A/en
Publication of JPH0831168A publication Critical patent/JPH0831168A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable performing arithmetic processings and the movement processings of data in the inside of a memory without interposing a processor at high speed and with low electric power by amplifying information via a sense-amplifier after information of two memory cells are simultaneously read out on a data line. CONSTITUTION:A memory array MA is constituted of memory cells MC0 to MC3 arranged at intersected points between plural word lines W0 to W3 and plural data line pairs Dj, DjB and reference memories RC0 to RC3 for arithmetics arranged at intersected points between plural word lines RW0 to RW3, and plural data line pairs Dj, DjB. A reference word line driving circuit RXD is connected with word lines RW0 to RW3. A sense-amplifier SAA is constituted of plural sense-amplifiers SAj performing the precharges of data line pairs DjB and amplifying read out signals and input and output gates 1%. Since the of electric charges of memory cells MC0 and MC1 occurs on a data line Dj, the AND or the OR between two information is obtained via the sense- amplifier SAA.

Description

【発明の詳細な説明】Detailed Description of the Invention
【0001】[0001]
【産業上の利用分野】本発明は半導体記憶装置に係り、
特にメモリ内部で並列に論理演算を行う機能や、メモリ
ブロック間で高速にデータのコピーを行う機能を内蔵す
る半導体記憶装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a function of performing a logical operation in parallel in a memory and a function of copying data at high speed between memory blocks.
【0002】[0002]
【従来の技術】パーソナルコンピュータやワークステー
ション等のグラフィックス処理を高速に行うためには、
表示メモリ中のあるブロック領域をビット単位でデータ
転送するビットブリット転送(BitBlt : bit block tran
sfer)機能が重要である。この機能は、移動元の座標と
幅、高さ、および移動先の座標を指定するだけで、画面
上の矩形領域をコピーする機能である。その際、移動と
ともに、移動先とのAND、ORなどの論理演算処理が
必要になる。こうした演算処理をCPUが行うと、グラ
フィックスVRAM (VRAM=Video Random Access Memor
y) のデータの読み書きが膨大になって、システムの性
能低下を生ずるため、VRAMへの読み書きを行うグラ
フィックス・プロセッサを別に設けてCPUの負担を軽
減するような構成が一般的になっている。例えば、この
種の構成は、バイト、1993年11月号、第229頁
〜第236頁(BYTE, November 1993, pp.229-236)に記
載されている。
2. Description of the Related Art In order to perform high-speed graphics processing for personal computers, workstations, etc.,
Bit block transfer (BitBlt: bit block tran) that transfers data to a block area in display memory in bit units
sfer) function is important. This function is a function of copying a rectangular area on the screen by simply specifying the coordinates of the movement source, the width, the height, and the coordinates of the movement destination. At that time, along with the movement, logical operation processing such as AND and OR with the movement destination is required. When the CPU performs such arithmetic processing, the graphics VRAM (VRAM = Video Random Access Memor)
Since the reading and writing of the data of y) becomes enormous and the performance of the system is deteriorated, it is general to provide a graphics processor for reading and writing to the VRAM separately to reduce the load on the CPU. . For example, this type of configuration is described in Bite, November 1993, pages 229-236 (BYTE, November 1993, pp.229-236).
【0003】また、VRAMに論理演算機能を設けて、
グラフィックス・プロセッサとVRAM間での読み書き
の回数を減らすような例が知られている。こうしたVR
AMとしては、例えば、1992年9月発行の日立IC
メモリ・データブック(1)−SRAM,PSRAM,
専用メモリ,ECL RAM、の第501頁−第521
頁、製品型名HM53462が挙げられる。この従来例
では、VRAMに既に蓄積されている情報と外部からの
入力データとの論理演算を行ってVRAMに書き戻すた
めに、入力ピンとメモリアレーの間に入力ピンと同数の
論理演算回路を設けている。論理演算の際には、メモリ
アレーからデータを読み出し、入力データとの論理演算
を行った後、メモリアレーに書き戻す、いわゆるリード
・モディファイ・ライト(Read Modified Write)動作を
行う。これにより、メモリから外部にデータを読みだし
てグラフィックス・プロセッサで演算を行う必要がなく
なり、VRAMとグラフィックス・プロセッサ間のデー
タ転送回数を減少させることが可能となる。なお、メモ
リアレー上で、メモリセル間のコピーを行う技術は特開
昭61−94290号公報に開示されている。
Further, by providing the VRAM with a logical operation function,
Examples are known in which the number of reads and writes between the graphics processor and VRAM is reduced. VR like this
As the AM, for example, Hitachi IC issued in September 1992
Memory data book (1) -SRAM, PSRAM,
Dedicated Memory, ECL RAM, pages 501-521
Page, product model name HM53462. In this conventional example, in order to perform a logical operation between information already stored in the VRAM and input data from the outside and write back to the VRAM, the same number of logical operation circuits as the input pins are provided between the input pin and the memory array. There is. At the time of the logical operation, a so-called read modified write operation of reading data from the memory array, performing a logical operation with the input data, and writing back to the memory array is performed. As a result, it is not necessary to read the data from the memory to the outside and perform the calculation in the graphics processor, and the number of data transfers between the VRAM and the graphics processor can be reduced. A technique for copying between memory cells on a memory array is disclosed in Japanese Patent Laid-Open No. 61-94290.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、前述し
た従来技術によれば、前者のVRAMへの読み書きを行
うグラフィックス・プロセッサを別に設ける場合には、
演算を行う度にメモリの中にある情報を逐一外部に読み
出して来る必要があるため、演算速度がメモリのアクセ
ス時間によって制限されるという問題点があった。
However, according to the above-mentioned prior art, when a graphics processor for reading / writing the former VRAM is separately provided,
Since it is necessary to read out the information in the memory one by one every time the calculation is performed, there is a problem that the calculation speed is limited by the access time of the memory.
【0005】また、後者のVRAMに論理演算機能を設
ける従来例では、メモリチップ内でのコピー機能を有し
ていないため、ビットブリット転送処理に対するグラフ
ィックス・プロセッサの負担軽減の効果が少ないという
問題点があった。
Further, in the latter conventional example in which the logical operation function is provided in the VRAM, since it does not have the copy function in the memory chip, the effect of reducing the load on the graphics processor for the bit blit transfer processing is small. There was a point.
【0006】そこで、本発明の目的は、グラフィックス
・プロセッサの介在なしに、メモリ内部での演算処理や
データのコピー処理を高速かつ低電力に行うことができ
る演算機能やデータコピー機能を有する半導体記憶装置
を提供することにある。
Therefore, an object of the present invention is to provide a semiconductor having an arithmetic function and a data copy function capable of performing an arithmetic process in a memory and a data copy process at high speed and low power without the intervention of a graphics processor. A storage device is provided.
【0007】[0007]
【課題を解決するための手段】上記課題を解決するため
に、本発明に係る半導体記憶装置は、複数のワード線
と、複数のデータ線対と、上記複数のワード線と上記複
数のデータ線対の所望の交点に配置された複数のメモリ
セルを有するメモリアレーと、上記複数のデータ線対の
各データ線対に接続された複数の信号増幅手段と、上記
複数のデータ線対の各データ線対に接続された複数の参
照信号発生手段とを有する半導体記憶装置において、上
記複数のワード線の所望のワード線を選択するワード線
選択手段をさらに具備し、上記ワード線選択手段が上記
複数のデータ線対の1つのデータ線対の一方のデータ線
に少なくとも2つのメモリセルからの情報を同時に読み
出した後、上記信号増幅手段により上記1つのデータ線
対の上記一方のデータ線に現れた信号を増幅することを
特徴とする。
In order to solve the above problems, a semiconductor memory device according to the present invention has a plurality of word lines, a plurality of data line pairs, a plurality of word lines and a plurality of data lines. A memory array having a plurality of memory cells arranged at desired intersections of a pair, a plurality of signal amplifying means connected to each data line pair of the plurality of data line pairs, and each data of the plurality of data line pairs A semiconductor memory device having a plurality of reference signal generating means connected to a line pair, further comprising word line selecting means for selecting a desired word line of the plurality of word lines, wherein the word line selecting means has the plurality of word line selecting means. Information from at least two memory cells are simultaneously read to one data line of one data line pair of the data line pair, and the one data line pair of the one data line pair is read by the signal amplifying means. Wherein the amplifying the signal appearing on line.
【0008】上記半導体記憶装置において、参照信号発
生手段は、複数の参照ワード線と複数の前記データ線対
の各交点に配置された参照メモリセルからなる参照メモ
リセルアレーと、前記参照ワード線の駆動回路とから構
成すれば好適である。
In the above semiconductor memory device, the reference signal generating means includes a reference memory cell array composed of reference memory cells arranged at respective intersections of the plurality of reference word lines and the plurality of data line pairs, and the reference word lines. It is preferable to be configured with a drive circuit.
【0009】また、上記半導体記憶装置において、ワー
ド線選択手段は、少なくとも2つのワード線を同時に独
立して選択する手段である。
In the above semiconductor memory device, the word line selecting means is a means for simultaneously and independently selecting at least two word lines.
【0010】また、本発明に係る半導体記憶装置は、複
数のワード線と、複数のデータ線対と、上記複数のワー
ド線と上記複数のデータ線対の所望の交点に配置された
複数のメモリセルを有するメモリアレーと、上記複数の
データ線対の各データ線対に接続された複数の参照信号
発生手段と、各々2つの入力を有する複数の信号増幅手
段とを有する半導体記憶装置において、上記複数のデー
タ線対のうち少なくとも2つを並列に1つの信号増幅手
段の2つの入力に接続する手段と、上記複数のデータ線
対の各々に対して少なくとも1つずつのメモリセルから
の情報を同時に読み出すようにしたワード線選択手段と
をさらに具備し、上記ワード線選択手段が上記複数の信
号増幅手段の入力の一方に少なくとも2つのメモリセル
からの情報を同時に読み出した後、上記信号増幅手段に
より信号を増幅することを特徴とする。
Also, the semiconductor memory device according to the present invention includes a plurality of word lines, a plurality of data line pairs, and a plurality of memories arranged at desired intersections of the plurality of word lines and the plurality of data line pairs. In a semiconductor memory device having a memory array having cells, a plurality of reference signal generating means connected to each data line pair of the plurality of data line pairs, and a plurality of signal amplifying means each having two inputs, Means for connecting at least two of the plurality of data line pairs in parallel to two inputs of one signal amplifying means, and information from at least one memory cell for each of the plurality of data line pairs. And a word line selecting means for reading simultaneously, wherein the word line selecting means simultaneously inputs information from at least two memory cells to one of the inputs of the plurality of signal amplifying means. After reading, characterized in that to amplify the signal by the signal amplifying means.
【0011】上記半導体記憶装置において、複数のデー
タ線対のうち少なくとも2つを並列に1つの信号増幅手
段の2つの入力に接続する手段は、一次元に配列された
信号増幅手段の両側に配された第1および第2のメモリ
セルアレーと信号増幅手段との間に2列に設けられ、第
1のメモリセルアレーのデータ線対の1つと第2のメモ
リセルアレーのデータ線対の1つを1つの信号増幅手段
に同時に接続するスイッチ手段とすれば好適である。
In the above semiconductor memory device, the means for connecting at least two of the plurality of data line pairs in parallel to the two inputs of one signal amplifying means are arranged on both sides of the one-dimensionally arranged signal amplifying means. One of the data line pair of the first memory cell array and one of the data line pair of the second memory cell array are provided in two columns between the first and second memory cell arrays and the signal amplifying means. It is preferable that the two are switch means for simultaneously connecting to one signal amplifying means.
【0012】さらに本発明に係る半導体記憶装置は、複
数のワード線と、複数のデータ線対と、上記複数のワー
ド線と上記複数のデータ線対の所望の交点に配置された
複数のメモリセルを有するメモリアレーと、上記複数の
データ線対の各データ線対に接続された複数の信号増幅
手段とから構成された複数のメモリブロックと、該メモ
リブロックへのデータの入出力を行なう入出力線と、上
記複数のワード線の所望のワード線を選択するワード線
選択手段と、上記複数の信号増幅手段のうちから上記入
出力線に接続する信号増幅手段を選択する列アドレス選
択線と列アドレス選択手段とを有し、メモリ外部からの
データ群のコピーのための条件を設定するコピー条件設
定手段と、前記データ群のコピー元およびコピー先のア
ドレスを発生するコピーアドレス発生手段とをさらに具
備することを特徴とする。
Further, the semiconductor memory device according to the present invention includes a plurality of word lines, a plurality of data line pairs, and a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs. And a plurality of memory blocks each comprising a memory array having a plurality of data line pairs, and a plurality of signal amplifying means connected to each of the plurality of data line pairs, and input / output for inputting / outputting data to / from the memory blocks. Line, a word line selection means for selecting a desired word line of the plurality of word lines, and a column address selection line and a column for selecting a signal amplification means connected to the input / output line from the plurality of signal amplification means. Copy condition setting means for setting a condition for copying a data group from the outside of the memory, and address generating means for generating a copy source and a copy destination of the data group. Characterized in that it further comprises a peak address generating means.
【0013】このように構成した半導体記憶装置におい
て、前記コピー条件設定手段は、データ群のコピー元お
よびコピー先の先頭アドレスを設定する先頭アドレス設
定手段と、コピーするデータ群のデータ量を設定するデ
ータ量設定手段とを少なくとも有する。
In the semiconductor memory device thus configured, the copy condition setting means sets the start address setting means for setting the start addresses of the copy source and copy destination of the data group and the data amount of the data group to be copied. At least data amount setting means.
【0014】また、上記半導体記憶装置において、前記
メモリブロックへのデータの入出力を行う入出力線と、
列アドレス選択線と、列アドレス選択手段とを各々二重
化して構成すれば好適である。
In the semiconductor memory device, an input / output line for inputting / outputting data to / from the memory block,
It is preferable that the column address selection line and the column address selection means are duplicated.
【0015】さらに、本発明に係る半導体記憶装置は、
複数のワード線と、複数のデータ線対と、上記複数のワ
ード線と上記複数のデータ線対の所望の交点に配置され
た複数のメモリセルを有するメモリアレーと、上記複数
のデータ線対の各データ線対に接続された複数の信号増
幅手段とから構成された複数のメモリブロックと、該メ
モリブロックへのデータの入出力を同時並列に行なう二
重化した入出力線と、上記複数のワード線の所望のワー
ド線を選択するワード線選択手段と、上記複数の信号増
幅手段のうちから上記二重化した入出力線に接続する信
号増幅手段を選択する二重化した列アドレス選択線と二
重化した列アドレス選択手段、とを具備することを特徴
とする。
Further, the semiconductor memory device according to the present invention is
A plurality of word lines, a plurality of data line pairs, a memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of data line pairs A plurality of memory blocks each composed of a plurality of signal amplifying means connected to each data line pair; a duplicated input / output line for simultaneously inputting / outputting data to / from the memory blocks; and a plurality of word lines Of word line selecting means for selecting a desired word line and a signal amplifying means connected to the duplicated input / output line from the plurality of signal amplifying means, and a duplicated column address selection line and a duplicated column address selection Means and are provided.
【0016】また、上記いずれの半導体記憶装置におい
ても、メモリアレーはダイナミックメモリで構成するこ
とができる。
Further, in any of the above semiconductor memory devices, the memory array can be configured by a dynamic memory.
【0017】[0017]
【作用】本発明に係る半導体記憶装置によれば、複数の
ワード線の所望のワード線を選択するワード線選択手段
が複数のデータ線対の1つのデータ線対の一方のデータ
線に少なくとも2つのメモリセルからの情報を同時に読
み出した後、信号増幅手段により上記1つのデータ線対
の上記一方のデータ線に現れた信号を増幅することによ
って、上記少なくとも2つのメモリセルの演算結果を得
ることができる。
According to the semiconductor memory device of the present invention, the word line selecting means for selecting a desired word line of the plurality of word lines has at least two data lines in one data line pair of the plurality of data line pairs. Obtaining the operation result of the at least two memory cells by simultaneously reading information from one memory cell and then amplifying the signal appearing on the one data line of the one data line pair by the signal amplifying means. You can
【0018】上記半導体記憶装置において、複数のデー
タ線対の各デ−タ線対に接続された複数の参照信号発生
手段は、複数の参照ワード線と複数の前記データ線対の
各交点に配置された参照メモリセルからなる参照メモリ
セルアレーと、前記参照ワード線の駆動回路とからな
り、演算モードに応じた演算用の参照信号を発生する。
データ線対の一方の少なくとも2つのメモリセルを、例
えば、各ワード線に少なくとも2つの並列接続されたワ
ード線選択手段である行デコーダにより同時に駆動して
接続し、データ線対の一方に現れたメモリセルの電荷量
の和と、データ線対の他方に現れた前記参照信号とを信
号増幅手段、すなわちセンスアンプへ入力することによ
り、演算モードに対応した演算結果を得ることができ
る。
In the above semiconductor memory device, the plurality of reference signal generating means connected to each data line pair of the plurality of data line pairs are arranged at each intersection of the plurality of reference word lines and the plurality of data line pairs. The reference memory cell array including the reference memory cells and the drive circuit for the reference word line generate a reference signal for operation according to the operation mode.
At least two memory cells of one of the data line pairs are simultaneously driven and connected by, for example, at least two row decoders, which are word line selection means connected in parallel to each word line, and appear in one of the data line pairs. The calculation result corresponding to the calculation mode can be obtained by inputting the sum of the charge amounts of the memory cells and the reference signal appearing on the other side of the data line pair to the signal amplifying means, that is, the sense amplifier.
【0019】また、スイッチ手段により、信号増幅手段
を共有する第1および第2のメモリセルアレーすなわち
左右のメモリセルアレー同志のデータ線対との間を接続
する場合は、左のメモリセルアレーのメモリセルは左の
行デコーダにより左の一方のデータ線に、右のメモリセ
ルアレーのメモリセルは右の行デコーダにより右の一方
のデータ線にそれぞれ接続され、かつ、左の参照ワード
線の駆動回路により参照メモリが左の他方のデータ線
に、右の参照ワード線の駆動回路により参照メモリが右
の他方のデータ線にそれぞれ接続されているので、これ
らのデータ線対間を左右のスイッチ手段により接続する
ことにより、データ線対の一方に現われたメモリセルの
電荷の和と、他方に現われた参照メモリセルの電荷の和
が、共有する信号増幅手段すなわち共通接続されたセン
スアンプへ入力されて演算モードに対応した演算結果を
得ることができる。従って、センスアンプを挟む2つの
メモリセルアレー間で演算を行うことができる。
When the switch means connects between the first and second memory cell arrays sharing the signal amplifying means, that is, the data line pairs of the left and right memory cell arrays, the memory cell array on the left side is connected. The memory cell is connected to the left data line by the left row decoder, the memory cell in the right memory cell array is connected to the right data line by the right row decoder, and the left reference word line is driven. The reference memory is connected to the other data line on the left by the circuit, and the reference memory is connected to the other data line on the right by the drive circuit for the reference word line on the right. The connection between the memory cell and the reference memory cell on one side of the data line pair and the sum of the charges on the other side and the reference memory cell on the other side increase the shared signal. It is possible to obtain an operation result corresponding to the operation mode is inputted to the unit or common-connected sense amplifier. Therefore, calculation can be performed between two memory cell arrays that sandwich the sense amplifier.
【0020】このように、ワード線につながるメモリセ
ル群と他のワード線につながるメモリセル群との間での
演算は、参照ワード線につながる参照メモリセル群と他
の参照ワード線につながる参照メモリセル群との間で得
られる参照信号が接続されたそれぞれのデータ線対間の
センスアンプでの比較だけなので、並列に行うことが可
能となる。従って、メモリアレーから情報を読み出すこ
となく論理演算を行うことができるようになる。
As described above, in the operation between the memory cell group connected to the word line and the memory cell group connected to another word line, the reference memory cell group connected to the reference word line and the reference connected to another reference word line. Since the reference signals obtained between the memory cell group and the respective data line pairs to which the reference signals are connected are only compared by the sense amplifier, it is possible to perform them in parallel. Therefore, the logical operation can be performed without reading the information from the memory array.
【0021】また、複数のメモリブロックを備えるメモ
リにおいて、データ群のコピー元およびコピー先の先頭
アドレスを設定する設定手段とコピーするデータ群のデ
ータ量を設定するデータ量設定手段とから成るコピー条
件設定手段と、データ群のコピー元およびコピー先のア
ドレスを発生する発生手段と、前記複数のメモリブロッ
ク間でデータ群の制御を行うコピー制御手段とを備える
ことにより、グラフィックス・プロセッサから命令とコ
ピーのための情報をメモリに送るだけで、メモリ内でコ
ピーのための条件設定及びコピー元およびコピー先のア
ドレスを発生しメモリブロック間でのデータ群の制御を
行うので、グラフィックス・プロセッサとメモリ間での
読み書きをせずにコピー処理を行うことができる結果、
高速かつ低電力にデータのコピーを行うことができる。
In a memory having a plurality of memory blocks, a copy condition including setting means for setting the start addresses of the copy source and copy destination of the data group and data amount setting means for setting the data amount of the data group to be copied. By providing a setting means, a generation means for generating a copy source address and a copy destination address of the data group, and a copy control means for controlling the data group among the plurality of memory blocks, an instruction from the graphics processor can be obtained. By sending the information for copying to the memory, the condition setting for copying and the address of the copy source and the copy destination are generated in the memory to control the data group between the memory blocks. As a result of being able to perform copy processing without reading and writing between memories,
Data can be copied at high speed and low power.
【0022】さらに、複数のメモリブロックを備えるメ
モリにおいて、メモリーアレーへの入出力線を読み出し
用と書き込み用に二重化すると共に列アドレス選択信号
と列選択回路も読み出し用と書き込み用に二重化し、さ
らに書き込み用入出力線を読み出し用コモンデータ線対
または書き込み用コモンデータ線対に切り替え接続する
よう構成することにより、通常のメモリ動作の他に、メ
モリ内のメモリブロック間のデータコピーを外部に読み
だすこと無く行うことができる。
Further, in a memory having a plurality of memory blocks, the input / output lines to the memory array are duplicated for reading and writing, and the column address selection signal and the column selecting circuit are also duplicated for reading and writing. By configuring the write I / O line to be switched and connected to the read common data line pair or the write common data line pair, in addition to normal memory operation, the data copy between the memory blocks in the memory can be read externally. It can be done without issuing.
【0023】[0023]
【実施例】【Example】
<実施例1>以下、図1乃至図4を用いて、本発明に係
る半導体記憶装置について詳細に説明する。図1は、本
発明に係る半導体記憶装置の一実施例を示す演算機能つ
きメモリの構成図である。図1において、参照符号MA
はメモリセルアレー、SAAはセンスアンプアレー、X
D1およびXD2はXデコーダ、YDはYデコーダ、A
MPは読み出し用のアンプ、DOBは出力バッファ、W
BUFは書き込みバッファを示す。
<Embodiment 1> Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to FIGS. FIG. 1 is a block diagram of a memory with an arithmetic function showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, reference numeral MA
Is a memory cell array, SAA is a sense amplifier array, X
D1 and XD2 are X decoders, YD is Y decoder, A
MP is a reading amplifier, DOB is an output buffer, W
BUF indicates a write buffer.
【0024】メモリセルアレーMAは、複数のワード線
(ここでは一部のみ示す)W0〜W3と複数のデータ線
対(ここでは一部のみ示す)Dj、DjBとの交点に配
されたメモリセル(ここでは一部のみ示す)MC0〜M
C3と、複数の演算用参照ワード線(ここでは一部のみ
示す)RW0〜RW3と複数のデータ線対Dj、DjB
との交点に配された演算用参照メモリセル(ここでは一
部のみ示す)RC0〜RC3とから構成される。また、
複数の演算用参照ワード線RW0〜RW3には、参照ワ
ード線駆動回路RXDが接続される。なお、参照符号D
jB、IOBの英文字”B”は、それぞれ対になるD
j、IOの否定の関係(又は相補の関係)を表わす。
The memory cell array MA is a memory cell arranged at an intersection of a plurality of word lines (only part of which is shown here) W0 to W3 and a plurality of data line pairs (only part of which is shown here) Dj and DjB. (Only a part is shown here) MC0-M
C3, a plurality of operation reference word lines (only part of which are shown here) RW0 to RW3, and a plurality of data line pairs Dj, DjB
Comprising arithmetic reference memory cells (only a part of which are shown here) RC0 to RC3 arranged at intersections with. Also,
A reference word line drive circuit RXD is connected to the plurality of calculation reference word lines RW0 to RW3. Note that reference numeral D
The letter "B" in jB and IOB is a pair D
Represents a negative relationship (or complementary relationship) between j and IO.
【0025】センスアンプアレーSAAは、データ線対
Dj、DjBのプリチャージや読み出された信号を増幅
するための複数のセンスアンプSAjと、データ線対D
j、DjBを入出力線対IO、IOBに接続するための
複数の入出力ゲートIOGとから構成される。ここで、
入出力ゲートIOGはMOSトランジスタM1、M2か
ら構成され、それぞれのMOSトランジスタM1、M2
のゲートはYアドレス選択信号YSjに接続される。
The sense amplifier array SAA includes a plurality of sense amplifiers SAj for precharging the data line pairs Dj and DjB and amplifying the read signals, and the data line pair DA.
It is composed of a plurality of input / output gates IOG for connecting j and DjB to the input / output line pairs IO and IOB. here,
The input / output gate IOG is composed of MOS transistors M1 and M2.
Is connected to the Y address selection signal YSj.
【0026】なお、このように構成される本発明に係る
半導体記憶装置において、メモリセルMC0〜MC3と
しては一般的なダイナミックメモリに用いられている1
T−1C型のセル、すなわち1つのMOSトランジスタ
と1つの蓄積容量を用いるが、電荷を蓄積することによ
って記憶する構成であれば、これに限るものではない。
また、センスアンプSAjは、データ線対Dj、DjB
間の微小電圧差を増幅する信号増幅手段であれば、公知
の差動構成の増幅回路を利用できるし、勿論、一般的な
ダイナミックメモリに用いられている回路構成と同じで
あっても良い。従って、演算用参照メモリセルとその参
照ワード線駆動回路RXDとを除く他の回路は、一般的
なダイナミックメモリに用いられている回路で構成でき
る。
In the semiconductor memory device according to the present invention having such a structure, the memory cells MC0 to MC3 used in a general dynamic memory are 1
Although a T-1C type cell, that is, one MOS transistor and one storage capacitor is used, the present invention is not limited to this as long as it is configured to store charges by storing them.
In addition, the sense amplifier SAj has a data line pair Dj, DjB.
A known differential amplifying circuit can be used as long as it is a signal amplifying unit that amplifies a minute voltage difference between them, and of course, it may have the same circuit configuration as that used in a general dynamic memory. Therefore, the circuits other than the calculation reference memory cell and the reference word line drive circuit RXD can be configured by circuits used in general dynamic memories.
【0027】図1に示す構成では、データ線Djに接続
する2つのメモリセル(例えば、MC0とMC1)、ま
たは対となるデータ線DjBに接続する2つのメモリセ
ル(例えば、MC2とMC3)の記憶情報の演算結果
を、それぞれ複数のデータ線対DjまたはDjBに接続
されたメモリセルに対して同時に得ることができる。2
つのメモリセルの演算結果を得るために、2つのワード
線、例えば、W0とW1を選択する。さらに、例えばデ
ータ線Djに接続する2つのメモリセルMC0、MC1
の記憶情報の演算を行う場合には、対となるデータ線D
jBに接続する2つの演算用参照メモリセルRC0、R
C1を演算用参照ワード線RW0、RW1により選択す
る。同様に、ワード線W2、W3を選択して、データ線
DjBに接続する2つのメモリセルMC2、MC3の記
憶情報の演算を行う場合には、対となるデータ線Djに
接続する2つの演算用参照メモリセルRC2、RC3を
演算用参照ワード線RW2、RW3により選択する。
In the configuration shown in FIG. 1, two memory cells (for example, MC0 and MC1) connected to the data line Dj or two memory cells (for example, MC2 and MC3) connected to the paired data line DjB are provided. The calculation result of the stored information can be simultaneously obtained for the memory cells connected to the plurality of data line pairs Dj or DjB, respectively. Two
Two word lines, for example W0 and W1, are selected to obtain the operation result of one memory cell. Further, for example, two memory cells MC0 and MC1 connected to the data line Dj
When the stored information is calculated, the pair of data lines D
Two calculation reference memory cells RC0, R connected to jB
C1 is selected by the operation reference word lines RW0 and RW1. Similarly, when the word lines W2 and W3 are selected and the storage information of the two memory cells MC2 and MC3 connected to the data line DjB is calculated, the two calculation lines connected to the paired data line Dj are used. The reference memory cells RC2 and RC3 are selected by the operation reference word lines RW2 and RW3.
【0028】図2に、演算用参照メモリセルとその参照
ワード線の駆動回路RXDの具体的な構成例を示す。こ
こでは、演算用参照メモリセルRC0とRC1の構成の
みを示したが、演算用参照メモリセルRC2とRC3も
これらと同様の構成である。図2において、参照符号M
10〜M13はNチャネルMOSFET(以下、NMO
Sトランジスタと称する)、C10とC11は蓄積容
量、PLは共通プレート電極、INV1〜INV3はイ
ンバータを示す。ここで、共通プレート電極PLは、高
電位側電源電圧VCC(不図示)の半分の電位、すなわ
ちVCC/2の電位に固定されている。演算用参照メモ
リセルRC0はメモリセルMC0と同様の構成であり、
蓄積容量C10の値もメモリセルMC0の蓄積容量の値
と実質的に同一である。
FIG. 2 shows a specific configuration example of the driving reference memory cell and the drive circuit RXD for the reference word line thereof. Here, only the configurations of the operation reference memory cells RC0 and RC1 are shown, but the operation reference memory cells RC2 and RC3 have the same configuration. In FIG. 2, reference numeral M
10 to M13 are N-channel MOSFETs (hereinafter referred to as NMO
C10 and C11 are storage capacitors, PL is a common plate electrode, and INV1 to INV3 are inverters. Here, the common plate electrode PL is fixed to a half potential of the high potential side power supply voltage VCC (not shown), that is, a potential of VCC / 2. The calculation reference memory cell RC0 has the same configuration as the memory cell MC0,
The value of the storage capacity C10 is also substantially the same as the value of the storage capacity of the memory cell MC0.
【0029】演算用参照メモリセルRC1は、通常のメ
モリセルMC1にNMOSトランジスタM12を追加
し、演算用参照メモリセルRC1の蓄積ノードの電位を
外部から設定できるようにしている。すなわち、演算モ
ード設定信号SETを印加したときにNMOSトランジ
スタM12が導通し、電圧VMAが蓄積容量C11に書
き込まれる。外部から与えられるモード設定電圧信号V
Mは、モード設定のタイミング信号であるモード設定信
号MSを印加することによりインバータINV2の入力
に書き込まれる。この電圧は、インバータINV2とI
NV3で構成されるラッチによって、電源が入っている
間は保持される。インバータINV1の入力はインバー
タINV2の出力に接続され、インバータINV1の出
力に電圧VMAが出力される。
The reference memory cell for calculation RC1 has an NMOS transistor M12 added to the normal memory cell MC1 so that the potential of the storage node of the reference memory cell for calculation RC1 can be set from the outside. That is, when the operation mode setting signal SET is applied, the NMOS transistor M12 becomes conductive and the voltage VMA is written in the storage capacitor C11. Mode setting voltage signal V given from the outside
M is written to the input of the inverter INV2 by applying the mode setting signal MS which is a timing signal for mode setting. This voltage is applied to the inverters INV2 and I
A latch composed of NV3 holds it while the power is on. The input of the inverter INV1 is connected to the output of the inverter INV2, and the voltage VMA is output to the output of the inverter INV1.
【0030】従って、外部から与えられたモード設定電
圧信号VMに応じて、電圧VMAの値は電源電圧のいず
れか、すなわち高電位側電源電圧VCC又は低電位側電
源電圧VSS(不図示)となる。演算用参照ワード線R
W1は、メモリセルのワード線W1と同じタイミングで
駆動することによって、データ線対DjとDjBの電圧
差に対応した演算結果がセンスアンプSAjで得られ
る。一方、演算用参照ワード線RW0には常に高い電圧
を印加して、NMOSトランジスタM10が導通したま
まとなるようにしておく。なお、演算用参照メモリセル
RC0を、演算用参照メモリセルRC1と同様にNMO
SトランジスタM12を接続した構成とすることも可能
であるが、その場合には演算用参照メモリセルRC0に
接続されるNMOSトランジスタM12を常に非導通と
なるようにしておけば良い。
Therefore, the value of the voltage VMA becomes one of the power supply voltages, that is, the high-potential-side power supply voltage VCC or the low-potential-side power supply voltage VSS (not shown), according to the mode setting voltage signal VM supplied from the outside. . Calculation reference word line R
By driving W1 at the same timing as the word line W1 of the memory cell, the operation result corresponding to the voltage difference between the data line pair Dj and DjB is obtained by the sense amplifier SAj. On the other hand, a high voltage is always applied to the calculation reference word line RW0 so that the NMOS transistor M10 remains conductive. The arithmetic reference memory cell RC0 is similar to the arithmetic reference memory cell RC1 in NMO.
The S transistor M12 may be connected, but in that case, the NMOS transistor M12 connected to the arithmetic reference memory cell RC0 may be kept non-conductive at all times.
【0031】本実施例の演算機能つきメモリにおいて
は、信号の演算を行う場合、2つのメモリセルと対をな
す2つの演算用参照メモリセルを同時に選択する。例え
ば、メモリセルMC0とMC1に記憶されている情報の
演算を行う場合には、演算用参照メモリセルRC0とR
C1を同時に選択する。この時のデータ線対Dj、Dj
Bの各電圧VDj、VDjBの変化を図3に示す。この
場合、データ線DjにはメモリセルMC0とMC1の電
荷の和が出現するので、蓄積されている情報の組合せに
応じて、3通りの電圧が出現する。すなわち、メモリセ
ルMC0とMC1に蓄積されている電圧が、ともに高
い電圧”1”の場合→Dj(1,1)、一方が高い電
圧”1”で他方が低い電圧”0”の場合→Dj(0,
1)またはDj(1,0)、ともに低い電圧”0”の
場合→Dj(0,0)、の3通りである。
In the memory with the arithmetic function of the present embodiment, when the arithmetic operation of the signal is performed, the two reference memory cells for arithmetic operation which are paired with the two memory cells are simultaneously selected. For example, when the information stored in the memory cells MC0 and MC1 is calculated, the reference memory cells RC0 and R0 for calculation are used.
Select C1 at the same time. Data line pair Dj, Dj at this time
FIG. 3 shows changes in the B voltages VDj and VDjB. In this case, since the sum of the charges of the memory cells MC0 and MC1 appears on the data line Dj, three kinds of voltages appear depending on the combination of the stored information. That is, when the voltages stored in the memory cells MC0 and MC1 are both high voltage “1” → Dj (1,1), when one is high voltage “1” and the other is low voltage “0” → Dj (0,
1) or Dj (1,0), both of which are low voltage “0” → Dj (0,0).
【0032】一方、参照データ線DjBには、演算用参
照メモリセルRC1に蓄積されている情報に応じて2通
りの電圧が出現する。何故ならば、前述したように演算
用参照ワード線RW0には常に高い電圧が印加されてい
るため、演算用参照メモリセルRC0に蓄積されている
電圧は共通プレート電位PLによる一定の電圧VCC/
2に、すなわち、演算用参照メモリセルRC0に蓄積さ
れている電荷は”1”と”0”の中間”1/2”に保持
されているからである。従って、演算用参照メモリセル
RC1に蓄積されている電圧が、’高い電圧”1”の
場合→DjB(1,1/2)、’低い電圧”0”の場
合→DjB(0,1/2)、の2通りである。演算用参
照メモリセルRC0に蓄積されている電荷は”1”と”
0”の中間であるから、DjB(1,1/2)の電圧は
Dj(1,1)とDj(0,1)あるいはDj(1,
0)との中間になる。また、DjB(0,1/2)の電
圧は、Dj(0,0)とDj(0,1)あるいはDj
(1,0)との中間になる。
On the other hand, two types of voltages appear on the reference data line DjB according to the information stored in the arithmetic reference memory cell RC1. Because a high voltage is always applied to the operation reference word line RW0 as described above, the voltage stored in the operation reference memory cell RC0 is constant voltage VCC /
This is because the electric charge accumulated in No. 2, that is, the electric charge accumulated in the arithmetic reference memory cell RC0 is held at "1/2" which is an intermediate between "1" and "0". Therefore, when the voltage stored in the arithmetic reference memory cell RC1 is “high voltage“ 1 ”→ DjB (1,1 / 2),“ low voltage “0” → DjB (0,1 / 2) ) And two. The charges accumulated in the calculation reference memory cell RC0 are "1" and "
Since it is in the middle of 0 ″, the voltage of DjB (1,1 / 2) is Dj (1,1) and Dj (0,1) or Dj (1,2).
It is in the middle of 0). Further, the voltage of DjB (0,1 / 2) is Dj (0,0) and Dj (0,1) or Dj (0,0).
It is in the middle of (1,0).
【0033】従って、参照情報としてVDjB=DjB
(1,1/2)を用いてセンスアンプを動作させると、
メモリセルMC0とMC1の蓄積されている情報の組合
せが、Dj(1,1)の組合せの場合のみデータ線Dj
が高い電圧に増幅され、それ以外の組合せでは低い電圧
になる。すなわち、2つのメモリセルMC0とMC1の
蓄積情報の論理積ANDを求めることができる。また、
参照情報としてVDjB=DjB(0,1/2)を用い
てセンスアンプを動作させると、Dj(0,0)の組合
せの場合のみデータ線Djが低い電圧に増幅され、それ
以外の組合せでは高い電圧になる。すなわち、2つのメ
モリセルMC0とMC1の蓄積情報の論理和ORを求め
ることができる。
Therefore, VDjB = DjB as reference information
When the sense amplifier is operated using (1, 1/2),
Only when the combination of information stored in the memory cells MC0 and MC1 is the combination of Dj (1,1), the data line Dj
Is amplified to a higher voltage, and other combinations result in a lower voltage. That is, the logical product AND of the storage information of the two memory cells MC0 and MC1 can be obtained. Also,
When the sense amplifier is operated using VDjB = DjB (0,1 / 2) as reference information, the data line Dj is amplified to a low voltage only in the combination of Dj (0,0), and is high in the other combinations. Become a voltage. That is, the logical sum OR of the storage information of the two memory cells MC0 and MC1 can be obtained.
【0034】このように、データ線対に接続されたセン
スアンプの参照電圧を設定するだけで、メモリセルの蓄
積情報のANDやORの演算機能を容易に実行すること
ができる。上記したことから理解されるように、新たに
設けた演算用参照ワード線の駆動回路RXDは、演算用
参照ワード線の1つだけを常に高レベルに保ち、論理積
ANDの演算を行う場合はそれ以外の演算用参照ワード
線をすべて高レベルにし、論理和ORの演算を行う場合
はそれ以外の演算用参照ワード線をすべて低レベルにす
るような動作を行う駆動回路である。
As described above, by simply setting the reference voltage of the sense amplifier connected to the data line pair, it is possible to easily execute the AND and OR operation functions of the information stored in the memory cells. As can be understood from the above description, the newly provided drive circuit RXD for the reference word line for calculation keeps only one of the reference word lines for calculation always at the high level and performs the operation of the AND operation. This is a drive circuit that sets all other operation reference word lines to a high level, and sets all other operation reference word lines to a low level when performing an OR operation.
【0035】図4は、図1に示した演算機能つきメモリ
の動作タイミングの一例を示すタイミング図である。な
お、この例ではデータ線対Dj、DjBの振幅が2V、
ワード線W0、W1及び演算用参照ワード線RW0、R
W1の振幅が3.5Vの場合について示しているが、こ
れらの値に限るものではない。
FIG. 4 is a timing chart showing an example of the operation timing of the memory with the arithmetic function shown in FIG. In this example, the amplitude of the data line pair Dj, DjB is 2V,
Word lines W0, W1 and reference word lines RW0, R for calculation
The case where the amplitude of W1 is 3.5 V is shown, but the value is not limited to these values.
【0036】さて、この例では、演算に先だって、演算
モードの設定とメモリセルへの書き込みを行っている。
先ず、時刻t0からt1にかけて、演算モード設定信号
SETを高レベルにし、演算用参照メモリセルRC1
に”1”または”0”を書き込む。今、OR演算である
と仮定し、”0”が書き込まれたとする。時刻t2から
t6にかけてワード線W0を高レベルにし、メモリセル
MC0に演算用データを書き込む。これは通常のDRA
Mと同様に、一旦読み出し動作を行った後、Yアドレス
選択信号YSjを高レベルにして、入出力線対IOとI
OBから入出力ゲートIOGを通して外部からの情報を
MC0に書き込んでいる。同様に、時刻t7からt11
にかけてワード線W1を高レベルにし、メモリセルMC
1にもう一方の演算用データを書き込む。なお、演算用
参照ワード線RW0は常に高レベルのままに保持してお
く。時刻t12からt15にかけて、ワード線W0、W
1、演算用参照ワード線RW1を同時に高レベルにし、
メモリセルMC0、MC1からデータ線Djへ、また演
算用参照メモリセルRC0、RC1から対となるデータ
線DjBへ、それぞれ蓄積電荷を流出させる。すなわ
ち、対となるデータ線DjBには参照情報としてVDj
B=DjB(0,1/2)の電圧が出現し、センスアン
プSAjの参照電圧が設定される。その後、通常のDR
AMと同様にセンスアンプSAjで増幅することによ
り、演算結果、この場合はMC0とMC1の情報のOR
演算の結果をデータ線対Dj、DjBの差の電圧として
得ることができる。
In this example, the operation mode is set and the memory cell is written before the operation.
First, from time t0 to t1, the operation mode setting signal SET is set to a high level, and the operation reference memory cell RC1
"1" or "0" is written in. Now, it is assumed that the OR operation is performed, and "0" is written. From time t2 to t6, the word line W0 is set to the high level and the operation data is written in the memory cell MC0. This is a normal DRA
Similar to M, after performing the read operation once, the Y address selection signal YSj is set to the high level to input / output line pair IO and I.
Information from the outside is written in MC0 from the OB through the input / output gate IOG. Similarly, from time t7 to t11
The word line W1 is set to the high level, and the memory cell MC
The other calculation data is written into 1. The calculation reference word line RW0 is always kept at the high level. From time t12 to t15, the word lines W0, W
1. The reference word line RW1 for calculation is set to high level at the same time,
The accumulated charges are caused to flow from the memory cells MC0 and MC1 to the data line Dj, and from the calculation reference memory cells RC0 and RC1 to the paired data line DjB. That is, VDj is used as reference information for the paired data line DjB.
A voltage of B = DjB (0,1 / 2) appears, and the reference voltage of the sense amplifier SAj is set. After that, the normal DR
By amplifying by the sense amplifier SAj as in the case of AM, the operation result, in this case, the OR of information of MC0 and MC1
The result of the calculation can be obtained as the voltage difference between the data line pair Dj and DjB.
【0037】以上、本実施例に示したように、本発明に
係る演算機能つきメモリによれば、新たに演算回路を設
けること無く、メモリセルMCn(n=0,1,……)
と同種の演算用参照メモリセルRCn(n=0,1,…
…)及びその参照ワード線の駆動回路RXDから構成さ
れる参照信号発生手段と、ワード線に並列接続した2つ
のXデコーダXD1、XD2とを付加するのみでワード
線単位で並列に論理演算を行うことができる。これによ
り、電力増大を最小限に抑えながら、演算速度を著しく
増大させることができる。
As described above, according to the memory with the arithmetic function of the present invention as shown in this embodiment, the memory cell MCn (n = 0, 1, ...) Is not provided with a new arithmetic circuit.
Reference memory cells RCn (n = 0, 1, ...
...) and its reference word line drive circuit RXD and reference signal generating means, and two X decoders XD1 and XD2 connected in parallel to the word line are only added to perform a logical operation in word line units in parallel. be able to. This makes it possible to significantly increase the calculation speed while minimizing the increase in power.
【0038】<実施例2>図5を用いて、本発明に係る
半導体記憶装置の第2の実施例を示す演算機能つきメモ
リについて説明する。前記実施例1では、2つのメモリ
セルの情報の演算を行う場合について説明したが、本発
明に係る演算機能つきメモリは、3つ以上のメモリセル
の情報の演算も同様に行うことができる。本実施例で
は、一例として3つのメモリセルの情報の演算を行う場
合について説明する。なお、構成としては、図1に示し
た構成と同様であるが、メモリセルを同時に3つ独立し
て選択するために、3つのXデコーダがワード線に並列
に接続される点が相違するだけであるので、構成図は省
略する。
<Embodiment 2> With reference to FIG. 5, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the case where the information of two memory cells is calculated has been described. However, the memory with a calculation function according to the present invention can similarly calculate the information of three or more memory cells. In this embodiment, as an example, a case where information of three memory cells is calculated will be described. Note that the configuration is similar to that shown in FIG. 1, except that three X decoders are connected in parallel to word lines in order to select three memory cells independently at the same time. Therefore, the configuration diagram is omitted.
【0039】図5は、3つのメモリセルの情報の演算を
行う場合のデータ線対DjおよびDjBの電圧変化を示
す図である。データ線Djには、3つのメモリセルに蓄
積されている情報にしたがって4通りの電圧が発生す
る。すなわち、3つのメモリセルの全部が高い電圧”
1”の場合、3つのメモリセルのうち1つが低い電
圧”0”の場合、3つのメモリセルのうち2つが低い
電圧”0”の場合、3つのメモリセルの全部が低い電
圧”0”の場合、である。
FIG. 5 is a diagram showing changes in the voltages of the data line pairs Dj and DjB when the information of three memory cells is calculated. Four kinds of voltages are generated on the data line Dj according to the information stored in the three memory cells. That is, all three memory cells have high voltage "
1 ”, one of the three memory cells has a low voltage“ 0 ”, two of the three memory cells have a low voltage“ 0 ”, and all three memory cells have a low voltage“ 0 ”. If,
【0040】一方、3つの演算用参照メモリセルの内の
1つは、先の実施例1の演算用参照メモリセルRC0と
同様にして、参照ワード線を高レベルに保ったままにし
ておき、”1”と”0”の中間の電荷”1/2”を得る
ようにしている。このため、参照データ線DjBには、
残りの2つの演算用参照メモリセルに蓄積されている情
報に応じて3通りの電圧が出現し得る。すなわち、’
残りの2つとも高い電圧”1”の場合、’どちらか1
つが低い電圧”0”の場合、’残りの2つとも低い電
圧”0”の場合、である。
On the other hand, one of the three reference memory cells for calculation has the reference word line kept at a high level in the same manner as the reference memory cell RC0 for calculation in the first embodiment. An electric charge "1/2" intermediate between "1" and "0" is obtained. Therefore, in the reference data line DjB,
Three types of voltages can appear depending on the information stored in the remaining two calculation reference memory cells. That is, '
If the remaining two are high voltage "1", 'either one
This is the case when one of them is a low voltage "0", and the case of "the remaining two are both a low voltage" 0 ".
【0041】従って、図5から分かるように、参照情報
として参照データ線の電圧VDjB=DjB(1,1,
1/2)を用いてセンスアンプを動作させると、3つの
メモリセルの蓄積されている情報の組合せが、Dj
(1,1,1)の組合せの場合のみデータ線Djが高い
電圧に増幅され、それ以外の組合せでは低い電圧とな
る。すなわち、3つのメモリセルの蓄積情報の論理積A
NDを求めることができる。また、参照情報としてVD
jB=DjB(0,0,1/2)を用いてセンスアンプ
を動作させると、Dj(0,0,0)の組合せの場合の
みデータ線Djが低い電圧に増幅され、それ以外の組合
せでは高い電圧になる。すなわち、3つのメモリセルの
蓄積情報の論理和ORを求めることができる。
Therefore, as can be seen from FIG. 5, the reference data line voltage VDjB = DjB (1, 1,
1/2) is used to operate the sense amplifier, the combination of information stored in the three memory cells becomes Dj
The data line Dj is amplified to a high voltage only in the case of the combination of (1, 1, 1), and becomes a low voltage in the other combinations. That is, the logical product A of the information stored in the three memory cells
ND can be calculated. In addition, VD as reference information
When the sense amplifier is operated using jB = DjB (0,0,1 / 2), the data line Dj is amplified to a low voltage only in the combination of Dj (0,0,0), and in other combinations. It becomes a high voltage. That is, the logical sum OR of the information stored in the three memory cells can be obtained.
【0042】このように、3つのメモリセルの蓄積情報
の論理積ANDをとる場合には、3つの演算用参照メモ
リセルの残りの2つに”1”を蓄積しておけば良く、論
理和ORをとる場合には3つの演算用参照メモリセルの
残りの2つに”0”を蓄積しておけば良い。
In this way, when the logical product AND of the storage information of the three memory cells is taken, "1" may be stored in the remaining two of the three reference memory cells for calculation, and the logical sum is obtained. In the case of OR, "0" may be stored in the remaining two of the three calculation reference memory cells.
【0043】本実施例においても、メモリチップ内で新
たに演算回路を設けることなく、メモリセルMCn(n
=0,1,……)と同種の参照メモリセルRCn(n=
0,1,……)及びそのワード線の駆動回路RXDとか
ら構成される参照信号発生手段と、ワード線に演算ビッ
ト数分だけ並列接続されたXデコーダ(本実施例の場合
並列接続した3つのXデコーダ)とを付加するのみでワ
ード線単位で並列に論理演算を行うことができる。これ
により、電力増大を最小限に抑えながら、演算速度を著
しく増大させることができる。
Also in the present embodiment, the memory cell MCn (n
= 0, 1, ...) and the same kind of reference memory cell RCn (n =
0, 1, ...) And a drive circuit RXD for the word line thereof, and an X decoder connected in parallel to the word line by the number of operation bits (in this embodiment, 3 connected in parallel). It is possible to perform a logical operation in parallel for each word line only by adding two X decoders). This makes it possible to significantly increase the calculation speed while minimizing the increase in power.
【0044】<実施例3>図6を用いて、本発明に係る
半導体記憶装置の第3の実施例を示す演算機能つきメモ
リについて説明する。図6は、演算モードを設定するた
めの動作タイミングを示す図である。実施例1では参照
ワード線につながる参照メモリセルの情報を一括して設
定していたが、本実施例ではYアドレス毎に設定を可能
にする場合の動作タイミングの一例を示す。なお、回路
構成は図1の場合と同じ構成であるので省略するが、演
算用参照ワード線の駆動回路RXDのSET信号ライン
と出力VMAラインを省略した回路構成としても良い。
ただし、後者の構成の場合には参照ワード線につながる
参照メモリセルを一括して設定することができなくな
る。また、この実施例でも、データ線対Dj、DjBの
振幅が2V、ワード線W0、W1及び演算用参照ワード
線RW1の振幅が3.5Vの場合について示している
が、これらの値に限るものではない。
<Third Embodiment> With reference to FIG. 6, a memory with an arithmetic function showing a third embodiment of the semiconductor memory device according to the present invention will be described. FIG. 6 is a diagram showing operation timing for setting the calculation mode. In the first embodiment, the information of the reference memory cells connected to the reference word line is collectively set, but in the present embodiment, an example of operation timing when setting is possible for each Y address is shown. Although the circuit configuration is the same as that of FIG. 1 and is therefore omitted, the circuit configuration may be such that the SET signal line and the output VMA line of the drive circuit RXD of the arithmetic reference word line are omitted.
However, in the latter configuration, it becomes impossible to collectively set the reference memory cells connected to the reference word line. Also in this embodiment, the case where the amplitude of the data line pair Dj, DjB is 2V and the amplitude of the word lines W0, W1 and the operation reference word line RW1 is 3.5V is shown, but the values are not limited to these values. is not.
【0045】先ず、時刻t20において演算用参照ワー
ド線RW1を高レベルにする。同時に、Yアドレス選択
信号YSjを高レベルにし、入出力線対IO、IOBか
らデータ線対Dj、DjBへ書き込みを行う。t22か
らt23にかけて演算の種類に対応する演算制御情報、
すなわち論理積ANDおよび論理和ORに対応した”
1”、”0”情報を入出力線対IO、IOBからデータ
線対Dj、DjBへ書き込む。そして、その後、t24
において演算用参照ワード線RW1を低レベルにするこ
とにより、演算制御情報が演算用参照メモリセルRC1
に蓄積される。演算に際しては、先の実施例1と同様、
t25からt28にかけてワード線W0、W1及び演算
用参照ワード線RW1を高レベルに変化させ、電荷の和
をデータ線対Dj、DjB上に出現させ、センスアンプ
SAjにより増幅する。
First, at time t20, the calculation reference word line RW1 is set to the high level. At the same time, the Y address selection signal YSj is set to high level, and writing is performed from the input / output line pair IO, IOB to the data line pair Dj, DjB. calculation control information corresponding to the type of calculation from t22 to t23,
That is, it corresponds to logical product AND and logical OR
The 1 "and" 0 "information is written from the input / output line pair IO, IOB to the data line pair Dj, DjB, and then t24.
In this case, by setting the operation reference word line RW1 to the low level, the operation control information is transferred to the operation reference memory cell RC1.
Is accumulated in In the calculation, as in the first embodiment,
From t25 to t28, the word lines W0 and W1 and the operation reference word line RW1 are changed to the high level, the sum of charges appears on the data line pair Dj and DjB, and is amplified by the sense amplifier SAj.
【0046】本実施例では、先の実施例1と異なり、演
算モード設定信号SETを用いずに、データ線対から演
算モードを設定するようにしている。このため、各デー
タ線対毎に演算モードを独立に設定できるという利点が
ある。また、この実施例に示すように、メモリセルへの
情報の書き込みに連続して演算モードの設定を行うこと
により、Yアドレス選択信号YSjの変化する回数を減
少することができ、より高速化、低電力化を図ることが
できる。なお、本実施例では、メモリセルへの情報の書
き込みの後に、演算モードの設定のための参照メモリセ
ルへの書き込みを行ったが、この書き込みの順序は入れ
替えても差し支えない。
In this embodiment, unlike the first embodiment, the calculation mode is set from the data line pair without using the calculation mode setting signal SET. Therefore, there is an advantage that the calculation mode can be independently set for each data line pair. Further, as shown in this embodiment, the number of changes of the Y address selection signal YSj can be reduced by setting the operation mode continuously after writing the information into the memory cell, and the speed is increased. It is possible to reduce power consumption. In this embodiment, after writing the information in the memory cell, the writing in the reference memory cell for setting the operation mode is performed, but the order of this writing may be changed.
【0047】<実施例4>図7乃至図9を用いて、本発
明に係る半導体記憶装置の第4の実施例を示す演算機能
つきメモリについて説明する。図7は本実施例の演算機
能つきメモリの構成図であり、図1の構成に加え、メモ
リセルアレーへの入出力線を読み出し用と書き込み用に
二重化するとともに、Yアドレス選択信号およびYアド
レス選択回路も読み出し用と書き込み用に二重化してい
る。
<Embodiment 4> A memory with an arithmetic function showing a fourth embodiment of the semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 7 is a block diagram of a memory with an arithmetic function of the present embodiment. In addition to the configuration of FIG. 1, the input / output lines to the memory cell array are duplicated for reading and writing, and a Y address selection signal and a Y address are provided. The selection circuit is also duplicated for reading and writing.
【0048】図7において、参照符号MAL0〜MAL
nおよびMAR0〜MARnはメモリセルアレー、SA
A0〜SAAnはセンスアンプアレー、RYDは読み出
し用Yデコーダ、WYDは書き込み用Yデコーダ、RY
Sjは読み出し用Yアドレス選択信号線、WYSjは書
き込み用Yアドレス選択信号線、RYACは読み出し用
Yアドレスカウンタ、WYACは書き込み用Yアドレス
カウンタ、AREGはアドレスレジスタ、CLKはクロ
ック信号、RASBは行アドレスストローブ信号、CA
SBは列アドレスストローブ信号、WEBは書き込みエ
ネーブル信号、XDL0〜XDLnおよびXDR0〜X
DRnはXデコーダ、XLL0〜XLLnおよびXLR
0〜XLRnはXアドレスラッチ、RIOおよびRIO
Bは読み出し用入出力線、WIOおよびWIOBは書き
込み用入出力線、IOS0〜IOSnはIOスイッチ、
RCDLおよびRCDLBは読み出し用コモンデータ
線、WCDLおよびWCDLBは書き込み用コモンデー
タ線、AMPは読み出し用のアンプ、DOBは出力バッ
ファ、WBUFは書き込みバッファをそれぞれ示す。な
お、図1で示した演算用参照ワード線RW0〜RWn、
演算用参照ワード線の駆動回路RXDは後述の図8に示
し、図7では省略してある。また、参照符号RIOB、
WIOB、RCDLB、WCDLBの英文字”B”は、
それぞれ対になるRIO、WIO、RCDL、WCDL
の否定の関係(相補の関係)を表わす。
In FIG. 7, reference numerals MAL0 to MAL are used.
n and MAR0 to MARn are memory cell arrays, SA
A0 to SAAn are sense amplifier arrays, RYD is a read Y decoder, WYD is a write Y decoder, and RY.
Sj is a read Y address selection signal line, WYSj is a write Y address selection signal line, RYAC is a read Y address counter, WYAC is a write Y address counter, AREG is an address register, CLK is a clock signal, and RASB is a row address. Strobe signal, CA
SB is a column address strobe signal, WEB is a write enable signal, XDL0 to XDLn and XDR0 to X.
DRn is an X decoder, XLL0 to XLLn and XLR
0 to XLRn are X address latches, RIO and RIO
B is a read input / output line, WIO and WIOB are write input / output lines, IOS0 to IOSn are IO switches,
RCDL and RCDLB are read common data lines, WCDL and WCDLB are write common data lines, AMP is a read amplifier, DOB is an output buffer, and WBUF is a write buffer. The reference word lines RW0 to RWn for calculation shown in FIG.
The calculation reference word line drive circuit RXD is shown in FIG. 8 described later and is omitted in FIG. 7. Further, reference numerals RIOB,
The English letter "B" in WIOB, RCDLB and WCDLB is
RIO, WIO, RCDL, and WCDL that make a pair respectively
Represents a negative relationship (complementary relationship).
【0049】ここで、メモリセルアレーおよびセンスア
ンプアレーのより詳細な構成を図8に示す。図8におい
て、参照符号RIOGjは読み出し用ゲート、WIOG
jは書き込み用ゲート、M20〜M23はNMOSトラ
ンジスタ、SHLは左アレー選択信号、SHRは右アレ
ー選択信号を示す。この例ではセンスアンプSAjの個
数を低減するために、左右2つのメモリセルアレーMA
L、MARで一つのセンスアンプアレーSAAを共有し
ている。通常のメモリ動作においては、左右いずれかの
選択されたメモリセルアレーMALまたはMARとセン
スアンプSAjをアレー選択信号SHLまたはSHRに
よって接続する。演算モードにおいては、アレー選択信
号SHLとSHRの両方とも高レベルにし、データ線D
LjとDRj、DLjBとDRjBがそれぞれ接続され
た状態で動作させる。例えば、ワード線W0とW2、演
算用参照ワード線RW0とRW2を高レベルにすること
により、図1の実施例と同様に、メモリセルMC0とM
C2の演算結果を得ることができる。このような構成に
することにより、センスアンプSAjを挟む2つのセル
アレーMAL、MAR間で演算を行うことができる。な
お、参照符号DLjBとDRjBの英文字”B”は、そ
れぞれ対になるDLjとDRjの否定の関係(相補の関
係)を表わす。
Here, a more detailed structure of the memory cell array and the sense amplifier array is shown in FIG. In FIG. 8, reference numeral RIOGj is a read gate and WIOG.
j is a writing gate, M20 to M23 are NMOS transistors, SHL is a left array selection signal, and SHR is a right array selection signal. In this example, in order to reduce the number of sense amplifiers SAj, two memory cell arrays MA on the left and right are provided.
One sense amplifier array SAA is shared by L and MAR. In a normal memory operation, either the left or right selected memory cell array MAL or MAR and the sense amplifier SAj are connected by an array selection signal SHL or SHR. In the operation mode, both the array selection signals SHL and SHR are set to the high level and the data line D
Lj and DRj and DLjB and DRjB are operated in a connected state. For example, by setting the word lines W0 and W2 and the operation reference word lines RW0 and RW2 to the high level, the memory cells MC0 and M0 can be changed as in the embodiment of FIG.
The calculation result of C2 can be obtained. With such a configuration, calculation can be performed between the two cell arrays MAL and MAR sandwiching the sense amplifier SAj. The letter "B" of the reference symbols DLjB and DRjB represents a negative relationship (complementary relationship) between the paired DLj and DRj.
【0050】このように構成することにより、本実施例
の演算機能つきメモリは、動画像のフレーム間の演算を
効率的に行うことができる。図9は、この構成をもとに
フレーム間演算処理を行ったときの動作の時間経過を示
すタイミング図である。図9の四角の領域の中で、上側
の記号はWが書き込み、OPが演算、Rが読み出し動作
をそれぞれ示している。また、図9の四角の領域の中
で、下側の記号は時間的に連続する2つのフレームAと
Bのいずれの処理を行うかを示しており、各フレーム
A、Bとも0〜nの(n+1)個のサブフレームに分割
している。これらは、そのままメモリの中でアクセスす
る場所に対応させており、例えばサブフレームA0〜A
nが左のアレー、サブフレームB0〜Bnが右のアレ
ー、AB0〜ABnが左のアレーと右のアレーを同時に
アクセスすることを示している。また、添字の0〜nは
図7に示した複数個のセンスアンプアレーSAA0〜S
AAnのどの場所をアクセスするかを示している。
With such a configuration, the memory with an arithmetic function of this embodiment can efficiently perform arithmetic between frames of a moving image. FIG. 9 is a timing chart showing the lapse of time when the interframe arithmetic processing is performed based on this configuration. In the square area of FIG. 9, the upper symbols indicate W, OP indicates calculation, and R indicates read operation. Further, in the square area of FIG. 9, the lower symbol indicates which of the two temporally consecutive frames A and B is to be processed, and each of the frames A and B has a value of 0 to n. It is divided into (n + 1) subframes. These correspond to the places to be accessed in the memory as they are, for example, subframes A0 to A
n indicates the left array, subframes B0 to Bn access the right array, and AB0 to ABn access the left array and the right array at the same time. The subscripts 0 to n are the plurality of sense amplifier arrays SAA0 to SAA shown in FIG.
It shows which location of AAn is to be accessed.
【0051】時刻t30以前には、先ず左アレー選択信
号SHLによりメモリセルアレーMALとセンスアンプ
SAjを接続し、フレームAの情報をサブフレームA0
〜Anに対応したメモリアレーMAL0〜MALnに書
き込む。また、時刻t30以後は、右アレー選択信号S
HRによりメモリセルアレーMARとセンスアンプSA
jを接続し、次のフレームBの情報をサブフレームB0
〜Bnに対応したメモリセルアレーMAR0〜MARn
に書き込む。これと並行して、例えば時刻t31でサブ
フレームA0とB0の情報がそろったところで、アレー
選択信号SHL、SHRを共に高レベルにし、データ線
DLjとDRj、DLjBとDRjBがそれぞれ接続さ
れた状態にして演算モードに切り換え、メモリセルアレ
ーMAL0とメモリセルアレーMAR0のワード線及び
演算用参照ワード線を高レベルにすることにより、サブ
フレームA0とB0間の演算処理が行われる。また、時
刻t32でサブフレームA0とB0間の演算処理が終了
したところで、読み出し用Yアドレス選択信号線RYS
jを高レベルにして、読み出し用入出力線RIO、RI
OBから演算結果を読み出すと同時に、次のサブフレー
ムA1とB1の演算処理を同じようにして行う。以下、
この動作を繰り返すことによって動画像のフレーム間の
演算を行うことができる。
Before time t30, the memory cell array MAL and the sense amplifier SAj are first connected by the left array selection signal SHL, and the information of the frame A is transferred to the subframe A0.
Write to memory arrays MAL0 to MALn corresponding to ~ An. Further, after the time t30, the right array selection signal S
HR memory cell array MAR and sense amplifier SA
j to connect the information of the next frame B to the subframe B0
To Bn memory cell array MAR0 to MARn
Write in. In parallel with this, for example, when the information of the subframes A0 and B0 is complete at time t31, the array selection signals SHL and SHR are both set to the high level, and the data lines DLj and DRj and DLjB and DRjB are connected to each other. Then, the arithmetic mode is switched to the arithmetic mode, and the word lines of the memory cell array MAL0 and the memory cell array MAR0 and the arithmetic reference word line are set to the high level, whereby the arithmetic processing between the subframes A0 and B0 is performed. Further, at the time t32, when the arithmetic processing between the subframes A0 and B0 is completed, the read Y address selection signal line RYS is read.
j is set to a high level, and read I / O lines RIO and RI
At the same time as the calculation result is read from the OB, the calculation processing of the next subframes A1 and B1 is performed in the same manner. Less than,
By repeating this operation, calculation between frames of a moving image can be performed.
【0052】このように、本実施例によれば、メモリセ
ルアレーが異なることにより、書き込み、読み出しおよ
び演算の各動作を並列に実行する、いわゆるパイプライ
ン処理を行うことが可能となる。したがって、本実施例
の構成は、動画像処理のように、間断無くデータの入出
力を伴うような処理に適している。
As described above, according to the present embodiment, since the memory cell arrays are different, it is possible to perform so-called pipeline processing for executing the write, read and operation operations in parallel. Therefore, the configuration of the present embodiment is suitable for a process involving continuous input / output of data, such as a moving image process.
【0053】<実施例5>図10を用いて、本発明に係
る半導体記憶装置の第5の実施例を示すコピー機能つき
メモリについて説明する。図10は、実施例4で示した
図7の構成とほぼ同じであるが、メモリ内のコピー処理
に適するようにするために、以下の3つの点で実施例4
の構成と相違する。
<Fifth Embodiment> A memory with a copy function showing a fifth embodiment of a semiconductor memory device according to the present invention will be described with reference to FIG. 10 is almost the same as the configuration of FIG. 7 shown in the fourth embodiment, but in order to make it suitable for the copy processing in the memory, the fourth embodiment has the following three points.
The configuration is different.
【0054】(1)読み出し用入出力線RIO、RIO
Bと、読み出し用コモンデータ線RCDL、RCDLB
との間に読み出し用のプリアンプAP0、AP1を設け
たこと、(2)書き込み用入出力線WIO、WIOBを
駆動するための書き込み用のポストバッファWB0,W
B1を設けたこと、および(3)書き込み用ポストバッ
ファWB0、WB1を、書き込み用コモンデータ線WC
DL、WCDLBか読み出し用コモンデータ線RCD
L、RCDLBかのいずれかに接続するための切り替え
スイッチWSL0、WSL1を設けたことである。
(1) Read input / output lines RIO, RIO
B and read common data lines RCDL, RCDLB
Read preamplifiers AP0 and AP1 are provided between the read preamplifiers AP0 and AP1 and (2) write postbuffers WB0 and W0 for driving the write input / output lines WIO and WIOB.
B1 is provided, and (3) the write post buffers WB0 and WB1 are connected to the write common data line WC.
DL, WCDLB or common data line for reading RCD
That is, the changeover switches WSL0 and WSL1 for connecting to either L or RCDLB are provided.
【0055】ここで、読み出し用のプリアンプAP0、
AP1は、読み出し用入出力線RIO,RIOBの信号
を電源電圧まで増幅し、読み出し用コモンデータ線RC
DL、RCDLBを高速に駆動する能力を有する。ま
た、切り替えスイッチWSL0、WSL1は、通常のメ
モリ動作においては、書き込み用ポストバッファWB
0、WB1を書き込み用コモンデータ線WCDL、WC
DLBを接続するように設定されていて、データ入力端
子DINから書き込みバッファWBUFを介して入力さ
れた外部からの書き込み情報を、書き込み用コモンデー
タ線WCDL、WCDLBを介して書き込み用ポストバ
ッファWIO、WIOBに伝えるように働く。一方、メ
モリのコピー動作を行う場合には、切り替えスイッチW
SL0、WSL1はコピー先の書き込み用ポストバッフ
ァWB0、WB1を、読み出し用コモンデータ線RCD
L、RCDLBに接続するように働く。
Here, the preamplifier AP0 for reading,
The AP1 amplifies the signals of the read input / output lines RIO and RIOB up to the power supply voltage and outputs the read common data line RC.
It has the ability to drive DL and RCDLB at high speed. Further, the changeover switches WSL0 and WSL1 are the write post-buffers WB in the normal memory operation.
0 and WB1 are common data lines for writing WCDL and WC
The external write information, which is set to connect the DLB and is input from the data input terminal DIN via the write buffer WBUF, is transmitted via the write common data lines WCDL and WCDLB to the write post buffers WIO and WIOB. Work to tell. On the other hand, when performing the memory copy operation, the changeover switch W
SL0 and WSL1 are write destination post-buffers WB0 and WB1 for the copy destination, and read common data line RCD.
L, works to connect to RCDLB.
【0056】以下、このように構成された本実施例のコ
ピー機能つきメモリのコピー動作を、メモリセルアレー
MAL0がコピー元、メモリセルアレーMAL1がコピ
ー先の場合を例にして説明する。なお、図10に示され
ていない構成要素は、図8の構成要素と同様であるので
図8に示した参照符号を用いる。
Hereinafter, the copy operation of the memory with a copy function of the present embodiment configured as described above will be described by taking the case where the memory cell array MAL0 is the copy source and the memory cell array MAL1 is the copy destination as an example. The components not shown in FIG. 10 are the same as the components in FIG. 8, so the reference numerals shown in FIG. 8 are used.
【0057】まず、コピー時の動作を、図11に示す動
作タイミング図を用いて説明する。この例では、コピー
動作の設定は、通常の読み出し/書き込み動作のときに
は用いない信号の組合わせにより行なっている。すなわ
ちアドレスレジスタAREGに入力される行アドレスス
トローブ信号RASB信号が低レベルに変化する時点t
0における列アドレスストローブ信号CASBおよび書
き込みエネーブル信号WEBを共に低レベルにし、なお
かつ、そのときのアドレス信号Aiの組合わせにより、
コピー元アドレス設定モードにする。このときのアドレ
スは読み出し用YアドレスカウンタRYACにセットさ
れる。また、次のt1においてコピー先アドレスを設定
し、そのアドレスを書き込み用YアドレスカウンタWY
ACにセットする。この後、t2〜t5においてクロッ
ク信号CLKに同期して読み出し用Yアドレスカウンタ
RYACと書き込み用YアドレスカウンタWYACを順
次カウントアップしながらコピー動作を行う。
First, the operation during copying will be described with reference to the operation timing chart shown in FIG. In this example, the copy operation is set by a combination of signals that are not used in the normal read / write operation. That is, the time t when the row address strobe signal RASB signal input to the address register AREG changes to low level.
The column address strobe signal CASB and the write enable signal WEB at 0 are both set to low level, and the combination of the address signal Ai at that time causes
Enter the copy source address setting mode. The address at this time is set in the read Y address counter RYAC. Also, at the next t1, the copy destination address is set and the address is set to the write Y address counter WY.
Set to AC. Thereafter, at t2 to t5, the copy operation is performed while sequentially counting up the read Y address counter RYAC and the write Y address counter WYAC in synchronization with the clock signal CLK.
【0058】この例では、コピー元アドレス、およびコ
ピー先アドレスを各々1サイクルで設定しているが、ア
ドレス信号が足りない場合には、各々2サイクルで行っ
てもよい。また、最初のサイクルでコピー動作モードを
設定した後、次の2サイクルでコピー元アドレスとコピ
ー先アドレスの設定を行ってもよい。また、通常の読み
出し/書き込み動作で用いないこれら以外の信号の組合
わせによって、コピー動作モード或いは、コピー元アド
レスやコピー先アドレスの設定をしてもよい。
In this example, the copy source address and the copy destination address are set in one cycle each, but if the address signals are insufficient, each may be set in two cycles. Further, after setting the copy operation mode in the first cycle, the copy source address and the copy destination address may be set in the next two cycles. Further, the copy operation mode or the copy source address or the copy destination address may be set by a combination of signals other than these signals which are not used in the normal read / write operation.
【0059】さらに、図10を用いてコピー動作を説明
する。先ず、センスアンプアレーSAA0の左アレー選
択信号SHLを高レベルにしてメモリセルアレーMAL
0のデータ線対DLj、DLjBをセンスアンプSAj
に接続し、読み出し用Yアドレス選択信号線RYSjを
高レベルにして読み出し用ゲートRIOGj(Xで示
す)を選択して導通状態にし、メモリセルアレーMAL
0内の○印で示したメモリセルの情報を、読み出し用入
出力線RIO、RIOG上に載せる。読み出し用入出力
線RIO、RIOGは、読み出し用のプリアンプAP0
を介して読み出し用コモンデータ線RCDL、RCDL
Bに接続されている。従って、メモリセルアレーMAL
0内の○印で示したメモリセルの情報は読み出し用コモ
ンデータ線RCDL、RCDLB上に現われる。
Further, the copy operation will be described with reference to FIG. First, the left array selection signal SHL of the sense amplifier array SAA0 is set to the high level and the memory cell array MAL is set.
0 data line pair DLj, DLjB is connected to sense amplifier SAj
And the read Y address selection signal line RYSj is set to a high level to select the read gate RIOGj (indicated by X) to make it conductive, and the memory cell array MAL is connected.
Information of the memory cell indicated by a circle in 0 is placed on the read input / output lines RIO and RIOG. The read input / output lines RIO and RIOG are connected to the read preamplifier AP0.
Read common data lines RCDL, RCDL via
Connected to B. Therefore, the memory cell array MAL
The information of the memory cell indicated by a circle in 0 appears on the read common data lines RCDL and RCDLB.
【0060】一方、コピー動作を行うために切り替えス
イッチWSL1は、書き込み用ポストバッファWB1を
読み出し用コモンデータ線RCDL、RCDLBに接続
するように働く。従って、センスアンプアレーSAA1
の書き込み用入出力線WIO1、WIOB1は、書き込
み用ポストバッファWB1および切り替えスイッチWS
L1を介して読み出し用コモンデータ線RCDL、RC
DLBに接続される。このとき、書き込み用Yアドレス
選択信号線WYSkを高レベルにして書き込み用ゲート
WIOGk(×印で示す)を導通状態にすると共に、セ
ンスアンプアレーSAA1の左アレー選択信号SHLを
高レベルにしてメモリセルアレーMAL1のデータ線対
DLj、DLjBを書き込み用入出力線WIO1、WI
OB1に接続する。これにより、読み出し用コモンデー
タ線RCDL、RCDLB上のメモリセルアレーMAL
0内の○印で示したメモリセルの情報は、メモリセルア
レーMAL1内の○印で示したメモリセル上へ書き込む
ことができる。
On the other hand, in order to perform the copy operation, the changeover switch WSL1 works so as to connect the write post buffer WB1 to the read common data lines RCDL, RCDLB. Therefore, the sense amplifier array SAA1
Of the write I / O lines WIO1 and WIOB1 are connected to the write post buffer WB1 and the changeover switch WS.
Read common data lines RCDL, RC via L1
Connected to DLB. At this time, the write Y address selection signal line WYSk is set to high level to set the write gate WIOGk (indicated by X) to the conductive state, and the left array selection signal SHL of the sense amplifier array SAA1 is set to high level. The data line pair DLj, DLjB of the array MAL1 is connected to the write input / output lines WIO1, WI.
Connect to OB1. As a result, the memory cell array MAL on the read common data lines RCDL, RCDLB
The information of the memory cell indicated by a circle in 0 can be written onto the memory cell indicated by a circle in the memory cell array MAL1.
【0061】このようにして、メモリセルアレーMAL
0から読み出されたデータは読み出し入出力線RIO0
→読み出しコモンデータ線RCDL→書き込み入出力線
WIO1の経路でメモリセルアレーMAL1に書き込ま
れる。なお、非選択のメモリセルアレーについては、読
み出し入出力線RIOおよび書き込み入出力線WIOの
電圧はデータ線のプリチャージレベル、例えば電源電圧
の中間値に設定しておけば、その非選択のメモリセルア
レーの入出力ゲートが導通しても不要な直流電流が流れ
ることはない。また、コピー元のセンスアンプアレーの
書き込み入出力線WIOは読み出し入出力線RIOと同
じ条件に設定しておけば、書き込み用Yアドレス選択信
号線WYSkによって導通する入出力ゲートを介してセ
ンスアンプの情報が反転することはない。以上により、
通常のメモリの読み出しや書き込み動作と同等の安定性
を確保したままメモリチップ内でコピー動作を行うこと
ができる。
In this way, the memory cell array MAL is
The data read from 0 is read input / output line RIO0
→ Read common data line RCDL → Write I / O line WIO1 is written to the memory cell array MAL1. For the unselected memory cell array, if the voltage of the read input / output line RIO and the write input / output line WIO is set to the precharge level of the data line, for example, the intermediate value of the power supply voltage, the unselected memory Even if the input / output gates of the cell array are turned on, unnecessary DC current does not flow. If the write I / O line WIO of the copy source sense amplifier array is set to the same condition as the read I / O line RIO, the sense amplifier array is connected via the I / O gate that is made conductive by the write Y address selection signal line WYSk. Information is never reversed. From the above,
It is possible to perform the copy operation in the memory chip while ensuring the same stability as the normal memory read / write operation.
【0062】また、コピー動作の場合には一方のメモリ
セルアレーが書き込み、他方が読み出しの動作を行う
が、本実施例の構成によれば、両方とも書き込み動作を
行わせることも可能である。その場合には、切り替えス
イッチWSL0及びWSL1を書き込み用コモンデータ
線WCDL、WCDLBに接続できるようにしておけば
良い。
Further, in the case of the copy operation, one memory cell array performs the write operation and the other performs the read operation, but according to the configuration of the present embodiment, both of them can perform the write operation. In that case, the changeover switches WSL0 and WSL1 may be connected to the write common data lines WCDL and WCDLB.
【0063】さらには、Yアドレス選択信号線、Yデコ
ーダ、入出力線などを三重化することにより、コピー動
作と並行して外部から別のメモリセルアレーへの読み出
しや書き込み動作を行うようにすることも可能である。
Furthermore, the Y address selection signal line, the Y decoder, the input / output line, etc. are tripled so that reading and writing operations from the outside to another memory cell array can be performed in parallel with the copy operation. It is also possible.
【0064】本実施例のように、メモリがコピー機能を
内蔵することにより、従来のようにプロセッサがメモリ
のコピー元からデータを読み出した後、コピー先に書き
込むといった動作を繰返し行う必要がなくなり、データ
の移動がメモリ内で閉じるため、同じ処理を従来に比べ
て高速かつ低電力で行うことができる。
By incorporating the copy function in the memory as in this embodiment, it is not necessary for the processor to repeatedly perform the operation of reading the data from the copy source of the memory and then writing the data to the copy destination, unlike the conventional case. Since the data movement is closed in the memory, the same processing can be performed at higher speed and lower power as compared with the related art.
【0065】以上、本発明の好適な実施例について説明
したが、本発明は前記実施例に限定されることなく、本
発明の精神を逸脱しない範囲内において種々の設計変更
をなし得ることは勿論である。
The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various design changes can be made without departing from the spirit of the present invention. Is.
【0066】[0066]
【発明の効果】前述した実施例から明らかなように、本
発明に係る半導体記憶装置によれば、ワード線によって
選択された複数のメモリセルから読み出された信号電荷
の和を、演算用参照メモリセルからの電荷と比較すると
同時に、複数のメモリセルの情報の論理演算をメモリ外
部に情報を読み出すことなく行うことができる。
As is apparent from the above-described embodiments, according to the semiconductor memory device of the present invention, the sum of the signal charges read from the plurality of memory cells selected by the word line is referred to for calculation. At the same time as comparing with the charges from the memory cells, the logical operation of the information of the plurality of memory cells can be performed without reading the information outside the memory.
【0067】また、メモリブロック間のデータ群のコピ
ーをメモリ外部にデータを読み出すことなくメモリ内部
で行うことができる。
Moreover, the data group between the memory blocks can be copied inside the memory without reading the data outside the memory.
【0068】従って、プロセッサの介在なしに、すなわ
ち、グラフィックス・プロセッサとメモリとの間でデー
タの読み書きをせずに、プロセッサから命令とコピーの
ための情報をメモリに送るだけで、メモリ内部において
演算処理やデータのコピー処理を高速かつ低電力に行う
ことが可能となり、システムの実効的な処理性能が向上
する。
Therefore, without the intervention of the processor, that is, without reading or writing data between the graphics processor and the memory, only the instruction and the information for copying are sent to the memory from inside the memory. The calculation processing and the data copy processing can be performed at high speed and low power, and the effective processing performance of the system is improved.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明に係る半導体記憶装置の第1の実施例を
示す演算機能つきメモリの構成図である。
FIG. 1 is a configuration diagram of a memory with an arithmetic function showing a first embodiment of a semiconductor memory device according to the present invention.
【図2】図1に示した演算機能つきメモリで使用する演
算用参照メモリセルとその参照ワード線の駆動回路の構
成図である。
FIG. 2 is a configuration diagram of a calculation reference memory cell used in the memory with a calculation function shown in FIG. 1 and a drive circuit for a reference word line thereof.
【図3】図1に示した演算機能つきメモリのデータ線電
圧の変化を示す図である。
FIG. 3 is a diagram showing changes in the data line voltage of the memory with an arithmetic function shown in FIG.
【図4】図1に示した演算機能つきメモリの動作タイミ
ングの一例を示すタイミング図である。
FIG. 4 is a timing chart showing an example of operation timing of the memory with an arithmetic function shown in FIG.
【図5】本発明に係る半導体記憶装置の第2の実施例の
演算機能つきメモリのデータ線電圧の変化を示す図であ
る。
FIG. 5 is a diagram showing changes in the data line voltage of the memory with an arithmetic function of the second embodiment of the semiconductor memory device according to the present invention.
【図6】本発明に係る半導体記憶装置の第3の実施例の
演算機能つきメモリの動作タイミングの一例を示すタイ
ミング図である。
FIG. 6 is a timing chart showing an example of the operation timing of the memory with an arithmetic function of the third embodiment of the semiconductor memory device according to the present invention.
【図7】本発明に係る半導体記憶装置の第4の実施例の
演算機能つきメモリを示す構成図である。
FIG. 7 is a configuration diagram showing a memory with an arithmetic function of a fourth embodiment of a semiconductor memory device according to the present invention.
【図8】図7に示した演算機能つきメモリのメモリセル
アレーおよびセンスアンプアレーの構成図である。
8 is a configuration diagram of a memory cell array and a sense amplifier array of the memory with an arithmetic function shown in FIG.
【図9】図7に示した演算機能つきメモリの画像フレー
ム間の演算処理の一例を示すタイミング図である。
9 is a timing chart showing an example of arithmetic processing between image frames of the memory with arithmetic function shown in FIG.
【図10】本発明に係る半導体記憶装置の第5の実施例
を示すコピー機能つきメモリの構成図である。
FIG. 10 is a configuration diagram of a memory with a copy function showing a fifth embodiment of the semiconductor memory device according to the present invention.
【図11】図10に示したコピー機能つきメモリの動作
タイミングの一例を示すタイミング図である。
11 is a timing chart showing an example of operation timing of the memory with a copy function shown in FIG.
【符号の説明】[Explanation of symbols]
MA…メモリセルアレー MC0、MC1…メモリセル RC0、RC1…演算用参照メモリセル RW0、RW1…演算用参照ワード線 Dj…データ線 SAA…センスアンプアレー SAj…センスアンプ IOG…IOゲート XD…Xデコーダ RXD…参照ワード線駆動回路 YD…Yデコーダ AMP…読み出し用アンプ DOB…出力バッファ XLL0〜XLLn、XLR0〜XLRn…Xアドレス
ラッチ WBUF…書き込みバッファ RYD…読み出し用Yデコーダ WYD…書き込み用Yデコーダ RYAC…読み出し用Yアドレスカウンタ WYAC…書き込み用Yアドレスカウンタ IOS0〜IOSn…IOスイッチ RIOG…読み出し用IOゲート WIOG…書き込み用IOゲート AP0、AP1…読み出し用プリアンプ WB0、WB1…書き込み用ポストバッファ WSL0、WSL1…切り替えスイッチ SHL…左アレー選択信号 SHR…右アレー選択信号 AREG…アドレスレジスタ CLK…クロック信号 CASB…列アドレスストローブ信号 RASB…行アドレスストローブ信号 WEB…書き込みエネーブル信号
MA ... Memory cell array MC0, MC1 ... Memory cell RC0, RC1 ... Operation reference memory cell RW0, RW1 ... Operation reference word line Dj ... Data line SAA ... Sense amplifier array SAj ... Sense amplifier IOG ... IO gate XD ... X decoder RXD ... Reference word line drive circuit YD ... Y decoder AMP ... Read amplifier DOB ... Output buffer XL0 to XLn, XLR0 to XLRn ... X address latch WBUF ... Write buffer RYD ... Read Y decoder WYD ... Write Y decoder RYAC ... Read Y address counter WYAC ... Write Y address counter IOS0 to IOSn ... IO switch RIOG ... Read IO gate WIOG ... Write IO gate AP0, AP1 ... Read preamplifier WB0, B1 ... write post buffer WSL0, WSL1 ... selector switch SHL ... left array selection signal SHR ... right array selection signal AREG ... address register CLK ... clock signal CASB ... column address strobe signal RASB ... row address strobe signal WEB ... write enable signal

Claims (10)

    【特許請求の範囲】[Claims]
  1. 【請求項1】複数のワード線と、複数のデータ線対と、
    上記複数のワード線と上記複数のデータ線対の所望の交
    点に配置された複数のメモリセルを有するメモリアレー
    と、上記複数のデータ線対の各データ線対に接続された
    複数の信号増幅手段と、上記複数のデータ線対の各デー
    タ線対に接続された複数の参照信号発生手段とを有する
    半導体記憶装置において、上記複数のワード線の所望の
    ワード線を選択するワード線選択手段をさらに具備し、
    上記ワード線選択手段が上記複数のデータ線対の1つの
    データ線対の一方のデータ線に少なくとも2つのメモリ
    セルからの情報を同時に読み出した後、上記信号増幅手
    段により上記1つのデータ線対の上記一方のデータ線に
    現れた信号を増幅することを特徴とする半導体記憶装
    置。
    1. A plurality of word lines, a plurality of data line pairs,
    A memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of signal amplifying means connected to each data line pair of the plurality of data line pairs. And a plurality of reference signal generating means connected to each data line pair of the plurality of data line pairs, further comprising a word line selecting means for selecting a desired word line of the plurality of word lines. Be equipped with
    After the word line selecting means simultaneously reads information from at least two memory cells to one data line of one data line pair of the plurality of data line pairs, the signal amplifying means reads the information of the one data line pair. A semiconductor memory device characterized by amplifying a signal appearing on the one data line.
  2. 【請求項2】前記参照信号発生手段は、複数の参照ワー
    ド線と複数の前記データ線対の各交点に配置された参照
    メモリセルからなる参照メモリセルアレーと、前記参照
    ワード線の駆動回路とから構成される請求項1に記載の
    半導体記憶装置。
    2. The reference signal generating means includes a reference memory cell array including reference memory cells arranged at respective intersections of a plurality of reference word lines and a plurality of data line pairs, and a drive circuit for the reference word lines. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises:
  3. 【請求項3】前記ワード線選択手段は、少なくとも2つ
    のワード線を同時に独立して選択する手段である請求項
    1または請求項2に記載の半導体記憶装置。
    3. The semiconductor memory device according to claim 1, wherein said word line selection means is a means for simultaneously and independently selecting at least two word lines.
  4. 【請求項4】複数のワード線と、複数のデータ線対と、
    上記複数のワード線と上記複数のデータ線対の所望の交
    点に配置された複数のメモリセルを有するメモリアレー
    と、上記複数のデータ線対の各データ線対に接続された
    複数の参照信号発生手段と、各々2つの入力を有する複
    数の信号増幅手段とを有する半導体記憶装置において、
    上記複数のデータ線対のうち少なくとも2つを並列に1
    つの信号増幅手段の2つの入力に接続する手段と、上記
    複数のデータ線対の各々に対して少なくとも1つずつの
    メモリセルからの情報を同時に読み出すようにしたワー
    ド線選択手段とをさらに具備し、上記ワード線選択手段
    が上記複数の信号増幅手段の入力の一方に少なくとも2
    つのメモリセルからの情報を同時に読み出した後、上記
    信号増幅手段により信号を増幅することを特徴とする半
    導体記憶装置。
    4. A plurality of word lines, a plurality of data line pairs,
    A memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of reference signal generation connected to each data line pair of the plurality of data line pairs And a plurality of signal amplifying means each having two inputs,
    At least two of the plurality of data line pairs are connected in parallel.
    It further comprises means for connecting to two inputs of one signal amplifying means, and word line selecting means for simultaneously reading information from at least one memory cell for each of the plurality of data line pairs. , The word line selection means has at least two inputs to one of the inputs of the plurality of signal amplification means.
    A semiconductor memory device, wherein information is read out from one memory cell at the same time and then the signal is amplified by the signal amplifying means.
  5. 【請求項5】前記複数のデータ線対のうち少なくとも2
    つを並列に1つの信号増幅手段の2つの入力に接続する
    手段は、一次元に配列された信号増幅手段の両側に配さ
    れた第1および第2のメモリセルアレーと信号増幅手段
    との間に2列に設けられ、第1のメモリセルアレーのデ
    ータ線対の1つと第2のメモリセルアレーのデータ線対
    の1つを1つの信号増幅手段に同時に接続するスイッチ
    手段である請求項4に記載の半導体記憶装置。
    5. At least two of said plurality of data line pairs
    Means for connecting two in parallel to two inputs of one signal amplifying means is provided between the signal amplifying means and the first and second memory cell arrays arranged on both sides of the one-dimensionally arranged signal amplifying means. 5. The switch means is provided in two columns and is for simultaneously connecting one of the data line pairs of the first memory cell array and one of the data line pairs of the second memory cell array to one signal amplifying means. The semiconductor memory device according to 1.
  6. 【請求項6】複数のワード線と、複数のデータ線対と、
    上記複数のワード線と上記複数のデータ線対の所望の交
    点に配置された複数のメモリセルを有するメモリアレー
    と、上記複数のデータ線対の各データ線対に接続された
    複数の信号増幅手段とから構成された複数のメモリブロ
    ックと、該メモリブロックへのデータの入出力を行なう
    入出力線と、上記複数のワード線の所望のワード線を選
    択するワード線選択手段と、上記複数の信号増幅手段の
    うちから上記入出力線に接続する信号増幅手段を選択す
    る列アドレス選択線と列アドレス選択手段とを有し、メ
    モリ外部からのデータ群のコピーのための条件を設定す
    るコピー条件設定手段と、前記データ群のコピー元およ
    びコピー先のアドレスを発生するコピーアドレス発生手
    段とをさらに具備することを特徴とする半導体記憶装
    置。
    6. A plurality of word lines, a plurality of data line pairs,
    A memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of signal amplifying means connected to each data line pair of the plurality of data line pairs. A plurality of memory blocks, an input / output line for inputting / outputting data to / from the memory block, a word line selecting means for selecting a desired word line of the plurality of word lines, and a plurality of signals. A copy condition setting for setting a condition for copying a data group from outside the memory, which has a column address selection line and a column address selection means for selecting a signal amplification means connected to the input / output line from the amplification means A semiconductor memory device further comprising: means and a copy address generating means for generating a copy source address and a copy destination address of the data group.
  7. 【請求項7】前記コピー条件設定手段は、データ群のコ
    ピー元およびコピー先の先頭アドレスを設定する先頭ア
    ドレス設定手段と、コピーするデータ群のデータ量を設
    定するデータ量設定手段とを少なくとも有する請求項6
    に記載の半導体記憶装置。
    7. The copy condition setting means includes at least a start address setting means for setting start addresses of a copy source and a copy destination of a data group, and a data amount setting means for setting a data amount of a data group to be copied. Claim 6
    The semiconductor memory device according to 1.
  8. 【請求項8】前記メモリブロックへのデータの入出力を
    行う入出力線と、列アドレス選択線と、列アドレス選択
    手段とを各々二重化して成る請求項6に記載の半導体記
    憶装置。
    8. The semiconductor memory device according to claim 6, wherein an input / output line for inputting / outputting data to / from said memory block, a column address selection line, and a column address selection means are duplicated.
  9. 【請求項9】複数のワード線と、複数のデータ線対と、
    上記複数のワード線と上記複数のデータ線対の所望の交
    点に配置された複数のメモリセルを有するメモリアレー
    と、上記複数のデータ線対の各データ線対に接続された
    複数の信号増幅手段とから構成された複数のメモリブロ
    ックと、該メモリブロックへのデータの入出力を同時並
    列に行なう二重化した入出力線と、上記複数のワード線
    の所望のワード線を選択するワード線選択手段と、上記
    複数の信号増幅手段のうちから上記二重化した入出力線
    に接続する信号増幅手段を選択する二重化した列アドレ
    ス選択線と二重化した列アドレス選択手段、とを具備す
    ることを特徴とする半導体記憶装置。
    9. A plurality of word lines, a plurality of data line pairs,
    A memory array having a plurality of memory cells arranged at desired intersections of the plurality of word lines and the plurality of data line pairs, and a plurality of signal amplifying means connected to each data line pair of the plurality of data line pairs. A plurality of memory blocks each including a plurality of memory blocks, a dual I / O line for simultaneously inputting and outputting data to and from the memory blocks, and a word line selecting means for selecting a desired word line of the plurality of word lines. , A semiconductor memory comprising: a duplicated column address selection line and a duplicated column address selection means for selecting a signal amplification means connected to the duplicated input / output line from the plurality of signal amplification means. apparatus.
  10. 【請求項10】前記メモリアレーはダイナミックメモリ
    で構成される請求項1乃至請求項9のいずれか一に記載
    の半導体記憶装置。
    10. The semiconductor memory device according to claim 1, wherein the memory array is a dynamic memory.
JP6160904A 1994-07-13 1994-07-13 Semiconductor storage device Pending JPH0831168A (en)

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JP6160904A JPH0831168A (en) 1994-07-13 1994-07-13 Semiconductor storage device

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JPH0831168A true JPH0831168A (en) 1996-02-02

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