JP4004250B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device such as an SRAM (Static Random Access Memory), and more particularly to a semiconductor memory device that reads and writes data to and from an arbitrary address at high speed and with low power consumption.
[0002]
[Prior art]
An SRAM (Static Random Access Memory) is more expensive than a DRAM (Dynamic Random Access Memory) having a large number of elements constituting a memory cell and a small number of elements constituting a memory cell. However, SRAMs are widely used in computers and the like because they do not require the refresh operation required by DRAMs and can be driven at high speed and with low power consumption.
[0003]
FIG. 4 is a circuit diagram showing a configuration of a conventional typical SRAM. The SRAM shown in FIG. 4 includes a memory cell array 900 in which a plurality of cells are arranged in a row direction and a column direction, and an address input unit 200, a data output unit 700, a data input unit 800, and the like that transmit and receive signals to and from an external circuit. Circuit.
[0004]
The memory cell array 900 includes a plurality of word lines WL (P) (P = 0, 1, 2, 3...) And a pair of bit lines bit (P) and bit (P) that are orthogonal to the word lines WL (P). P) _bar and a memory cell arranged at the intersection of the word line WL (P) and the bit line pair bit (P) and bit (P) _bar.
[0005]
Here, the case of P = 1 (line number 1) will be described. In this case, the bit line pair bit (1) and bit (1) _bar are the bit line pair 105a and 105b.
[0006]
Memory cell 100 arranged at the intersection of word line WL (1) and bit line pair pair 105a and 105b is constituted by a data holding circuit composed of two inverter circuits and two transfer gates. In the data holding circuit, an input terminal and an output terminal of one inverter circuit are connected to an output terminal and an input terminal of the other inverter circuit, respectively. Each transfer gate has a gate terminal connected to the word line WL (1), a drain terminal connected to the bit line pair 105a and 105b, and a source terminal connected to the input terminal and output terminal of the inverter circuit. It is connected to the.
[0007]
The address input unit 200, the data output unit 700, and the data input unit 800 are circuits that transmit and receive signals to and from an external circuit. The address input unit 200 inputs an address signal, and the data output unit 700 outputs read data. The data input unit 800 inputs write data.
[0008]
Other peripheral circuits receive a row decoder 210 and a column decoder 220 that decode an input address signal, an output signal from the column decoder 220, a column selection circuit 221 that selects a specific column, and a bit line pair 105a. And 105b (charging operation for setting the same potential) and a precharge circuit 300 for charging the bit line pairs 105a and 105b to a specific potential, a sense amplifier 500 for amplifying a small potential difference between the bit line pairs 105a and 105b during data reading, and data Write amplifier 600 for transmitting data input at the time of writing to bit line pairs 105a and 105b, control unit 410 that performs timing control on input signals and output signals of these peripheral circuits, clock signals from external circuits, and various enables Control signal such as signal It is constituted by the control input unit 400 to be input.
[0009]
Next, the operation of the SRAM shown in FIG. 4 will be described. FIGS. 5A and 5B are timing charts of signals representing operations at the time of data reading and data writing of the SRAM shown in FIG.
[0010]
CLK is a clock signal input from an external circuit (not shown) connected to the SRAM. The input of the address signal Ain to the SRAM, the write data input Din at the time of writing, and the output data Dout from the SRAM to the external circuit are all performed in synchronization with CLK.
[0011]
First, the operation at the time of data reading shown in FIG. At the rising edge of CLK (time Tr0), the bit line pairs 105a and 105b are equalized by the precharge circuit 300 so as to have the same potential, and at the same time, a specific potential (generally a power supply voltage or 1/2 of the power supply voltage). ) Is charged. At this time, the bit line pair in the sense amplifier 500 and the write amplifier 600 is similarly precharged. Tpc shown in FIG. 5A is a time required for precharging the bit line pairs in the bit line pairs 105a and 105b, the sense amplifier 500 and the write amplifier 600, and is referred to as a precharge time.
[0012]
After precharge is completed for the bit line pairs in the bit line pairs 105a and 105b, the sense amplifier 500, and the write amplifier 600, the address signal is decoded from the falling edge (time Tr1) of CLK. First, one word line WL (1) is selected by the row decoder 210, and the transfer gate in the memory cell 100 connected to the word line WL (1) is turned on (ON state). Thereby, bit line pair 105a and 105b are connected to the data holding circuit in memory cell 100, respectively, and a slight potential difference starts to occur between bit line pair 105a and 105b from the same potential state after precharging. Following the decoding in the row direction, the column decoder 220 selects one set of bit line pairs 105 a and 105 b via the column selection circuit 221 and connects to the sense amplifier 500. Sense amplifier 500 amplifies a minute potential difference generated between bit line pairs 105 a and 105 b and transmits output data to data output unit 700.
[0013]
Tac shown in FIG. 5A is a time from when the decoding of the address signal is started until the output data appears at the output of the SRAM, and is called an access time. The read speed of the SRAM is determined by the longer of the precharge time Tpc and the access time Tac.
[0014]
Thus, assuming that the period of the clock signal CLK from the external circuit is Tclk, the relationship of Tclk> 2Tpc is established when Tpc ≧ Tac, and Tclk> 2Tac is established when Tpc ≦ Tac. As a result, Tclk can only be shortened up to twice the longer period of Tpc and Tac. Such a shortest cycle of CLK at the time of data reading is called an SRAM read cycle time.
[0015]
Next, the operation at the time of data writing shown in FIG. In the data write operation, the precharge and address signal decode operations for the bit line pairs 105a and 105b, the sense amplifier 500 and the write amplifier 600 are the same as the data read operation. In the case of writing, simultaneously with the falling edge of CLK (time Tw1), the input data input from the data input unit 800 passes through the write amplifier 600 and is input to the bit line pairs 105a and 105b. Thereby, the data of the memory cell 100 connected to the selected word line WL (1) and the bit line pair 105a and 105b is rewritten, and the input data input from the write amplifier 600 to the bit line pair 105a and 105b. Is transmitted to the data output unit 700 through the sense amplifier 500. The precharge time Tpc at the time of data writing has the same value as the precharge time Tpc at the time of data reading. On the other hand, the access time Tac ′ at the time of data writing is that the decoding of the address signal is started more than the time from when the decoding of the address signal is started until the data appears in the output of the SRAM (access time at the time of reading data). Since the time until the data in the data holding circuit of the memory cell 100 is rewritten is longer, the latter is used as the access time. The data write speed of the SRAM is also determined by the longer of the precharge time Tpc and the access time Tac ′.
[0016]
Thus, assuming that the cycle of the clock signal CLK from the external circuit is Tclk, the relationship of Tclk> 2Tpc is established when Tpc ≧ Tac ′, and Tclk> 2Tac ′ is established when Tpc ≦ Tac ′. As a result, Tclk can only be shortened up to twice the longer period of Tpc and Tac ′. Such a shortest cycle of CLK at the time of data writing is called an SRAM write cycle time.
[0017]
In the SRAM that operates in synchronization with the clock signal of the external circuit shown in FIG. 4, the longer read cycle time and write cycle time is the SRAM cycle time (the shortest cycle in which the SRAM operates normally).
[0018]
As described above, in the conventional SRAM shown in FIG. 4, the data read operation or data write operation cannot be completed in a time shorter than the cycle time described above. JP-A-6-44783 discloses a configuration in which such a restriction is eliminated and the SRAM is operated at a higher speed.
[0019]
The configuration of the SRAM disclosed in this publication pays attention to the fact that the precharge time is not included in the access time for accessing each memory cell and performing the data read operation or data write operation. The operation of the SRAM according to the configuration is such that two independent word line and bit line pairs are provided, and data writing operation or data reading operation is alternately performed for each word line and bit line pair system. As a result, the bit line pair of each system of the word line and the bit line pair is completely separated, and the data from the bit line pair of the other system is pre-charged while the bit line pair of one system is precharged. A write operation or a data read operation is performed.
[0020]
FIG. 6 is a circuit diagram showing a configuration of the SRAM disclosed in the above publication.
[0021]
The SRAM shown in FIG. 6 includes a plurality of memory cells 3 each having a pair of inverter circuits. In each memory cell 3, the input terminal and output terminal of one inverter circuit are connected to the output terminal and input terminal of the other inverter circuit, respectively. Each memory cell 3 is connected to bit line pair 2A1 and 2A2 by transfer gates 31A and 32A, and connected to bit line pair 2B1 and 2B2 by transfer gates 31B and 32B. The gate terminals of transfer gates 31A and 32A are connected to word line 1A, and the gate terminals of transfer gates 31B and 32B are connected to word line 1B. Word lines 1A and 1B are connected to A row decoder 4A and B row decoder 4B, respectively. Bit line pair 2A1 and 2A2 are connected to A column decoder 51A through switch column 52A. Bit line pair 2B1 and 2B2 are connected to B column decoder 51B via switch column 52B.
[0022]
Thus, by connecting each memory cell 3, each memory cell 3 can be independently accessed from each system of the row decoders 4A and 4B and the column decoders 51A and 51B.
[0023]
The SRAM peripheral circuit is provided with a write control unit 6, an output unit 7, a precharge circuit 8, a cycle control unit 10, and the like. The cycle controller 10 applies an access signal to each memory cell 3 corresponding to the address signal in order to each system of the word lines 1A and 1B and the bit line pairs 2A1, 2A2, and 2B1, 2B2. The row decoders 4A and 4B and the column decoders 5A and 5B of each system are switched and controlled.
[0024]
FIG. 7 is a timing chart of signals showing the operation of the SRAM provided with two systems of word line and bit line pairs shown in FIG. As described above, in the SRAM, it is necessary to perform precharge time separately from the data write operation and the data read operation. However, if the precharge is performed, the data write operation or the data read operation itself is related to the precharge time. do not do. Therefore, a data write operation or a data read operation is performed alternately for each system of word lines and bit line pairs provided in two systems. At this time, since the bit line pair of each system is in a completely separated state, the other bit line pair performs a data write operation or a data read operation while one bit line pair is precharged. Can be done. As a result, the precharge time can be substantially eliminated, and high-speed access can be made accordingly.
[0025]
[Problems to be solved by the invention]
However, in the SRAM configuration disclosed in Japanese Patent Application Laid-Open No. 6-44783, since two bit line pairs are provided, the number of bit line pairs to be driven is doubled. The power consumed per unit time for driving the line pair is doubled, the power consumption of the entire SRAM is increased, and there is a problem that it cannot be used for applications requiring low power consumption.
[0026]
The present invention solves such problems, and an object of the present invention is to provide a semiconductor memory device that operates at a high speed and is driven with low power consumption.
[0027]
[Means for Solving the Problems]
The semiconductor memory device of the present invention First An input / output connection portion, a second input / output connection portion, and a first input / output connection portion and a second input / output connection portion; Corresponding to each A memory cell array in which a plurality of memory cells each having a pair of control terminals are arranged in a matrix, and a peripheral circuit for driving the memory cell array, each memory cell along the row direction is a word line Connected to And , Row direction The same number of memory cells placed in Bit line pair But Each of the bit line pairs is constituted by a bit line and a bit bar line, Each memory cell along the column direction 2 pairs adjacent along the row direction Bit line In pairs Connected The Semiconductor memory device, 2Nth and 2N + 1th memory cells adjacent in the row direction In the 2Nth memory cell in FIG. 2Nth and 2N + 1th adjacent along the row direction Each bit line of each bit line pair Connected to The second input / output connection portion is 2Nth and 2N + 1th bit line pairs Each bit bar line Connected to The 2N + 1th memory cell has the first input / output connection portion 2N + 1 and 2Nth Each bit line of each bit line pair Connected to The second input / output connection is 2N + 1 and 2Nth Bit bar line of each bit line pair And the peripheral circuit for driving the memory cell array is connected to the 2Nth and 2N + 1th memory cells, respectively. Bit line pairs And 2N + 1th of Bit line pair Each of Are alternately precharged in synchronization with a clock signal input from an external circuit. First precharge means and second Precharge means and each bit line pair that has completed precharge among the first input / output connection portion and the second input / output connection portion of each memory cell selected by an address signal input from an external circuit The first input / output connection section or the second input / output connection section connected is turned on, and the other second input / output connection section or the first input / output connection section is turned off. Control means for controlling a control signal input to the control terminal.
[0028]
Of the 2Nth memory cell Said A first input / output connection and Said A pair of each corresponding to the second input / output connection Said Control terminals are connected to the first and second word lines, respectively, and the 2N + 1th memory cell Said A first input / output connection and Said A pair of each corresponding to the second input / output connection Said Control terminals are connected to the third and fourth word lines, respectively.
[0030]
The peripheral circuit includes a plurality of sense amplifiers, a plurality of write amplifiers, a plurality of column selection circuits, a multiplexer and a demultiplexer, and corresponds to the sense amplifier and the write amplifier. Said A column to which the precharge control means for controlling the sense amplifier and the write amplifier to be precharged simultaneously with the precharge of the bit line pair and the memory cell selected by an address signal input from an external circuit is connected. Column selection circuit selection means for controlling to select a selection circuit; Said Multiplexer and Said The demultiplexer has signal line selection means for controlling to select a signal line for performing a read operation and a write operation, respectively.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0032]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. As in the SRAM shown in FIG. 4, the SRAM of the semiconductor memory device shown in FIG. 1 has a memory cell array 900 in which a plurality of memory cells are arranged in a matrix, an address input unit 200 that transmits and receives signals to and from an external circuit, Peripheral circuits such as a data output unit 700 and a data input unit 800 are included.
[0033]
In the memory cell array 900, 2J columns × I rows (J and I are positive integers) are arranged. Each memory cell is connected to two word lines and a pair of bit lines.
[0034]
In FIG. 1, in the 2J memory cells arranged in the row direction, the 2Nth (N is a positive integer) adjacent memory cell 100 and the 2N + 1th memory cell 110 are shown, respectively. The cell 100 is connected to the 2Nth bit line pair 105a and 105b, and the 2N + 1th memory cell 110 is connected to the 2N + 1th bit line pair 115a and 115b. In addition, word lines WL (0) 0A and WL (0) 0B are connected to the memory cell 100, and word lines WL (0) 1A and WL (0) 1B are connected to the memory cell 110. Thus, in the entire memory cell array 900, 4 × I word lines (WL (0) 0A to WL (I) 0A, WL (0) 0B to WL (I) 0B, WL (0) 1A to WL (I ) 1A, WL (0) 1B to WL (I) 1B), and these word lines are all connected to the row decoder 210.
[0035]
The memory cell 100 includes a data holding circuit including two inverter circuits 101 and 102, transfer gates 103a and 103b connecting the data holding circuit and the 2Nth bit line pair 105a and 105b, a data holding circuit and a 2N + 1th Transfer gates 104a and 104b connecting the bit line pairs 115a and 115b. In the data holding circuit, the input terminal and the output terminal of the inverter circuit 101 are connected to the output terminal and the input terminal of the inverter circuit 102, respectively.
[0036]
Transfer gates 103a and 103b have their gate terminals connected to word line WL (0) 0A, their drain terminals connected to 2Nth bit line pair 105a and 105b, and their source terminals connected to an inverter circuit. 101 and 102 are connected to the input terminal and the output terminal, respectively. The transfer gates 104a and 104b have their gate terminals connected to the word line WL (0) 0B, and their drain terminals connected to the memory cell 110 adjacent to the memory cell 100, the 2N + 1th bit line pair 115a. And 115b, and the source terminals thereof are connected to the input terminals and the output terminals of the inverter circuits 101 and 102, respectively.
[0037]
The memory cell 110 includes a data holding circuit including two inverter circuits 111 and 112, transfer gates 113a and 113b connecting the data holding circuit and the 2N + 1th bit line pair 115a and 115b, a data holding circuit and a 2Nth The transfer gates 114a and 114b connect the bit line pairs 105a and 105b. In the data holding circuit, the input terminal and the output terminal of the inverter circuit 111 are connected to the output terminal and the input terminal of the inverter circuit 112, respectively.
[0038]
Transfer gates 113a and 113b have their gate terminals connected to word line WL (0) 1B, their drain terminals connected to 2N + 1th bit line pair 115a and 115b, and their source terminals connected to inverter circuit 111. And 112 are connected to input terminals and output terminals, respectively. The transfer gates 114a and 114b have their gate terminals connected to the word line WL (0) 1A and their drain terminals connected to the memory cell 100 adjacent to the memory cell 110 to the 2Nth bit line pair 105a. Are connected to the input terminals and the output terminals of the inverter circuits 111 and 112, respectively.
[0039]
The 2N-th bit line pair 105a and 105b are connected to the precharge circuit A301 and the column selection circuit A222, and are connected to the sense amplifier A501 and the write amplifier A601 via the column selection circuit A222. Similarly, the 2N + 1-th bit line pair 115a and 115b is connected to the precharge circuit B310 and the column selection circuit B223, and is connected to the sense amplifier B510 and the write amplifier B610 via the column selection circuit B223.
[0040]
As a circuit for transmitting / receiving a signal to / from an external circuit, a data output unit 700 for outputting read data, a data input unit 800 for inputting write data, an address input unit 200 for inputting address signals, and an external circuit. A control signal input unit 400 for inputting control signals such as a clock signal and various enable signals is provided.
[0041]
Other peripheral circuits include a row decoder 210 that selects a word line based on an address signal input to the address input unit 200, and a column decoder 220 that generates a switching signal for the column selection circuit A222 and the column selection circuit B223 from the address signal. The multiplexer 710 that switches the input signal from the sense amplifier A501 and the input signal from the sense amplifier B510 and outputs it to the data output unit 700, and the write data from the data input unit 800 are input, and the write data is input to the write amplifier A601. Alternatively, it includes a demultiplexer 810 that switches to and outputs the write amplifier B 610 and a control unit 410 that controls the operation timing of these peripheral circuits.
[0042]
FIG. 2 is a timing chart showing operations at the time of data reading and data writing of the SRAM which is the semiconductor memory device shown in FIG. In FIG. 2, the A system is a peripheral circuit related to the operation of the 2Nth bit line pair 105a, 105b in the row direction, and the B system is a peripheral circuit related to the operation of the 2N + 1th bit line pair 115a, 115b. . The SRAM of the present invention operates in synchronization with a clock signal CLK input from an external circuit, and the A system peripheral circuit and the B system peripheral circuit alternately perform a precharge operation, a read operation, and a write operation.
[0043]
FIG. 3 is a timing chart showing a specific operation of the SRAM when the operation shown in the upper part of FIG. 3 is performed on the SRAM which is the semiconductor memory device shown in FIG.
[0044]
As an example of the SRAM of the present invention, it has a memory cell array 900 of 8 columns × 128 rows, the address signal Ain is 10 bits wide, Ain [9: 3] of the address signal Ain is the row address, and Ain [2: 0] is input to the row decoder 210 and the column decoder 220 as column addresses, respectively, and is decoded. As an example of the operation of such an SRAM, consider the operation of the next five cycles with reference to the operation waveform shown in FIG.
[0045]
Cycle 1: Write data D1 to address “16” (Ain [9: 0] = “0000010000”) (A system)
Cycle 2: Reading from address “16” (Ain [9: 0] = “0000010000”) (B system)
Cycle 3: Read from address “16” (Ain [9: 0] = “0000010000”) (A system)
Cycle 4: Read from address “5” (Ain [9: 0] = “0000000101”) (read data D2) (B system)
Cycle 5: Write data D3 to address “9” (Ain [9: 0] = '0000001001') (A system)
Hereinafter, the operation of the SRAM of the present embodiment will be described.
[0046]
First, in the precharge operation, at time t0, a pulse signal (not shown) that prompts the precharge circuit A301 to start precharge is output to the precharge circuit A301 via the signal line C10 (see FIG. 1). The system precharge is started (hereinafter, the same applies at times t2, t4, and t6). At this time, precharge is also performed for the bit line pairs in the sense amplifier A501 and the write amplifier A601 belonging to the A system. At time t1, a pulse signal (not shown) that prompts the precharge circuit B310 to start precharge is output from the control unit 410 to the precharge circuit B310 via the signal line C9 (see FIG. 1). This is started (hereinafter, the same applies at times t3 and t5). At this time, as in the case of the A system, precharge is also performed on the bit line pairs in the sense amplifier B 510 and the write amplifier B 610 belonging to the B system. The time Tpc required for precharging is shorter than the cycle of the clock signal CLK from the external circuit, and the cycle of CLK is set so that the precharge operation is completed by the next cycle of CLK.
[0047]
Next, attention is paid to the decoding of the address signal Ain [n: 0] (here n = 9) having an n + 1 bit width. Assuming that the address signal Ain [k: 0] (here, k = 2) is data in the column direction, decoding is performed in the following procedure.
[0048]
(1) At time t1, an enable signal is output from the control unit 410 to the address input unit 200 via the signal line C11 (see FIG. 1), an address signal is output from the address input unit 200, and the row decoder 210 and the column decoder 220 are output. Is input.
[0049]
(2) First, in the row direction, the row number of the selected memory cell is determined by decoding Ain [n: k + 1]. Here, the value of the address signal is “16”, the memory cell in the second row is selected from Ain [9: 3] = “0000010”, and the four word lines WL (2) corresponding to the row number are selected. 0A, WL (2) 0B, WL (2) 1A, WL (2) 1B are candidates for outputting enable signals for the four transfer gates in each memory cell.
[0050]
(3) When Ain [0] is 0 (the memory cell to be selected is a 2N column memory cell), the four cells that are candidates for outputting the enable signal in the above operations (1) and (2) Word lines WL (a) 0A, WL (a) 0B (a is a number corresponding to the row number of the selected memory cell) for performing ON / OFF operations of transfer gates of 2N columns of memory cells. ) Becomes a candidate for outputting an enable signal to the transfer gate, and the stage where Ain [0] is 1 (the selected memory cells are 2N + 1 rows of memory cells), enabled by the above operations (1) and (2) Of the four word lines that are candidates for signal output, word lines WL (a) 1A and WL (a) 1B that perform ON / OFF operations of transfer gates of 2N + 1 columns of memory cells A candidate for outputting an enable signal to the transfer gate. Here, in cycle 1 (t0 to t1), since Ain [9: 3] = '0000010' and Ain [0] = '0', WL (2) 0A and WL (2) 0B are candidates. Remain as.
[0051]
{Circle around (4)} At the time when decoding of the address signal is started, if the system that has finished precharging is the A system, of the two remaining word lines as candidates for outputting the enable signal, A The word line that performs the ON / OFF operation of the transfer gate connected to the system bit line pair is finally determined as the word line that outputs the enable signal. Further, when the system that has completed precharging is the B system, of the two word lines remaining as candidates for outputting the enable signal, the transfer circuit connected to the B system bit line pair. The word line that performs the ON / OFF operation of the gate is finally determined as the word line that outputs the enable signal. As a result, at time t1, the A system has finished precharging, so that the remaining two word lines WL (2) 0A and WL (2) 0B remain as candidates for outputting the enable signal to the transfer gate. Of these, WL (2) 0A belonging to the A system is selected, and an enable signal is output to WL (2) 0A.
[0052]
(5) Next, in the column direction, the 2N-th bit line pair and the 2N + 1-th bit line are decoded by decoding the address signal Ain [k: 1] (Ain [0] is decoded as “0” or “1”). One pair is selected from each pair. Here, since k = 2 and Ain [2: 1] = '00', N = 0 is set, and the bit line pair in the 0th column and the bit line pair in the 1st column are selected.
[0053]
(6) Since the system that has completed precharging at time t1 is the A system, an enable signal is output from the control unit 410 to the column selection circuit A222, and the two pairs selected in (5) above are selected. The bit line pair in the 0th column belonging to the A system among the bit line pairs is selected.
[0054]
The read operation and write operation are as follows. At time t1, since the enable signal input from the external circuit is WE = '0', the write operation is selected, and the A-system write amplifier A601 that has finished precharging from the control unit 410 at time t1. In addition, the enable signal is output to the sense amplifier A501 via the signal lines C3 and C4, respectively, and the selection signal for switching the demultiplexer 810 and the multiplexer 710 to the A system is output via the signal lines C6 and C7, respectively. Here, the access time Tac ′ required for writing is the time from the start of decoding of the address signal at time t1 to the completion of rewriting of the data holding circuit in the memory cell. Tac ′ is shorter than the cycle of the clock signal CLK from the external circuit, and the cycle of CLK is set so that the write operation is completed by the next cycle of CLK.
[0055]
At subsequent time t2, the decoding operation by the address signal is the same as described above. However, since the system that has finished precharging at time t2 is the B system, WL (2) 0B is selected as the word line in the row direction, and the column selection circuit from the control unit 410 in the column direction. An enable signal is output to B223, and the bit line pair in the first column is selected. At time t2, since the enable signal input from the external circuit is WE = '1', the read operation is selected, and the control unit 410 receives the sense amplifier B510 of B system that has finished precharging at time t2. The enable signal is output from the control unit 410 via the signal lines C6 and C7 so that the demultiplexer 810 and the multiplexer 710 are switched to the B system simultaneously. Here, the access time Tac required for reading is the time from when the decoding of the address signal is started at time t2 until the output signal is output to Dout of the data output unit 700. Tac is shorter than the cycle of the clock signal CLK from the external circuit, and the cycle of CLK is set so that the read operation is completed by the next cycle of CLK. The same operation as described above is repeated at time (t3, t4, etc.) after time t2.
[0056]
In the SRAM, if the memory capacity (number of memory cells) and the driving capability of each transistor of the data holding circuit in the memory cell are similar, the precharge time Tpc, the data read time Tac, and the data write time Tac are different even in different SRAMs. 'Is almost the same value.
[0057]
As a result, in the SRAM of the present invention, as shown in FIG. 3, the precharge operation and the data read operation or the data write operation are performed in the same cycle except for the first cycle. Therefore, the access time for one data read operation or write operation may be one cycle. As a result, in the SRAM of the present invention and the conventional SRAM disclosed in the above publication, the precharge time Tpc, the data read time Tac, and the data write time Tac ′ are substantially the same value. With respect to the conventional SRAM disclosed in the aforementioned publication, a data read operation or a data write operation can be performed at substantially the same high speed operation.
[0058]
Further, the conventional SRAM disclosed in the above-mentioned publication has two independent bit line pairs, and the number of bit line pairs to be driven is doubled, so that the load becomes large, and the unit time Power consumption per hit increases. On the other hand, the SRAM of the present invention has two independent bit line pairs. However, when the SRAM is driven, one of the two bit line pairs has one bit line pair. Since the connection is made in common with the bit line pairs of unselected memory cells adjacent in the row direction, only the other one bit line pair is actually driven. As a result, the SRAM of the present invention has a driving load that is ½ that of a conventional SRAM, and the power consumption per unit time can be reduced to ½ that of a conventional SRAM.
[0059]
Therefore, the SRAM of the present invention can operate at high speed and with low power consumption.
[0060]
【The invention's effect】
In the semiconductor memory device of the present invention, the first input / output connection is connected to the bit line pair to which the memory cell is connected, and the bit line pair connected to the memory cell adjacent to the memory cell in the row direction. The second input / output connection is connected to each other, and in this way, the adjacent memory cells in the row direction are connected so that the bit line pair is shared. It can be driven by power consumption.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the SRAM that is the semiconductor memory device shown in FIG. 1;
FIG. 3 is a timing chart showing a specific operation of the SRAM which is the semiconductor memory device shown in FIG. 1;
FIG. 4 is a circuit diagram showing a configuration of a conventional SRAM.
FIG. 5A is a timing chart showing an operation at the time of data reading of a conventional SRAM;
(B) It is a timing chart showing the operation | movement at the time of data writing.
FIG. 6 is a circuit diagram showing a configuration of an SRAM disclosed in the publication.
7 is a timing chart showing the operation of the SRAM shown in FIG.
[Explanation of symbols]
100 memory cells
101 Inverter circuit
102 Inverter circuit
103a transfer gate
103b transfer gate
104a transfer gate
104b transfer gate
105a bit line
105b bit bar line
110 memory cells
111 Inverter circuit
112 Inverter circuit
113a transfer gate
113b transfer gate
114a transfer gate
114b transfer gate
115a bit line
115b bit bar line
200 Address input part
210 line decoder
220 column decoder
221 column selection circuit
222 Column selection circuit A
223 Column selection circuit B
300 Precharge circuit
301 Precharge circuit A
310 Precharge circuit B
400 Control signal input section
410 Control unit
500 sense amplifier
501 sense amplifier A
510 sense amplifier B
600 writing amplifier
601 Write amplifier A
610 Write amplifier B
700 Data output part
710 multiplexer
800 Data input part
810 Demultiplexer
900 Memory cell array

Claims (3)

A plurality of memory cells each having a first input / output connection portion, a second input / output connection portion, and a pair of control terminals respectively corresponding to the first input / output connection portion and the second input / output connection portion are arranged in a matrix. a memory cell array which is has a peripheral circuit for driving the memory cell array, each memory cell along a row direction are connected to the word lines, memory cells and the same number of arranged in the row direction A pair of bit lines is provided, each of the bit line pairs is constituted by a bit line and a bit bar line, and each memory cell along the column direction is adjacent to each other in two rows along the row direction . a connected semiconductor memory device,
The 2N-th memory cell in each of the 2N-th and 2N + 1-th memory cells adjacent in the row direction is the 2N-th and 2N + 1-th bit line pair adjacent to each other in the row direction . are connected to respective bit lines, said second input-output connection units may be connected to each of the bit bar line of 2N th and 2N + 1 th each bit line pair, 2N + 1 th memory cells, the first inlet The output connection is connected to the respective bit lines of the 2N + 1th and 2Nth bit line pairs, and the second input / output connection is connected to the bit bar lines of the 2N + 1th and 2Nth bitline pairs , respectively. And
The peripheral circuit that drives the memory cell array includes:
Pre each of the 2N th and 2N + 1 th the 2N-th bit line pair connected to each memory cell in and 2N + 1-th bit line pairs, respectively in synchronization with the clock signal inputted from an external circuit alternately First precharging means and second precharging means for charging;
The first input / output connection portion and the second input / output connection portion of each memory cell selected by an address signal input from an external circuit are connected to each bit line pair that has been precharged. Input to the control terminal so that the first input / output connection section or the second input / output connection section is turned on and the other second input / output connection section or the first input / output connection section is turned off. Control means for controlling the control signal;
A semiconductor memory device comprising:   A pair of the control terminals corresponding to the first input / output connection portion and the second input / output connection portion of the 2Nth memory cell are respectively connected to the first and second word lines, and the 2N + 1th memory 2. The semiconductor memory device according to claim 1, wherein the pair of control terminals corresponding to the first input / output connection portion and the second input / output connection portion of the cell are connected to the third and fourth word lines, respectively. . The peripheral circuit includes a plurality of sense amplifiers, a plurality of write amplifiers, a plurality of column selection circuits, a multiplexer, and a demultiplexer.
Precharge control means for controlling the sense amplifier and the write amplifier to precharge simultaneously with the precharge of the bit line pair corresponding to the sense amplifier and the write amplifier;
Column selection circuit selection means for controlling to select a column selection circuit to which the memory cell selected by an address signal input from an external circuit is connected;
Signal line selection means for controlling the multiplexer and the demultiplexer to select signal lines for performing a read operation and a write operation, respectively;
The semiconductor memory device according to claim 1, comprising:

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