JPH07122996B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which memory cells are integrated on a large scale.

[0002]

2. Description of the Related Art There is a so-called RAM as a type of semiconductor integrated circuit (hereinafter referred to as a semiconductor memory) in which memory cells are integrated on a large scale.

A RAM (Random Access Memory) is a device capable of temporarily storing information and reading it at a necessary time, and is also called a read / write memory. The RAM includes a memory cell that stores information, an address circuit that selects a specific memory cell from the outside, a timing circuit that controls reading / writing of information, and the like. In RAM, a plurality of memory cells are arranged in a matrix. Since the operation of selecting a desired memory cell from the plurality of memory cells is performed by designating the intersection of the matrix, the access time is constant regardless of the position (address) of the memory cell.

RAMs are bipolar RAMs and MOSRAs.
It is roughly classified into M and 2.

Bipolar RAM has the following advantages.

(1) It operates at a higher speed than a MOSRAM.

(2) The operation of the memory cell is static type,
Easy to control timing.

On the other hand, the bipolar RAM has the following drawbacks.

(3) Compared with the MOSRAM, the power consumption (particularly when not operating) is large.

(4) Compared with the MOSRAM, the manufacturing process is complicated and it is difficult to obtain high integration. Bipolar RAMs are classified into two types, TTL type and EOL type, depending on the difference in input / output level. Bipolar RAM with TTL interface
Access time (readout time) is 30 to 60 (nsec)
, ECL interface bipolar R
The access time of AM is in the range of 4-35 (nsec).

Therefore, the bipolar RAM is applied to various memory systems which require high speed.

On the other hand, compared with the bipolar RAM, the MOS
RAM has simple structure and manufacturing process,
It is advantageous in terms of storage density and price, and is used in areas that do not require high-speed operation.

MOSRAM is classified into a dynamic type and a static type.

In a dynamic MOSRAM, its memory cell is composed of relatively few transistors, that is, 1 to 3 transistors per bit (1 to 3 transistors / bit). Therefore, if the chip area is the same, the bit density is higher than that of the static type MOS RAM described later.

In the dynamic type MOSRAM,
Information is stored as a charge on the capacitance in the memory cell.
Since the electric charge accumulated in the capacitor is discharged by a leak current or the like, it is necessary to read the information in the memory cell and rewrite it (refresh) within a predetermined time.

On the other hand, static type MOSRA
In M, as its memory cell, a flip-flop circuit generally composed of six elements is used. Therefore, the refreshing which is required in the dynamic MOSRAM is not required.

The access time of the dynamic MOSRAM is in the range of 100 to 300 (nsec), and the access time of the static MOSRAM is 30 to 200.
It is in the range of (nsec). Moreover, the access time of the MOS RAM is a large value as compared with the bipolar RAM.

On the other hand, the device size of MISFET in a semiconductor integrated circuit is being reduced by improving the photolithography technique. The IEEE JOUR published in October 1982.
NALOF SOLID-STATE CIROUIT, VOL. SC-17, NO.5, pages 793 to 797 uses wafer process technology with a design rule of 2 (μm) and access time 65 (n
sec) Operation power consumption 200 (mW), standby power consumption 10
A (μW) 64K-bit static MOS RAM is described.

On the other hand, as an example of the ECL type bipolar RAM, the access time is 15 (nsec) and the power consumption is 800.
(MW) 4K-bit ECL type bipolar RAM is manufactured and sold by the present applicant under the product name HM100474-15.

As described above, the characteristics of the high speed and high power consumption bipolar RAM and the low speed and low power consumption MOSR
Independent of the characteristics of AM, there is a technological trend of increasing the storage capacity of semiconductor memories such as 1K bit, 4K bit, 16K bit, 64K bit, 256K bit, 1M bit ....

[0021]

Considering the power consumption of the semiconductor memory and the current photolithography technology that determines the element size of the bipolar transistor, the storage capacity of the bipolar RAM will be limited to 16 Kbits.

On the other hand, as the storage capacity of the semiconductor memory increases (especially 64 Kbits or more), the semiconductor chip area also increases, and the signal lines of the RAM address circuit are arranged over a long distance on the large area semiconductor chip. To be done. As the distance of the signal line of the address circuit becomes longer, the stray capacitance of this signal line naturally increases and the equivalent distributed resistance of this signal line also increases. When the wiring width of the signal line of the address circuit is reduced to 2 (μm) or less by improving the photolithography technique for miniaturization, the equivalent distributed resistance of the signal line further increases. In addition, since the fan-out of each circuit increases as the capacity increases, the load capacity due to the gate capacity of the next-stage MOS also increases. Therefore, 2 (μm)
64K-bit MOSRA with all address circuits configured by CMOS using the photolithography technology of
In M, the access time of the address is 30 (nse
c) will be the limit.

The present invention was made by the present inventor in developing a semiconductor memory having an access time equivalent to an ECL type bipolar RAM and a power consumption equivalent to a static MOS RAM.

It is an object of the present invention to provide a semiconductor memory with high speed and low power consumption. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0025]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

CMOS circuit and bipolar transistor
Should be supplied to the internal circuit and the external terminal
Semiconductor integrated circuit comprising an output circuit for forming a signal
Output circuit that outputs signals to the above external terminals
Drive that drives the transistor and the output transistor
And the output transistor has a CMOS structure.
Power MISFET, and the above-mentioned CMOS circuit is provided to the above-mentioned drive unit.
The signal to be output formed by
Charge up or de-charge the gate capacitance of the output MISFET.
Use a bipolar transistor that is charged.

[0027]

Operation: Output M of CMOS structure having large gate capacitance
Driving the ISFET with a bipolar transistor
Form an output signal with large signal amplitude at high speed
can do.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the internal structure of a static RAM having a storage capacity of 64 Kbits and input / output in 1-bit units. Each circuit block surrounded by the broken line IC is formed on one silicon chip by the semiconductor integrated circuit technology. Static R of this embodiment
The AM has four matrices (memory arrays M-ARY1 to M-ARY4) each having a storage capacity of 16 Kbits (= 16384 bits), whereby a total storage capacity of 64 Kbits (= 65536 bits). Is to have. 4 memory arrays M-A
RY1 to M-ARY4 have the same configuration as each other, and each of them has 128 memory cells.
They are arranged in 128 rows (columns).

An address circuit for selecting a desired memory cell from a memory array having a plurality of memory cells includes an address buffer ADB and a row decoder R-DC.
R0, R-DCR1, R-DCR2, column decoder C
-DCR1 to DCR4, column switches C-SW1 to C
-SW4 and the like.

The signal circuit that handles reading and writing of information is
Although not particularly limited, it is composed of a data input buffer DIB, data input intermediate amplifiers DIIA1 to DIIA4, a data output buffer DOB, a data output intermediate amplifier DOIA, and sense amplifiers SA1 to SA16.

The timing circuit for controlling the information read / write operation is not particularly limited, but the internal control signal generation circuit COM-GE, the sense amplifier selection circuit SAS.
It is composed of C.

Row-related address selection line (word line WL1
1-WL1128, WL21-WL2128, WR11
~WR1128, WR21~WR2128 the) decoded output signal obtained based on the address signal A ₀ to A ₈ is sent from the row decoder R-DCR1, R-DCR2. Among the address signals A _{0 to} A ₈ , the address signals A ₇ and A ₈ are four memory matrixes M-ARY1.
~ Used to select one memory matrix from M-ARY4.

Address buffer ADB receives address signals A _{0 to} A ₁₅ and forms internal complementary address signals a ₀ to a ₁₅ based on the received address signals A _{0 to} A ₁₅ . The internal complementary address signal a ₀ is the same as the internal address signal a ₀ in phase with the address signal A _0.
0 and an internal address signal a ₀ whose phase is inverted with respect to the address signal A ₀ . The remaining interior complementary address signals a ₁ ~ a ₁₅ likewise is constituted by the internal address signals a ₁ ~a ₁₅ and the internal address signal a ₁ ~a _15.

Of the internal complementary address signals a _{0 to} a ₁₅ formed by the address buffer ADB, the internal complementary address signals a ₇ , a ₈ and a _{9 to} a ₁₅ are the column decoder C.
-DCR1 to C-DCR4 are supplied. The column decoders C-DCR1 to C-DCR4 decode (decode) these internal complementary address signals, and select signals (decode output signals) obtained by this decoding are stored in the column switches C-SW1 to C-SW4. Insulated gate field effect transistor for switch (hereinafter referred to as MISFET) Q ₁₀₀₁ , Q ₁₀₀₁ , Q ₁₁₂₈ , Q ₁₁₂₈ , Q ₂₀₀₁ ,
Supply to the gate electrodes of Q ₂₀₀₁ , Q ₃₀₀₁ , Q ₃₀₀₁ , Q ₄₀₀₁ , and Q ₄₀₀₁ .

Word lines WL _{11 to} WL ₁₁₂₈ , WL _{21 to} WL
_{Of the 2128} , WR _{11 to} WR ₁₁₂₈ , and WR _{21 to} WR ₂₁₂₈ , one word line designated by a combination of external address signals A _{0 to} A ₈ is the row decoder R- mentioned above.
DCR1, selected by R-DCR2, by a column decoder C-DCR1~C-DCR4 and the column switch C-SW1~C-SW4 as described above, the address signal _{A 7, A 8, A 9} ~A 15 from the outside A pair of complementary data lines designated by the combination is a plurality of complementary data line pairs D _1001, D _{1001 to} D _1128, D _1128, D _2001, D _2001.
~ D _2128, D _2128, D _3001, D ₃₀₀₁ ~ D _3128, D _3128,
It is selected from D _4001, D _{4001 to} D _4128, D ₄₁₂₈ . As a result, the memory cell M-CE located at the intersection of the selected word line and the selected complementary data line pair.
L is selected.

In the read operation, the switch MIS
_{FETQ 1, Q 1 ~Q 4,} Q 4, Q 8, Q 8, Q 12, Q 12, Q
_Although not particularly limited, ₁₆ and Q ₁₆ are turned off by the control signal output from the internal control signal generation circuit COM-GE. As a result, the common data lines CDL ₁ , CD
L _{1 to} CDL ₄ , CDL ₄ and write signal input intermediate amplifier D
IIA1 to DIIA4 are electrically separated. The information of the selected memory cell is transmitted to the common data line via the selected complementary data line pair. The information of the memory cell transmitted to the common data line is sensed by the sense amplifier and output to the outside via the data output intermediate amplifier DOIA and the data output buffer DOB.

In this embodiment, the sense amplifier is 16
Although provided individually, these sense amplifiers SA1 to S1
Among A16, one sense amplifier, that is, the sense amplifier whose input terminal is coupled to the complementary data line pair selected via the common data line is the sense amplifier selection circuit S.
Selected by the sense amplifier selection signal from ASC,
Perform a sense operation.

In the write operation, the switch MISF
ETQ ₁ , Q _{1 to} Q ₄ , Q ₄ , Q ₈ , Q ₈ , Q ₁₂ , Q ₁₂ ,
Q ₁₆ and Q ₁₆ are turned on by the control signal from the internal control signal generation circuit COM-GE. Address signal A ₇
According to A _15, for example, a column decoder C-DCR1
If There was a switch MISFET Q _1001, Q ₁₀₀₁ to the on state, the output signal of the data input intermediate amplifier DIIA1 is common data line pair CDL1, CDL1, MISFET
Complementary data line pair D via TQ ₁ , Q ₁ , Q ₁₀₀₁ , Q _{1001
Passed to 1001} , D ₁₀₀₁ . At this time, the row decoder R
If the word line WL11 is selected by -DCR1, this word line WL11 complementary data lines D _1001, D
Information corresponding to the output signal of the data input intermediate amplifier DIIA1 is written in the memory cell provided at the intersection with ₁₀₀₁ .

The common data line pair CDL1, CDL1 is
Although not particularly limited, in the present embodiment, it is composed of four sets of common data line pairs (sub-common data line pairs). In this figure, two sets of common data line pairs are shown among these four sets of common data line pairs. 2 remaining
Similarly to the common data line pair shown in the figure, the pair of common data line pairs respectively have switch MISFETs Q ₂ ,
Data input intermediate amplifier DIIA via Q ₂ , Q ₃ and Q ₃
It is designed to be combined with 1. An input terminal of one sense amplifier and one input / output electrode of 32 sets of switch MISFETs are coupled to each of the four sets of common data line pairs. That is, the first common data line pair, an input terminal of the sense amplifier SA1, the input and output terminals of the switch _{MISFETQ 1001, Q 1001 ~Q 1032,} Q 1032 is coupled to the second common data line pair , The input terminal of the sense amplifier SA2 and the switch MISF
The input / output terminals of ETQ ₁₀₃₃ , Q _{1033 to} Q ₁₀₆₄ , Q ₁₀₆₄ are coupled, and the sense amplifier S is connected to the third common data line pair.
A3 input terminal and switch MISFETs Q ₁₀₆₅ , Q
₁₀₆₅ to Q _1096, coupled input and output terminals of Q _1096, the fourth common data line pair includes an input terminal of the sense amplifier SA4, switch MISFETQ _1097, Q ₁₀₉₇ ~Q _1128,
The input / output terminals of Q ₁₁₂₈ are connected. In the write operation, these four common data line pairs are electrically coupled to each other through the switch MISFETs Q ₁ , Q _{1 to} Q ₄ , Q ₄ , but in the read operation, they are electrically isolated from each other. To be done. As a result, it is possible to reduce the stray capacitance coupled to the input terminal of the sense amplifier during the read operation, and to speed up the read operation.
In the read operation, switch MISFET
Only the sense amplifier whose input terminal is coupled to the sub-common data line pair to which the information from the selected memory cell is transmitted via is selected to execute the sensing operation. . Other common data line pair CD
The L2, CDL2 to CDL4, and CDL4 have the same configuration as the above-mentioned common data line pair CDL1 and CDL1.

In the present embodiment, the switch MISF is used.
ETQ ₁ , Q _{1 to} Q ₄ , Q ₄ , Q ₈ , Q ₈ , Q ₁₂ , Q ₁₂ ,
Although a common control signal WECS is supplied to Q ₁₆ and Q ₁₆ , a selection signal from a coder may be supplied to each switch MISFET in a column. With this configuration, it is possible to reduce the load capacitance of the data input intermediate amplifier in the write operation, and it is possible to speed up the write operation.

The internal control signal generation circuit COM-GE has 2
In response to the two external control signals CS (chip select signal) and WE (write enable signal), a plurality of control signals CS ₁ , CS ₂ , CS ₃ , WECS, WECS,
DOC etc. are generated.

The sense amplifier selection circuit SASC includes a chip select signal CS and internal complementary address signals a ₇ to a _15.
In response, the above-described sense amplifier selection signal and internal chip select signals CS, CS are formed.

FIG. 2 shows the address buffer ADB of FIG.
Row decoder R-DCR0, R-DCR1, R-DCR
2 is a block diagram showing 2 in more detail.

In FIG. 2, in the circuit of the logic symbol whose output side is marked black, the output transistor for charging and discharging the output signal line is composed of a bipolar transistor, and a transistor for logic processing such as inversion, non-inversion, NAND and NOR. Quasi-CMOS with CMOS
A circuit, and a circuit of a normal logic symbol is a pure CMOS circuit.

As shown in FIG. 2, the address buffer ADB
Receives TTL level address signals A _{0 to} A ₃ from the outside at their inputs, and outputs non-inverted outputs a _{0 to} a ₃ and inverted outputs a ₀ to
Non-inversion / inversion circuits G _{0 to} G ₃ for transmitting a ₃ to the complementary output signal line are arranged. This non-inverting / inverting circuit G
_{0 to} G ₃ are composed of a quasi-CMOS circuit as shown in FIG.

In FIG. 4, Q ₄₀ , Q ₄₂ , Q ₄₄ , Q ₄₆ ,
Q ₅₀ , Q ₅₂ , and Q ₅₃ are N-channel MISFETs, and Q ₄₁ , Q ₄₂ , Q ₄₃ , and Q ₄₉ are P-channel MISF.
ET, and Q ₄₇ , Q ₄₈ , Q ₅₁ , and Q ₅₄ are NPN bipolar transistors.

The resistor R ₄₀ and MISFET Q ₄₀ are connected to the MISFET Q ₄₁ , MISFET Q ₄₁ , from the external surge voltage applied to the input terminal.
A gate protection circuit for protecting the gate insulating film of Q ₄₂ is constructed.

[0049] For _{Q 41, Q 42, Q 43} , Q 44 is composing the two-stage cascaded CMOS inverters, signal and phase signal of the node N ₁ is transmitted to the node N _3.

Since Q ₄₅ and Q ₄₆ also form a CMOS inverter, a signal having a phase opposite to that of the node N ₃ is transmitted to the node N ₄ .

Q ₄₇ is an output transistor for charging the capacitive load C ₄₁ of the output terminal OUT, and Q ₄₈ is an output transistor for discharging the capacitive load C ₄₁ .

[0052] Q _49, Q ₅₀ also for forming a CMOS inverter, the signal at the node N ₃ and opposite phases are transmitted to node N _5.

Q ₅₂ is turned on by the signal of the node N ₃ , and the discharging transistor Q of the capacitive load C ₄₂ at the output terminal OUT is turned on.
Source follower MISF for giving base current to ₅₄
ET, Q ₅₃ operates not only as a load of the source follower MISFET Q ₅₂ but also as a switch MISFET for discharging the base accumulated charge of Q ₅₄ .

To prevent Q _{48 from} being driven in the saturation region, the source of MISFET Q ₄₅ is connected to the collector of Q ₄₈ instead of the power supply V _CC , and similarly, Q ₅₄ is prevented from being driven in the saturation region. Therefore, the point that the drain of the MISFET Q ₅₂ is connected to the collector of Q ₅₄ instead of the power source V _CC is also a great feature of the improvement.

Therefore, in the non-inverting / inverting circuit of FIG. 4, when a high level signal is applied to the input terminal IN,
Node N ₃ becomes the low level to the high level, the node N ₄ and the node N _5, the base of Q _47, since the base current is supplied via the Q _43, Q _{4 7} is turned on. Since the output terminal OUT to be in a high level, Q ₅₂ are turned on,
A base current is supplied to Q ₅₄ via this Q ₅₂ . At this time, Q ₄₆ and Q ₅₀ are on because the node N ₃ is at high level. Therefore, Q ₄₅ and Q ₅₄ are turned off because their base accumulated charges are discharged via Q ₄₆ and Q ₅₀ . Therefore, the capacitive load C ₄₁ is quickly charged by the low output impedance bipolar output transistor Q ₄₇ , and the capacitive load C ₄₂ is quickly discharged by the low output impedance bipolar output transistor Q ₅₄ .
When the charging of the capacitive load C ₄₁ is completed, the collector of Q ₄₇
When the current stops flowing in the emitter path and the discharge of the capacitive load C ₄₂ ends, the drain / source path of Q ₅₂ and the Q ₅₄
No current flows through the collector-emitter path of the.

When a low-level signal is applied to the input terminal IN of the non-inverting / inverting circuit of FIG. 4, Q ₄₇ and Q ₅₄ are turned off and Q ₄₈ and Q ₅₁ are turned on, so that a capacitive load is applied. C ₄₁
Are discharged at high speed and the capacitive load C ₄₂ is charged at high speed. At this time, the node N ₅ becomes high level, so that MI
SFET Q ₅₃ turns on. Therefore, the charge accumulated in the base of Q ₅₄ is discharged to the ground potential point at a high speed via Q _53, and the turn-off speed of Q ₅₄ is improved. Capacitive load C
_When the discharge of ₄₁ ends, no current flows in the drain-source path of Q ₄₅ and the collector-emitter path of Q ₄₈ , and when the charging of the capacitive load C ₄₂ ends, current flows in the collector-emitter path of Q _51. It stops flowing.

If the charging and discharging of the capacitive loads C ₄₁ and C ₄₂ are not performed by the bipolar transistors Q ₄₇ , Q ₄₈ , Q ₅₁ and Q ₅₄ but by the MISFET, then the MISFET Since the on resistance of is extremely large compared to the on resistance of the bipolar transistor, charging / discharging can be executed only at a low speed.

On the other hand, in the address buffer of the embodiment shown in FIG. 2, internal address signals a ₀ , a _{0 to} a ₃ , a _{3 are} inputted.
To the output signal line of the non-inverting / inverting circuit G _{0 to} G ₃
The output transistor of the bipolar
Because it is a transistor, as an output signal line of the non-inverting-inverting circuit G ₀ ~G ₃ it is placed over long distances on a semiconductor chip surface, a non-inverting-inverting circuit G ₀
It becomes possible to operate ~ G ₃ at a high speed.

The row decoder R-DCR0 of FIG. 2 operates as a predecoder of the address circuit. The row decoder R-DCR0 internal address signal a ₀ obtained from the address buffer _{ADB, a 0 ~a 3, a} 3 3 is applied input NAND circuit _{G 15 ~G 2 3, G 24} ~G 31, G ₄₀ ~ G
₄₇ and a chip select signal CS and 2-input NOR circuits G _{32 to} G ₃₉ to which the output signals of the 3-input NAND circuits G _{24 to} G ₃₁ are applied.

Row decoder RD as a predecoder
Output signal line of CR0 (that is, 3-input NAND circuit G ₁₆
To G ₂₃ , G _{40 to} G ₄₇ output signal lines and 2-input NOR circuit G
The output signal lines _{32 to} G ₃₉ ) are connected to the row decoder R- as the decoder / driver of the address circuit as shown in FIG.
Inside the DCR1 and the row decoder R-DCR2, they are arranged over a long distance in the vertical direction.

3 in the row decoder R-DCR0 shown in FIG.
Input NAND circuit _{G 16 ~G 23, G 24 ~G} 31, G 40 ~G 47
Is composed of a quasi-CMOS circuit as shown in FIG. The quasi-CMOS 3-input NAND circuit of FIG.
Channel MISFET Q _{55 to} Q ₅₇ N channel MIS
An input logic processing section composed of FETs Q _{58 to} Q ₆₁ ;
And an output section constituted by NPN bipolar output transistors Q ₆₂ and Q ₆₃ . MISFET Q ₆₁ is a switch MISFET for discharging the base accumulated charge of Q _63.
To work as.

When a high level input signal is applied to all _three input terminals IN _{1 to} IN ₃ , Q _{55 to} Q ₅₇ are turned off, Q _{58 to} Q ₆₀ are turned on, and the node N ₇ is at low level. And Q ₆₁ is turned off. Then, in the output section, Q
_{When 62} is turned off and the output terminal OUT is at the high level, the base current is supplied to Q ₆₃ via Q _{58 to} Q ₆₀ ,
Q ₆₃ turns on. The electric charge of the capacitive load C _{43 at} the output terminal OUT is discharged at high speed to the ground potential point through the collector-emitter path of Q ₆₃ , and the capacitive load C ₄₃ , the diode Q ₆₄ , and the MISFETs Q _{58 to} Q ₆₀ , Discharge current also flows through the base-emitter junction route of Q ₆₃ . Due to the voltage drop across diode Q ₆₄ at this time, Q ₆₂
Is reliably controlled off.

When a low level input signal is applied to at least one of the _three input terminals IN _{1 to} IN ₃ , the node N ₇ becomes high level, Q ₆₂ is turned on, and the capacitive load C ₄₃ is turned on. Is charged at a high rate through the collector-emitter path of Q ₆₂ . By node N ₇ is at high level, the base charges accumulated in Q ₆₁ is discharged at high speed through the drain-source path of Q _61, it is possible to improve the turn-off speed of Q _63.

Thus, the quasi-CMOS 3-input NA of FIG.
The output of the ND circuit is a bipolar transistor Q ₆₂ , Q
_Since it is composed of ₆₃ , charging of the capacitive load C ₄₃
The discharge is performed at high speed.

Since the outputs of the 3-input NAND circuits G _{24 to} G _{31 in} the row decoder R-DCR 0 of FIG. 2 are connected to the inputs of the 2-input NOR circuits G _{32 to} G _{39 over} a short distance, You may comprise with the pure CMOS circuit as shown in FIG.

The pure CMOS 3-input NAND circuit of FIG. 6 is a P channel MISFET Q _{64 to} Q ₆₆ N channel MI.
It is composed of SFETs Q _{67 to} Q ₆₉ . Since the distance of the signal line from the output terminal OUT is short as described above,
Capacitance value of the stray capacitance C _{4 4} of the output terminal OUT is small.

Therefore, charging of this small stray capacitance C ₄₄
Discharge has a relatively large on-resistance MISFET Q ₆₄ ~
Be performed by Q _66, Q ₆₇ ~Q _69, can be run at relatively high speeds. The 2-input NOR circuits G _{32 to} G _{39 in} the row decoder R-DCR0 shown in FIG. 2 are quasi CMOS as shown in FIG.
It is composed of a circuit.

The quasi-CMOS 2-input NOR circuit shown in FIG.
P channel MISFETQ₇₀, Q ₇₁, N channel M
ISFETQ₇₂~ Q₇₄An input logic processing unit configured by
And NPN bipolar output transistor Q₇₅, Q₇₆By
And an output unit configured as a unit. MISFETQ₇₄Is Q
₇₆Switch MIS for discharging base accumulated charge
Operates as a FET.

When a low level input signal is applied to all of the _two input terminals IN ₁ and IN ₂ , Q ₇₀ and Q ₇₁ are turned on,
Q _72, Q ₇₃ are turned off, the node N ₉ becomes a high level. Then, Q ₇₅ is turned on, and the capacitive load C _{45 at} the output terminal OUT is charged at high speed via the collector-emitter path of Q ₇₅ . When the node N ₉ becomes high level, Q ₇₄ is turned on, and the base accumulated charge of Q ₇₆ is Q _74.
Is discharged at high speed through the drain-source path, Q ₇₆
The turn-off speed of can be improved.

When a high-level input signal is applied to at least one of the two input terminals, for example, the input terminal IN ₁ , Q ₇₀ is turned off and Q ₇₂ is turned on, and the node N
₉ is low level. Then, Q ₇₅ is turned off at the output section, and when the output terminal OUT is at a high level, Q ₇₂ , Q
_The base current is supplied to Q ₇₆ via ₇₇ , and Q ₇₆ is turned on. The electric charge of the capacitive load C _{45 at} the output terminal OUT is discharged at high speed through the collector-emitter path of Q ₇₆ , and the capacitive load C ₄₅ , the diode Q ₇₇ and the MISFET are discharged.
The drain-source path of Q _72, also a discharge current flows in the route of the base-emitter junction of Q _76. The voltage drop across diode Q ₇₇ at this time ensures that Q ₇₅ is off.

The row decoders R-DCR1 and RD shown in FIG.
CR2 operates as a decoder driver of the address circuit. The row decoder R-DCR1 the row decoder R-DCR0 2-input NOR circuit G ₄₈ which receives the output signal of 2-input NAND circuit which receives the output signals of the row decoder R-DCR0 the 2-input NOR circuit G ₄₃ G _{49 to} G ₅₆ , and inverters G _{57 to} G ₆₄ for receiving the output signals of these 2-input NAND circuits G _{49 to} G ₅₆ .

Output of 2-input NOR circuit G ₄₈ and 2-input NA
The distance of the signal lines from the inputs of the ND circuits G _{49 to} G ₅₆ is long, and the stray capacitance value of these signal lines is large. Therefore, the 2-input NOR circuit G ₄₈ is composed of a quasi-CMOS circuit as shown in FIG.

Since the outputs of the two-input NAND circuits G _{49 to} G _{56 in} the row decoder R-DCR 1 shown in FIG. 2 are connected to the inputs of the inverters G _{57 to} G _{64 over} a short distance, as shown in FIG. It is composed of a pure CMOS circuit.

The pure CMOS 2-input NAND circuit shown in FIG. 9 is a P channel MISFET Q ₈₂ , Q ₈₃ N channel MI.
It is composed of SFETs Q ₈₄ and Q ₈₅ . Since the distance of the signal line from the output terminal OUT is short as described above,
The stray capacitance C ₄₇ of the output terminal OUT has a small capacitance value.

Therefore, charging of this small stray capacitance C ₄₇
MISFET Q ₈₂ with a relatively large on-state discharge
It is executed by the _{Q 83, Q 84, Q 85} , a small stray capacitance C
₄₇ charge / discharge is executed at high speed.

The outputs of the inverters G _{57 to} G ₆₄ in the row decoder R-DCR1 of FIG. 2 are the memory array M-ARY.
It is connected to one word line WL _{11 to} WL ₁₈ . Therefore, the row decoder R-DC as a decoder driver
R1 of the output signal line (i.e. the output signal line of the inverter G ₅₇ ~G _64), the memory as a word line WL ₁₁ to WL ₁₈
For placement over a long distance in the lateral direction within the array M-ARY1, stray capacitance of the word line WL ₁₁ to WL ₁₈ is extremely large.

Thus, the row decoder R-DCR shown in FIG.
The inverters G _{57 to} G _{64 in} No. 1 are quasi-C as shown in FIG.
It is composed of a MOS circuit.

The quasi-CMOS inverter shown in FIG. 10 has a P-channel MISFET Q ₈₆ and an N-channel MISFET.
Q _{87 to} Q ₈₉ , NPN bipolar driver output transistor Q ₉₀ ,
It is constituted by Q _{9 1.} The operation of this quasi-CMOS inverter is the inverting output OUT of the non-inverting / inverting circuit of FIG.
Since the operation of the Q _{49 to} Q ₅₄ circuit is the same as that of the Q _{49 to} Q ₅₄ circuit, detailed description thereof will be omitted. However, the large stray capacitance C ₄₈ is charged and discharged at high speed by the NPN bipolar output transistors Q ₉₀ and Q _91. It

In FIG. 2, the row decoder D-DCR2
Is configured in the same manner as R-DCR1 described above.

FIG. 3 shows the address buffer ADB of FIG.
6 is a block diagram showing the column decoder C-DCR1 and the like in more detail.

In FIG. 3 as well, in the circuit of the logic symbol whose output side is marked black, the output transistor for charging and discharging the stray capacitance of the output signal line is composed of a bipolar transistor, and is inverted, non-inverted, NAND, NOR.
Quasi-CMO in which logical processing such as is executed by a CMOS circuit
It is an S circuit, and the circuit of the normal logic symbol is pure CMOS.
Circuit.

As shown in FIG. 3, the address buffer ADB
Are externally supplied with TTL level address signals A _{7 to} A _15.
At its input, and the non-inverted outputs a _{7 to} a ₁₅ and the inverted output a ₇
Inverting-inverting circuit G ₇ ~G ₁₅ for delivering ~a _{1 5} to the complementary output signal lines are arranged.

The non-inverting / inverting circuits G _{7 to} G ₁₅ are shown in FIG.
It is composed of a quasi-CMOS circuit as shown in FIG. Accordingly, Me barrel output transistor of the non-inverting-inverting circuit G ₇ ~G ₁₅ is configured by a bipolar transistor as shown in FIG. 4, the output signal lines of the non-inversion and inversion circuit G ₇ ~G ₁₅ is a semiconductor chip Even if they are arranged over a long distance on the surface, the non-inverting / inverting circuits G _{7 to} G ₁₅ can be operated at high speed.

The column decoder C-DCR1 has internal address signals a ₇ -a obtained from the address buffer ADB.
2-input NAND circuit G ₇₄ to which ₁₅ and a _{7 to} a ₁₅ are applied
It includes G ₇₇ , G _{78 to} G ₈₁ , G _{82 to} G ₈₅ , and 3-input NAND circuits G _{86 to} G ₈₉ .

[0085] As further shown in FIG. 3, in the column decoder C-DCR1, these NAND circuits G ₇₄ ~
Since the output signal line of G ₉₃ is arranged over a long distance and is connected to the input terminals of many NOR circuits G _{94 to} G ₉₅ , the stray capacitance of the output signal line of these NAND circuits G _{74 to} G ₉₃ is large. Has a large capacitance value.

Therefore, the 3-input NAND circuits G _{86 to} G
₈₉ is a quasi-CMOS 3-input NAND circuit as shown in FIG. 5, and 2-input NAND circuits G _{74 to} G ₈₅ are
It is composed of a quasi-CMOS 2-input NAND circuit in which the input terminal IN ₃ and the MISFETs Q ₅₇ and Q ₆₀ are omitted from FIG.

On the other hand, in FIG. 3, the 3-input NOR circuit G
The output signal lines of ₉₄ and G ₉₅ are short distance inverters G ₁₀₀ and G
_Since these are connected to ₁₀₁ inputs, these 3 inputs NO
The capacitance value of the stray capacitance of the output signal lines of the R circuits G _{94 to} G ₉₅ is small. Therefore, these 3-input NOR circuits G _{94 to} G
_{Reference numeral 95} is a pure CMOS / 3-input OR circuit. Furthermore, since the output signal line of the inverter G _100, G ₁₀₁ is connected to the input terminal of 2-input NOR circuit G _98, G ₉₉ a short distance, the stray capacitance of the output signal lines of the inverters G _100, G ₁₀₁ Has a small capacitance value. Therefore, these inverters G ₁₀₀ and G ₁₀₁ are composed of well-known pure CMOS inverters.

Further, the output signal lines of the two-input NOR circuits G ₉₈ and G ₉₉ are arranged in a relatively short distance and the column switch C-SW _{1 is used.}
Since these are connected to the gate electrodes of the switching MISFETs Q ₁₀₀₁ and Q ₁₀₀₁ , these NOR circuits G ₉₈ and G ₉₉ are connected.
The output signal line has a small stray capacitance. Therefore, these N
The OR circuit is a pure CMOS / 2-input NOR as shown in FIG.
It is composed of a circuit.

[0089] pure CMOS · 2-input NOR circuit is a P-channel MISFET Q ₇₈ in FIG. 8, Q _{7 9,} N-channel M
It is composed of ISFETs Q ₈₀ and Q ₈₁ . Since the distance of the signal line from the output terminal is relatively short, the output terminal OU
The capacitance value of the stray capacitance C ₄₆ of T is small.

Therefore, charging of this small stray capacitance C ₄₆
MISFET Q ₇₈ with a relatively large on-state discharge
Even if executed by Q ₇₉ , Q ₈₀ , Q ₈₁ , small stray capacitance C
₄₆ charging and discharging is performed at high speed.

The three-input NOR circuits G _{94 to} G described above are used.
_Reference numeral ₉₅ denotes the second input NOR circuit of FIG.
₃ is added and its gate is connected to the input terminal IN ₃
Connected to the third P-channel MISFET Q ₇₈ , Q
Was inserted in series with _79, the third N-channel MISFET Q _80, Q whose gate is connected to the input terminal IN ₃
It is composed of a pure CMOS / 3-input circuit inserted in parallel with ₈₁ .

Further, FIG. 3 shows the memory array M of FIG.
The 1-bit memory cell M-CEL of ARY1 is shown in more detail.

This memory cell M-CEL has a load resistance R
₁ and R ₂ and N channel MISFETs Q ₁₀₁ and Q _102.
It is composed of a flop and N-channel MISFETs Q ₁₀₃ and Q ₁₀₄ for transmission gates.

Flip-flops are used as information storage means. The transmission gate is controlled by the address signal applied to the word line WL ₁₁ connected to the row decoder R-DCR1, and the complementary data line pair D
Information transmission between ₁₀₀₁ , D ₁₀₀₁ and the flip-flop is controlled by this transmission gate.

FIG. 11 shows the sense amplifier selection circuit S of FIG.
An example of main part of ASC and internal control signal generation circuit COM-
It is a circuit diagram which shows an example of GE in more detail.

In the figure, the sense amplifier selection circuit SASC is shown.
Of these, receiving a chip select signal CS from the outside,
Data output intermediate amplifier DOIA, row decoder R-DC
The circuit of the part that forms the control signals CS, CS supplied to the R0 and the column decoder C-DCR1 and the like is shown.

The circuit of this portion to which the chip select signal CS from the outside is applied is composed of the same circuit as the non-inverting / inverting circuit of FIG. Output signal CS of this circuit
Is obtained from the bipolar transistors T ₁ , T ₂ , T ₃ , and T ₄ , the output C of the sense amplifier selection circuit SASC is obtained.
The capacity dependence of the charge and discharge rates of S and CS is small. Therefore, the output CS of the sense amplifier selection circuit SASC is the input terminals of the NOR gates G _{32 to} G ₃₉ of the row decoder R-DCR 0 of FIG. 2 and the N of the column decoder C-DCR 1 of FIG.
Even if it is connected to the input terminals of the OR gates G _{94 to} G ₉₅ , this output CS becomes high speed. In addition, the sense amplifier selection circuit S
Even if the output CS of the ASC is connected to the gate electrodes of the plurality of switch MISFETs in the data output intermediate amplifier DOIA, the output CS becomes high speed.

Although not shown in the figure, the sense amplifier selection circuit SASC has internal complementary address signals a ₇ -a.
₁₅ and a decoder circuit for receiving the control signal CS and forming a selection signal S1 to be supplied to the sense amplifier.
With this decoder circuit. , Sense amplifiers SA1 to S
Among A16, a sense amplifier whose input terminal is electrically coupled to the complementary data line pair to be selected is selected,
The sense operation is executed. The output part of this decoder circuit is composed of a quasi-CMOS circuit, and the capacity dependence of the output charge / discharge is reduced. As a result, the operation of selecting the sense amplifier can be speeded up. Even if the control signal is supplied to the decoder circuit, the control signal CS is high speed because the control signal is formed by the bipolar transistor as described above.

In this embodiment, the decoder circuit is provided in the sense amplifier selection circuit SASO in order to select the sense amplifier. However, the column decoder C-DCR1
The selection signal formed by C-DCR4 may be used as the selection signal of the sense amplifier. By doing so, the number of elements can be reduced, and high integration can be achieved.

Internal control signal generation circuit COM-G of FIG.
E is a plurality of internal delay chip select signals C when the chip select signal CS from the outside is applied.
It has a circuit section for generating S ₂ , CS ₁ , CS ₁ , and CS ₂ . Most of this circuit portion is composed of a CMOS circuit. However, these outputs CS ₂ , CS ₁ , CS ₁ , CS ₂
Is a bipolar output transistor T ₅ , T ₆ , T ₉ , T ₁₀ ,
Since it is obtained from T ₁₁ , T ₁₂ , T ₇ , and T ₈ , the capacity dependency of charging / discharging of these outputs is small.

Internal control signal generation circuit COM-G of FIG.
Further, E is a circuit unit for generating write control signals WECS and WECS and a data output buffer control signal DOC by applying a write enable signal WE from the outside to internal delay chip select signals CS ₁ and CS _2. Have. Most of this circuit portion is also composed of a CMOS circuit. However, since the signal WECS is obtained from the bipolar output transistors T ₁₄ and T ₁₅ , the charge / discharge capacity dependence of the output WECS is small. Therefore, this output WECS is the column decoder C-DC of FIG.
Multiple input terminals of the NAND (not shown) of R1 or switch MISFETs Q ₁ and Q _{1 of} FIG.
Even when applied to the gate electrodes of Q ₁₆ and Q ₁₆ , this output WE
CS will be faster.

FIG. 12 shows the sense amplifier SA1, the data output intermediate amplifier DOIA, and the data output buffer DO of FIG.
FIG. 6 is a circuit diagram showing in more detail by B and the like.

FIG. 13 shows the data input buffer DI of FIG.
FIG. 6 is a circuit diagram showing in more detail B, the data input intermediate amplifier DIIA1, and the like.

FIG. 14 is a signal waveform diagram of each part at the time of reading and writing of the static RAM of the embodiment shown in FIGS. 1 to 13.

First, the operation of reading information from the static RAM will be described with reference to FIGS. 12 and 14.

As shown in FIG. 14, address signals A _{0 to} A ₀
It is assumed that the chip select signal CS changes to low level at the same time that ₁₅ is applied and the write enable signal WE is held at high level. Internal control signal generation circuit CO
From M-GE, as shown in FIG. 14, internal delay chip select signals CS ₁ , CS ₂ , CS ₃ and write control signal W are shown.
An ECS and data output buffer control signal DOC is generated.

When the supplied address signals A _{0 to} A ₁₅ are address signals designating the word line WL ₁₁ and the complementary data line pair D ₁₀₀₁ and D _1001, for example, the word line WL ₁₁ and the complementary data line pair D _The memory cell M-CEL provided at the intersection of ₁₀₀₁ and D ₁₀₀₁ is selected. Internal information of the selected memory cell M-CEL is complementary data line pair D _{10 01,} D _1001, switching MISFET Q _1001, Q
_It is transmitted to both inputs of the sense amplifier SA1 via ₁₀₀₁ . The sense amplifier SA1 composed of differential pair transistors T _21, which are emitter-coupled, T ₂₂ a constant current source MISFETT ₂₀ Prefecture. When the high-level selection signal S1 is applied from the sense amplifier selection circuit SASC to the gate electrode of the constant current source MISFETT ₂₀ , the sense amplifier SA1 executes the sensing operation.

Data output from sense amplifier selection circuit SASC Constant current source MISFET T ₂₃ of intermediate amplifier DO1A
When the high level internal chip select signal OS is applied to the gate electrode of T ₂₆ , the data output intermediate amplifier DOIA
Performs an amplifying operation.

Therefore, the output signal of the sense amplifier SA1 is the grounded base transistors T ₂₇ , T ₂₈ , the emitter follower transistors T ₂₉ , T ₃₀ , the output MISFET T ₃₅ ,
It is transmitted to the output node N ₁₁ of the data output intermediate amplifier DOIA via T ₃₈ .

As shown in FIG. 12, the data output buffer D
The data output buffer control signal DOC is supplied to the OB from the internal control signal generation circuit COM-GE. Also, FIG.
As shown in FIG. 2, the data output buffer DOB has T ₃₉ , T
₄₀ pure CMOS inverters, T _{41 to} T ₄₈ quasi-CMOS
2-input NAND circuit, quasi-CMOS 2-input NOR circuit of T _{49 to} T ₅₆ , MISFETT for P-channel switch
₅₇ , an N-channel switch MISFET ₅₈ , a P-channel output MISFET T ₅₉ , and an N-channel output MISFET T ₆₀ .

When the data output buffer control signal DOC is at the high level, the switch MISFETs T ₅₇ and T ₅₈ are turned on, and the output MISFETs T ₅₉ and T ₆₀ are turned off at the same time. Output Do
ut becomes high impedance (floating) state.

At the time of reading information, the data output buffer control signal DOC becomes low level, and the switch MISF is used.
T ₅₇ and T ₅₈ of ET are turned off, and the quasi-C in response to the signal level of the output node N ₁₁ of the data output intermediate amplifier DOIA.
The gate electrodes of T ₅₉ and T ₆₀ of the output MISFET are controlled by the output of the MOS / 2-input NAND circuit and the output of the quasi-CMOS / 2-input NOR circuit, and effective data is obtained from the output terminal Dout. T _{59 of} output MISFET,
To reduce the on-resistance of T ₆₀ , these MISFETs
The channel width W of is set to an extremely large value.
Then, although the gate capacitances of these MISFETs T ₅₉ and T ₆₀ are extremely large, they are quasi-CMOS 2-input NA.
The output part of the ND circuit is a bipolar output transistor T ₄₇ ,
It is constituted by a T _48, the output section of the quasi-CMOS-2-input NOR circuit because it is constituted by a bipolar output transistor T _55, T _56, charging and discharging of the gate capacitance of the T _59, T ₆₀ of the output MISFET is It runs at high speed.

Next, the operation of writing information in the static RAM will be described with reference to FIGS. 13 and 14.

As shown in FIG. 14, address signals A _{0 to} A ₀
At the same time that ₁₅ is applied, the chip select signal CS changes to low level, and then the write enable signal WE changes to low level. Internal control signal generation circuit COM-G
From E, as shown in FIG. 14, internal delay chip select signals CS ₁ , CS ₂ , CS ₃ , write control signal WECS,
The data output buffer control signal DOC is generated.

As shown in FIG. 13, the input data Din and the inverted internal chip select signal CS ₁ are applied to the data input buffer DIB. At the time of writing information, the signal CS ₁ changes to low level. Then, for the P channel switch of the data input buffer, MISFETT ₆₁
Is on, for N channel switch, MISFETT _{6 2}
Changes off. As a result, pure CMs connected in multiple stages
The input data Din is transmitted to the output node N ₁₂ via the OS / inverter.

At the time of writing information, the write control signal W
EOS changes to low level. Then, in the data input intermediate amplifier DIIA1 of FIG.
ISFET T ₆₃ and T ₆₅ are ON, N-channel MISF
ETT _64, T ₆₆ are turned off, appear the output node N ₁₂ and the phase signal of the data input buffer DIB is the node N _13, which opposite phase signal appears on node N _14.

The common data line CD is passed through the quasi-CMOS inverter composed of the signals T _{67 to} T ₇₂ of the node N _13.
The signal of the node N ₁₄ transmitted to L ₁ is transmitted to the common data line CDL ₁ via the quasi-CMOS inverter composed of T _{73 to} T ₇₈ . The common data line pair CDL ₁ and CDL ₁ having a large parasitic capacitance are charged and discharged by these quasi-CMOs.
S-inverter bipolar output transistors T ₇₁ , T
₇₂ , T ₇₇ , and T ₇₈ , these charge and
The discharge is performed at high speed.

Thus, the data input intermediate amplifier DIIA
The complementary output signal of 1 is the common data line pair CDL ₁ , CDL ₁
MISFET for switch, Q ₁ , Q ₁ , Q ₁₀₀₁ , Q ₁₀₀₁ ,
The data is transmitted to the memory cell M-CEL through the complementary data line pair D ₁₀₀₁ and D ₁₀₀₁ and writing of information to the memory cell is executed.

[0119]

【The invention's effect】

(1) Non-inversion / inversion circuit G of the address buffer ADB
_{0 to} G ₁₅ are composed of quasi-CMOS circuits. In this quasi-CMOS circuit, most of the non-inversion / inversion logic processing section is composed of a CMOS circuit, and thus low power consumption is possible. Furthermore, since the output transistor that executes the charging / discharging of the non-inverting / inverting output is composed of the bipolar transistor, the bipolar transistor can obtain a small output resistance even with a small element size as compared with the MISFET. Even if the stray capacitance of the output signal lines of the inverting circuits G _{0 to} G ₁₅ becomes large, high speed operation is possible.

(2) Row decoders R-DCR0, R-DCR1, R
-DCR2 of NAND circuit _{G 16 ~G 23, G 24 ~G} 31, G
Circuits having a large stray capacitance of the output signal line, such as _{40 to} G ₄₇ , NOR circuits G _{32 to} G ₃₉ , G _{48 to} G ₆₅ , and inverters G _{57 to} G ₆₄ , are configured by quasi-CMOS circuits, and therefore these circuits are used. Can have low power consumption and high speed.

Furthermore, since circuits such as the NAND circuits G _{49 to} G ₅₆ having a small stray capacitance on the output signal line are composed of pure CMOS circuits, it is possible to reduce the power consumption of these circuits.

(3) Since circuits with large stray capacitances of output signal lines, such as the NAND circuits G _{74 to} G ₈₅ of the column decoders C-DCR1 to C-DCR4, are composed of quasi-CMOS circuits, these circuits are low-powered. Power consumption and high speed can be achieved.

Further, since the circuits with small stray capacitances of the output signal lines, such as the NOR circuits G _{74 to} G ₉₉ and the inverters G ₁₀₀ and G ₁₀₁ , are composed of quasi-CMOS circuits, these circuits can be made to consume less power. be able to.

(4) Since the non-inverting / inverting circuit forming the sense amplifier selection circuit SASC is composed of a quasi-CMOS circuit, low power consumption is achieved and outputs CS, CS are provided.
Is obtained from the bipolar output transistor, the outputs CS, CS have a high speed even if the stray capacitances of the outputs CS, CS are large.

(5) The internal control signal generation circuit COM-GE is a quasi-CMO.
Since it is composed of an S circuit, low power consumption is achieved and outputs CS ₂ , CS ₃ , CS ₁ , CS ₁ , WE
Since CS is derived from a bipolar output transistor,
Even if the stray capacitance of these outputs is large, these outputs C
_{S 2, CS 3, CS 1} , CS 1, WECS becomes faster.

(6) Since the data output buffer DOB is composed of a quasi-CMOS circuit, low power consumption is achieved.

Furthermore, since the large gate capacitance of the output MISFET of the data output buffer DOB is charged / discharged by the bipolar output transistor, this gate capacitance is charged / discharged at a high speed. It The data output buffer DOB can form a relatively large output voltage because the output transistor is a MISFET. As a result, the change from one output level to the other output level becomes relatively large. As described above, due to the driving of the output transistor by the bipolar transistor and the rapid change of the output level by the output MISFET itself, the data output buffer operates at a sufficiently high speed.

(7) Since the data input buffer DIB is composed of a pure CMOS circuit, low power consumption is achieved.

(8) The data input intermediate amplifier DIIA1 is a quasi-CMOS
Since it is composed of a circuit, low power consumption is achieved.

Furthermore, since charging / discharging of the common data line pair CDL ₁ , CDL ₁ having a large parasitic capacitance is executed by the bipolar output transistor, these charging / discharging are executed at high speed.

Due to the above synergistic effect, this static S
The following characteristics could be obtained in the RAM.

(A) Non-inversion / inversion circuit G of the address buffer ADB
The propagation delay time tpd from _{0 to} G ₁₅ from input to output is about 3.
It was shortened to 0 (nsec), the standby power consumption of the entire non-inverting / inverting circuits G _{0 to} G ₁₅ was reduced to about 33.7 (mW), and the operating power consumption was reduced to about 45.8 (mW). .

(B) Row decoders R-DCR0, R-DCR1, R
-DCR2, column decoder C-DCR1 to C-DCR
Propagation delay time tpd from input of 4 to consumption is about 4.8 (n
sec) and the total standby power consumption is almost zero,
The power consumption during operation was reduced to about 153 (mW).

(C) Memory cell M-CEL, sense amplifier SA
1, the propagation delay time tpd of the entire data output intermediate amplifier DOIA is reduced to about 5.0 (nsec), and 64K (6553)
6) All memory cells M-CEL, sense amplifier S
The standby power consumption of the entire A1 to SA16 and the data output intermediate amplifier DOIA was reduced to about 0.6 (mW), and the operating power consumption was reduced to about 160 (mW).

(D) The propagation delay time tpd from the input to the output of the data output buffer DOB is shortened to about 2.8 (nsec), the standby power consumption is almost zero, and the operating power consumption is 23.5.
(MW).

(E) By the above (a) to (d), the access time (reading time) is shortened to about 15.6 (nsec), which is almost the same value as the access time (nsec) of the ECL type bipolar RAM. was gotten.

(F) The static SR according to (a) to (d) above.
The standby power consumption of the AM as a whole is about 34.3 (mW), and the power consumption during operation is about 382.3 (mW), which is low between the conventional bipolar RAM and the conventional static MOSRAM (close to the conventional static MOSRAM). The power consumption characteristics were obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the memory cell M-CEL of FIG. 3, the load resistors R ₁ and R ₂ are P-channel MISFE.
Instead of T, a CMOS inverter may be used to form a flip-flop. Further, the flip-flop may be configured by a multi-emitter NPN transistor.

Further, by refreshing, the memory cell M-CEL may be configured not by a flip-flop circuit but by an information temporary storage type circuit by accumulating charges in the cell capacitance.

Further, the signal levels of the address signals A _{0 to} A ₁₅ applied to the address buffer ADB are not the TTL level but the ECL level and are set to the address buffer ADB.
May be configured to execute an appropriate level conversion operation.

Further, the input Din and the output Dout may be constructed in a format of a plurality of bits (for example, 4 bits, 8 bits ...) Instead of 1 bit.

The number of memory matrices is not limited to four and may be more or less.

In the above description, the case where the invention made by the present inventor is mainly applied to the semiconductor memory has been described, but the present invention is not limited thereto.

For example, on a semiconductor chip, only an address circuit for selecting a specific cell of a memory cell, a signal circuit for handling reading / writing of information, and a timing circuit for controlling an operation of reading / writing information are used. , As required, bipolar analog circuit, MOS analog circuit, P channel MOS logic, N channel MOS logic, CMOS logic, I ² L circuit,
It goes without saying that any of the ECL circuits can be arranged on the semiconductor chip.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of a static RAM according to an embodiment of the present invention.

2 is a block diagram showing the address buffer ADB, row decoders R-DCR0, R-DCR1 and R-DCR2 of FIG. 1 in more detail.

3 is a block diagram showing the address buffer ADB, column decoder C-DCR1 and the like of FIG. 1 in more detail.

FIG. 4 is a circuit diagram showing a quasi-CMOS / non-inverting / inverting circuit.

FIG. 5 is a circuit diagram showing a quasi-CMOS 3-input NAND circuit.

FIG. 6 is a circuit diagram showing a pure CMOS / 3-input NAND circuit.

FIG. 7 is a circuit diagram showing a quasi-CMOS 2-input NOR circuit.

FIG. 8 is a circuit diagram showing a pure CMOS 2-input NOR circuit.

FIG. 9 is a circuit diagram showing a pure CMOS 2-input NAND circuit.

FIG. 10 is a circuit diagram showing a quasi-CMOS inverter.

11 is a circuit diagram showing the sense amplifier selection circuit SASC and internal control signal generation circuit COM-GE in FIG. 1 in more detail.

12 is a circuit diagram showing in more detail the sense amplifier SA1A, the data output intermediate amplifier DOIA, the data output buffer DOB, etc. of FIG.

13 is a circuit diagram showing the data input buffer DIB, the data input intermediate amplifier DIIA1, etc. of FIG. 1 in more detail.

FIG. 14 is a signal waveform diagram of each part at the time of reading and writing of the static RAM of the embodiment shown in FIGS. 1 to 13.

[Explanation of symbols]

M-CEL ... memory cell, ADB ... address buffer,
R-DCR0, R-DCR1, R-DCR2 ... Row Deco
, C-DCR1 to C-DCR4 ... column decoder,
C-SW1 to C-SW4 ... Column switch, DIB ...
Data input buffer, DIIA1 to DIIA4 ... Data input
Power intermediate amplifier, SA1 to SA16 ... Sense amplifier, DO
IA ... Data output intermediate amplifier, DOB ... Data output buffer
FA, COM-GE ... Internal control signal generation circuit, SASC
... sense amplifier selection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masanori Odaka, Masanori Kodaka, 1450, Kamimizumoto-cho, Kodaira-shi, Tokyo, Hitachi Device Development Center (72) Inventor, Hideaki Uchida 111, Nishiyote-cho, Takasaki-shi, Gunma Hitachi, Ltd. (56) References JP 48-39157 (JP, A) JP 58-125291 (JP, A) JP 59-149733 (JP, U) JP 55-152728 (JP) , U)

Claims (3)

[Claims] 1. A semiconductor integrated circuit comprising an internal circuit formed by combining a CMOS circuit and a bipolar transistor, and an output circuit for forming a signal to be supplied to an external terminal, wherein the output circuit is the external circuit. comprising an output transistor for outputting a signal to the terminal, and a driving unit for driving the output transistor, the output transistor, the external end of the drain
1st MI of P channel which outputs the signal which should be supplied to the child
SFET and its drain should be supplied to the above external terminal.
From the second N-channel MISFET that outputs a signal
And the driving unit drives the first output MISFET to drive the first
Driving unit and second driving unit for driving second output MISFET
And the signal formed by the CMOS circuit
The current is amplified and the first MISFET and the second MISF are amplified.
Charge up or disable the gate capacitance of ET.
A semiconductor integrated circuit comprising a bipolar transistor for charging . 2. The first driving unit receives an input signal to be output and
The first control signal and the first control signal is at a first level
, The first output MISF according to the input signal
ET is driven and the first control signal is different from the first level.
When the second level is
Drive control for turning off the first output MISFET
A first CMOS logic circuit that forms a control signal, and the second driving unit outputs the input signal to be output and the first control circuit.
Receives the second control signal whose phase is inverted from that of the control signal,
When the second control signal is at the second level, the input
Drive the second output MISFET according to the force signal,
When the second control signal is at the first level, the input
The second output MISFET is turned off regardless of the force signal.
Second CMOS theory for forming a drive control signal that causes a state
The semiconductor integrated circuit of Claims paragraph 1, wherein a is intended to include physical circuitry. 3. The first drive circuit comprises the first output MIS.
The first control signal is provided between the gate and the source of the FET.
Signal and it is turned on when it is at the second level above.
A third P-channel type MISFET, and the second driving unit has a gate of the second output MISFET.
It is provided between the sources and receives the second control signal
N channel turned on at the first level
3. A semiconductor integrated circuit according to claim 2, further comprising a fourth type MISFET .