JPS59139727A - Cmos integrated circuit device - Google Patents

Abstract

PURPOSE:To give direct access to a CMOS static RAM through an ECL circuit and to facilitate production of a CMOS IC device by using an input level converting circuit which receives a signal of a level of emitter coupled logic ECL and converts it into a CMOS signal. CONSTITUTION:An input level converting circuit is provided to a CMOS IC device to receive a signal of ECL level and converts it into a signal of MOS level. Then an external address or a control signal is supplied to the base of an nMOS FETQ10 from a terminal ECLIN. A differential nMOSFETQ9 is connected to the FETQ10, and the reference voltage Vref for level dicision is applied to the base of the FETQ9. Then a constant current source containing an nMOSFETQ13 is connected to a common source. While pMOSFETs Q11 and Q12 which work as current mirror type active loads are connected to the drains of FETs Q9 and Q10 respectively. The voltage Vref is produced by a circuit consisting of partial pressure resistances R3 and R4, MOSFETs Q1-Q8, etc. Then direct access is given to a CMOS RAM through an ECL circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMO3 (complementary metal-insulator-semiconductor) integrated circuit device.

0MO8- in which CMOS static type RAM (Random Access Memory) is directly accessed by ECL (emitter coupled logic) circuit.
ECL compatible RAM is l5SCDIGIIST
OF TIICHNCAL PAPBR3 magazine 198
2, February issue, pp. 248-249.

FIG. 1 shows a reference voltage generation circuit for converting the ECL level signal to a CMOS level.

Since this circuit uses bipolar transistors, it is necessary to add a bipolar transistor manufacturing process to the CMO3 integrated circuit manufacturing process, which has the disadvantage of complicating the manufacturing process. Furthermore, since the 0M03 circuit and the bipolar transistor are configured on the same IC chip, there is a problem that launch-up due to a parasitic thyristor is likely to occur.

Further, FIG. 2 shows a level conversion circuit that converts an ECL level signal into a CMOS level signal using the reference voltage generated by the reference voltage generation circuit.

This circuit has the disadvantage that in addition to the large number of circuit elements (13), the current consumption is large because a relatively large bias current is flowing.

Further, FIG. 3 shows an output level conversion circuit that converts a CMOS level signal into an ECL level signal.

In this circuit, a bipolar output transistor is driven by a CMOS inverter. Therefore, when forming a high-level output signal, in order to supply a relatively large base current when the drain-source voltage of the p-channel MO3FET is almost 0 volts, its chip size must be set large ( There is a drawback.

Further, when forming a low level output signal, the n-channel MOS FET is turned on and the output transistor is turned off, so that -2 volts is output. Therefore, the operation of the ECL circuit receiving this output signal becomes slow.

The purpose of this invention is to provide EC without complicating the manufacturing process.
An object of the present invention is to provide a CMO3 integrated circuit device that operates stably upon receiving an L level signal.

Another object of the present invention is to provide a CMO5 integrated circuit device that operates in response to ECL level signals and achieves low power consumption.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 4A shows a block diagram of a CMOS static RAM to which the present invention is applied.

The figure shows a 5-bit device with a storage capacity of 16 bits and an output of 1 bit.
- The internal configuration of a RAM integrated circuit (hereinafter referred to as IC) is shown.

16 bit memory cells each with 128 columns (rows)
x 32 rows (columns) - 4 matrices (memory array M -
ARYI to M-ARY4), and each matrix is arranged in two parts on the left and right sides of the row decoder R-DCH.

Row address selection lines (word lines WLI to WL128
．． WR1 to WR128) have address signals AO-A5.
．． A12. 256 decoded output signals obtained based on A13 are sent out from the row decoder R-DCR.

In this way, the memory cell M-CEL of each matrix is connected to one of the word lines WLI to WL12B and WRI to WR12B and a complementary data line pair D11. D1
1-D132. D132.

Address signal A5. A6 is used to select only one of the four memory matrices. Address signals A7 to All are used to select one column in one selected memory matrix.

The memory matrix selection circuit GS receives the address signal A5. Decipher into four combinations based on A6.

Column decoders C-DCR1 to C-DCR4 provide 32 types of column selection decode output signals based on the address signals A7 to All, respectively.

Common data line CDL during reading.

CDL is common data line split MO3FET (Ql,
Ql;...+Q4. Q4) is divided into four for each memory matrix, and the common complementary data line pair CDL, δ lower], is commonly coupled during writing.

Sense amplifiers SAI to SA4 are provided corresponding to the divided common complementary data line pairs CDL and CDL, respectively.

The purpose of dividing the common complementary data line pair CDL, CDL and providing each with sense amplifiers SAI or SA4 in this way is to divide the parasitic capacitance of the common complementary data line pair CDL, CDL, and to improve the readout of information from the memory cell. There are ways to speed up the process.

Address buffer ADB has 14 external address signals A
14 pairs of complementary address signals from O to A13 each! θ〜
13 and decoder circuits (R-DCR, C-DC
R, GS).

The internal control signal generation circuit COM-GS receives two external control signal planes (chip select signal) and Wl (write enable signal), and generates C3l (row decoder control signal),
It sends out 5AC (sense amplifier control signal), we (write control signal), DIC (data driver control signal), etc.

The circuit operation of the MOS static type RAM will be explained according to the timing diagram of FIG. 4B.

All operations in this MOS static type RAM,
That is, the address setting operation, read operation, and write operation are performed only while one of the external control signals CS is at a low level. At this time, if the other external control signal W1 is at a high level, a read operation is performed, and if it is at a low level, a write operation is performed.

First, address setting operation and read operation will be explained.

The address setting operation is always performed based on the address signal applied during this period when the external control signal CS is at a low level. Conversely, by keeping the external control signal C8 at a high level, (
Address setting operations and read operations can be prevented.

When the external control signal C8 becomes low level, the row decoder R-DCR starts operating upon receiving a high level internal control signal C3I synchronized with this signal. The row decoder (also word driver) R-DCR has eight types of complementary address signals 10 to 5°A12. A13 is decoded to select one word line and set it to high level.

On the other hand, four memory arrays M-ARYI to M-ARY4
One of them is the memory array selection signal m1 to m
4 and one selected memory array (
For example, one complementary data line pair (for example, Dll, Dll) in the column decoder (for example, C-DC
Rl).

In this way, one memory cell is selected (address setting)
will be done.

Information of the memory cell selected by the address setting operation is sent to one of the divided common complementary data line pairs and amplified by a sense amplifier (for example, 5A1).

In this case, any one of the four sense amplifiers SAI to SA4 receives the memory array selection signals m1 to m.
4, and only one selected sense amplifier operates while receiving the high-level internal fllJII signal SAC.

In this way, power consumption can be reduced by rendering the remaining three sense amplifiers, which do not need to be used, out of the four sense amplifiers SAI N5A4 into a non-operating state. The outputs of the three sense amplifiers in the non-operating state are in a high impedance (floating) state.

The output signal of the sense amplifier is sent to the data output buffer DOB.
The signal is amplified by and sent to the outside of the IC as output data Dout.

The data output buffer DOB operates while receiving the high level control output DOC.

Next, the write operation will be explained.

When the external control signal WE becomes low level, the high level control signal we synchronized with this is applied to the component complementary data line dividing MO3FET (Ql, Ql;...;Q4.Q4
), and the common complementary data line pair CDL, CDL is commonly coupled.

On the other hand, while receiving the low level control signal DIG, the data manual buffer DIR amplifies the input data signal Din from outside the IC and sends it to the commonly coupled common complementary data line pair CDL, CDL.

The input data signal on the common complementary data line pair CDL, CDL is written into the memory cell M-CEL determined by the address setting operation.

The memory cells M-CEL have the same configuration, and although not particularly limited, as shown in detail in the figure, the memory cells M-CEL are n-channels whose gates and drains are cross-connected to each other. Memory MO3IET
Qml, Qm2, information holding resistors R1 and R2 respectively provided at their drains, and the memory MOS F B
An n-channel transmission gate MO3F is provided between TQml and Qm2 and a pair of complementary data lines, D.
It is composed of ETQn+3°Qm4.

The memory cell M-CEL retains stored information by supplying the power supply voltage Vcc to the connection point with the resistor R1°R2.

The resistors R1 and R2 are made to have a high resistance value, for example, several megohms to several gigaohms, in order to reduce the power consumption of the memory cell M-CEL in a state in which stored information is held. In order to reduce the area occupied by the memory cell, the resistors R1 and R2 are, for example, relatively high-resistance resistors formed on the surface of the semiconductor substrate forming the MOSFET via a relatively thick field insulating film. Consists of a polysilicon layer.

In order to allow the CMOS static RAM having the above configuration to be directly accessed from the ECL circuit, the following interface circuit is built-in.

FIG. 5 shows a circuit diagram of an embodiment of an input level conversion circuit that receives an ECL level signal and converts it into a CMOS level signal.

The external address signal and external control signal are ECL level input signals and are input from the terminal ECL IN.

This input signal is applied to the gate of n-channel MO3FET QIO. A reference voltage V ref for level determination is applied to the gate of the n-channel MOSFET Q9 which is in a differential configuration with the MO3FET QIO. And the above MO3FETQ9. The common source of QIO is an n-channel MOS as a constant current source.
FETQ13 is provided. In addition, the above MO3FE
TQ9. A current mirror type p-channel MO3FET Q11, Ql2 is provided as an active load on each drain of the QIO. This increases the gain.

The output of the differential amplifier circuit is a p-channel MO3FET.
Q14 and an n-channel MO3FET QI5, which further amplifies the CM
It is converted into an OS level signal CMO5OUT.

This level-converted signal CMO3OUT is
If the L level signal ECL IN is an address signal,
If it is a control signal, it is transmitted to the address buffer ADH, and to the internal control signal generation circuit COM-GS.

Reference voltage V re for determining the above external ECL signal
f is composed of the following circuit.

In this embodiment, it is assumed that the circuit is used for a so-called IOK type external ECL circuit, and therefore the reference voltage Vref is made to have a predetermined dependence on the power supply voltage. Therefore, voltage dividing resistors R1 and R2 that divide the power supply voltage
The resistance ratio is set to R1/R1+R2=0.148.

The following constant voltage circuit is operated by the power supply voltage having the above-mentioned power supply voltage dependence.

A p-channel MO3FET Q1 and an n-channel MOSFET Q2 arranged in series form a bias current. n made into a current mirror configuration with the above MO3FETQ2
The drain of the channel MOSFET Q4 is connected to a p-channel MO3FET Q3. Q5 is provided.

In addition, along with the above MO3FETQ4, an n-channel MO
3FETQ8 is also configured as a current mirror with respect to MO3FETQ2.

Then, there is an n-channel MO3FETQ6 whose gate is made of N+ type polysilicon, and an n-channel MO3FETQ whose gate is made of P-type polysilicon.
7 sources are shared and connected in a differential configuration. These MO3FETQ6, Q7 have their gates,
The drains are connected to form a diode.

The drain of the MO3FETQ6 is connected to the MO3FE
Bias current from TQ5 is supplied.

Moreover, the above MO3FETQ6. A bias current formed by MO3FETQB is made to flow through the common source of Q7. The drain of the MO3FET Q7 is connected to the power supply voltage terminal formed by the voltage dividing resistors R1 and R2.

Therefore, from the common terminal of MO3FETQ6, a voltage Vr corresponding to the difference in threshold voltage between MO3FETQ7 and MO3FETQ6 is obtained with the power supply voltage as a reference.

In order to make this voltage Vr itself a constant voltage that has no dependence on the power supply voltage, the MO3FETQ6. Make the current flowing through Q7 equal. In other words, the drain current of MO3FETQ5 is 1/2 of the drain current of MO3FET'Q8.
Set to . This current ratio is determined by the MO3FETQ4. Q
8 and/or MO3FETQ3. It can be set by appropriately selecting the size ratio of Q5.

As mentioned above, MO3FETQ6. When the currents of Q7 are made equal, the voltage Vr, which is the threshold voltage, becomes a constant voltage of about 1.2 volts, which corresponds to the silicon band gap.

Therefore, when the power supply voltage Vee is -5.2 volts,
Since the power supply voltage of the voltage-divided constant voltage circuit is -0.77 volts, the voltage Vr is -1.97, which is lower than the reference voltage V ref of -1.29 volts required for the ECL level. turn into.

Therefore, resistors R3 and R4 are provided to divide the constant voltage Vr. These resistors R3 and R4 divide the constant voltage Vr' to form -0.52 volts. This makes it possible to form a reference voltage Vref of -1.29 volts. Also, assuming that it is used for a so-called 100K type external ECL circuit,
Since there is no dependence on power supply voltage, resistor R1 for voltage division
, R2 can be removed. In this case, Vcc' is connected to Vcc. In addition, the voltage dividing resistors R1 and R2 are
Since it is provided to give power supply voltage dependence to the reference voltage V ref, it does not necessarily need to be formed of a resistor, and may be a combination of an MO3 resistor and a resistive element, for example.

FIG. 6 shows a circuit diagram of an embodiment of an output level conversion circuit that receives a CMOS level signal and converts it into an ECL level signal.

In this embodiment, the output circuit of the data output buffer yDOB in FIG. 4A is replaced with the following output level conversion circuit.

p-channel MO3FETQI 6 and n-channel MO
3FETQI 7 constitutes a CMOS inverter,
Receives read output signal. A resistor R5 and a diode D are provided in parallel between the output of this inverter and the power supply voltage terminal Vcc. The collector thereof is connected to the power supply voltage terminal Vcc, and the base of the CMO terminal is connected to the power supply voltage terminal Vcc.
A bipolar transistor Q20 to which an output signal from the S inverter is applied is provided.

The emitter of this transistor Q20 is connected to the data output terminal Dout, and a load resistor R7 is provided between the emitter and the ECL circuit power supply voltage Vtt (-2 volts) outside the IC.

In this circuit, when the input signal is at low level, p-channel MO3FET QI 6 turns on and supplies approximately Vcc level to the base of transistor Q20, so its output level should be ECL high level of approximately -0.9 volts. I can do it.

In this embodiment, since the resistor R5 is provided, the base current to the transistor Q20 can also be supplied from the resistor R5, so that the chip size of the p-channel MO3FET QI6 can be reduced by that amount.

Further, when the input signal is at a high level, the n-channel MO3FET QI 7 is turned on, turning on the diode D. Therefore, since the forward voltage of this diode D is applied to the base potential of the transistor Q20, its output level can be set to the ECL low level of about -1.7 volts.

FIG. 7 shows a circuit diagram of another embodiment of the output level conversion circuit.

In this embodiment, in order to prevent a relatively large current from flowing through the n-channel MO3FET Q17 during low level output in the circuit shown in FIG.
A current limiting resistor R6 is provided in series with TQI 7.

Further, when changing the output signal from high level to low level, an n-channel MO3FET Q1B is provided in parallel with the resistor R6 in order to prevent the resistor R6 from delaying the fall of the output signal. The gate is provided with a delay circuit DL that delays the input signal of the inverter, and a delay circuit DL that inverts the delayed signal.
A signal passed through MOS inverter IV is applied.

When the input signal changes from low level to high level and its ECL output changes from low level to high level, the MO3FETQI changes by the delay time in the delay circuit.
8 keeps turning on.

Therefore, when MO3FETQI 7 turns on, both MO3FETQI 7. Current flows through Ql8, which speeds up the fall of the ECL output signal, and in a steady state, MOS FETQlB is turned off and current is limited by resistor R6.

In this embodiment, the current limiting resistor R6 is the CM
It may be provided between the n-channel MO3FET Q17 of the OS inverter and its output node, or only the current limiting resistor R6 may be provided. Furthermore, the resistor R5 may be omitted.

In this example, the input level conversion circuit is composed of only MOSFETs, and the collector of the bipolar transistor used in the output level conversion circuit is connected to the ground potential of the circuit, in other words, to the substrate of the CMO3 integrated circuit. Since the N-type semiconductor substrate is used as the collector,
The P-type well region can be used as a base, and the N-type region formed in the P-type well region can be configured as an emitter.

That is, the above bipolar transistor is a normal n
It can be formed in the same way as a channel MO3FET. Therefore, in this embodiment, a CMO3 integrated circuit device compatible with the above ECL circuit can be created using only the known CMO8 integrated circuit manufacturing process.

In addition, the reference voltage V ref of the input level conversion circuit can be set with an extremely stable constant voltage using a silicon band gap and a resistance ratio, so it can be set with high accuracy without being affected by manufacturing errors, etc. .

Although the number of elements is larger than that of the circuit shown in Figure 2, it is composed of MOSFETs that do not require element isolation like bipolar transistors, and only one is provided in the CMOS integrated circuit. Therefore, when viewed from the perspective of the entire CMO3 integrated circuit, there is no need to increase the chip size.

In addition, the input level conversion circuit is a high gain differential MOS F
It is composed of an ET circuit and an inverter, and the number of elements can be reduced to seven. This input level conversion circuit is
Since they are provided for each input terminal, the chip size can be reduced when viewed from the overall CMO3 integrated circuit, and power consumption can also be reduced.

The invention is not limited to the above embodiments.

In the CMOS static type RAM mentioned above, the memory cells include a p-channel MO3FET and an n-channel MO3FET.
A flip-flop circuit configured with an O5FET may also be used. Further, the configuration of the memory array and the configuration of the peripheral circuit can take various embodiments.

Furthermore, the present invention can be widely applied to not only the static RAM as in the embodiment described above but also to information processing devices configured with CMOS gate arrays and other devices using CMO3 circuits.

[Brief explanation of the drawing]

1st ¥! J is a circuit diagram of a reference voltage generation circuit showing an example of the prior art, FIG. 2 is a circuit diagram of an input level converting circuit showing an example of the prior art, and FIG. 3 is an output level converting circuit showing an example of the prior art. A circuit diagram of the circuit, FIG. 4A is a block diagram showing an embodiment of a CMOS static type RAM to which the present invention is applied, and FIG. 4B is a circuit diagram of the circuit.
FIG. 5 is a circuit diagram of an input level conversion circuit and its reference voltage generation circuit showing one embodiment of the present invention, and FIG. 6 is a tie-hanging diagram for explaining its operation. Circuit Diagram of Output Level Conversion Circuit FIG. 7 is a circuit diagram of an output level conversion circuit showing another embodiment of the present invention. M-ARY1 to M-ARY4...Memory array (memory matrix), M-CEL...Memory cell, O3...
Memory matrix selection circuit, C-DCR1 to C-DC
R4...Column decoder. SAI~SA4...Sense amplifier, COM-GE...Internal control signal generation circuit, R-DCR...Row decoder, A
DH...address buffer, C-5W1 to C-3W
4. Column switch. 4B #/QH〈Incl./lHinoTf C″7″C11-n No. 5 Figure 6 Figure 7 Continuation of Figure 1 Page 0 Inventor: Osamu Takahashi 0 Inventor: Masa Yamamoto 0 Inventor: Katsuro Sasaki 0 Inventor: Yokanji, 1450 Kamisui Honmachi, Kodaira City, Hitachi, Ltd., Musashi Factory

Claims (1)

[Claims] 1. MO of diode type N0 type polysilicon gate
A constant voltage generation circuit which forms a constant voltage corresponding to the silicon bandgap by differentially forming an SFET and a P-type polysilicon gate MOSFET, and an input signal level by dividing the output voltage of the constant voltage generation circuit. a reference voltage generation circuit consisting of a voltage dividing resistor that forms a reference voltage Vref for determining the CMO3 signal level; and a differential MO3FET circuit that receives the reference voltage Vref and an input signal input from an external terminal. A CMO3 integrated circuit device comprising a level conversion circuit for converting levels. 2. The above reference voltage V ref is ECL (or CML
) level of the input signal level.
3 integrated circuits. 3. Claim 2, characterized in that the reference voltage generation circuit has an input circuit for making the reference voltage Vref have an appropriate dependence on the power supply voltage.
The CMO3 integrated circuit described in section. 4. The CMO3 integrated circuit according to claim 3, wherein the input circuit comprises a voltage dividing resistor. 5. The CMO3 integrated circuit device according to claim 1, wherein the signal passed through the level conversion circuit is transmitted to a built-in static type RAM. 6. The signal passed through the level conversion circuit is connected to the built-in C
2. The CMO3 integrated circuit device according to claim 1, wherein the CMO3 integrated circuit device is transmitted to an information processing circuit using a MOS gate array.