JPH0746510B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device, and a technique effective when applied to a static RAM (random access memory) composed of, for example, MOSFET (insulated gate type field effect transistor). It is about.

[Background technology]

In a MOS static RAM, a plurality of memory cells are usually arranged in a matrix. The select terminals of a plurality of memory cells arranged in the same row are commonly connected to one word line corresponding to the row, and the data input / output terminals of a plurality of memory cells arranged in the same column are the data corresponding to that column. Commonly connected to the line. The plurality of data lines are connected to the common data line via the column switch circuit.

An input terminal of the sense amplifier and an output terminal of the write circuit are coupled to the common data line.

Therefore, the data in one memory cell selected by the word line and the column switch circuit is supplied to the sense amplifier.

By the way, a data line load MOSFET that is always turned on is provided between the data line and the power supply terminal, and the data line load MOSFET sets the potential of the data line to a desired level before starting data reading. You can

When such a data line load MOSFET is provided, when a predetermined word line is selected, the selection terminals of all the memory cells connected to the word line are turned on, and the memory cells connected to those selection terminals are turned on. A through current flows through the static flip-flop circuit via the data line selection element. This shoot-through current occurs in all the memory cells connected to the selected one word line. For this reason, although one memory cell is selected, a large amount of memory cell consumes an unnecessary current, resulting in an increase in power consumption.

In particular, in order to achieve high-speed reading of data, it is effective to increase the transconductance of the data line load MOSFET to reduce the potential difference applied between the data lines. It will be even more.

In addition, MOS static RAM with data line load MOSFET
As an example of the document described about JP-A-57-1279
There is 89 publication.

[Object of the Invention]

An object of the present invention is to provide a semiconductor memory device capable of reducing a through current flowing from a data line load element via a memory cell and thus achieving a reduction in power consumption.

The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a high-resistance first data line negative MOSFET and a low-resistance second data line load MOSFET, which are switch-controlled in a complementary manner based on the data line selection signal, are provided in each data line, and the data line selection signal is selected according to the selection level. The second data line load MOSFET is turned on, and the first data line negative MO
By turning on the SFET, the first data line load MO
Through-current flowing from the SFET through the memory cell is reduced to reduce power consumption.

〔Example〕

FIG. 1 is a circuit diagram showing a static RAM which is an embodiment of the present invention.

The static RAM shown in the figure is formed on one semiconductor substrate by a known semiconductor integrated circuit technology. Terminals AX1 to A
Xk, AY1 to AYk, Dout, Din and Vcc are external terminals thereof. This static RAM is operated by supplying a power supply voltage from an external power supply device (not shown) provided between the power supply terminal Vcc and the ground terminal.

In the figure, 1 is a memory array, which is shown as a representative static memory cells 1a to 1d, word lines W1 to Wn,
It is composed of data lines D1, ▲ ▼, Dn, ▲ ▼.

The static memory cells 1a to 1d have the same configuration as each other and are not particularly limited, but as shown in detail by taking 1a as a representative, the differential MOSFETs Q1 and Q2 and the load resistances R1 and
It is composed of a static flip-flop circuit composed of R2 and N-channel type transfer MOSFETs Q3 and Q4 respectively provided between the input / output terminal of this static flip-flop circuit and the pair of data lines D1 and ▲ ▼. To be done.

The static memory cell holds data by supplying the power supply voltage applied to the power supply terminal Vcc to the connection point of the load resistors R1 and R2.

The static memory cells 1a to 1d are arranged in a matrix as shown. Of the static memory cells 1a to 1d arranged in a matrix, the gates of the transfer MOSFETs Q3 and Q4 that constitute the selection terminals of the static memory cells 1a, 1c and 1b, 1d arranged in the same row respectively correspond to each other. Static memory cells 1a, 1b and 1c, which are connected to the word lines W1 and Wn, while arranged in the same column,
The pair of input / output terminals 1d are connected to the corresponding pair of data lines D1, ▲ ▼ and Dn, ▲ ▼. And the data lines D1, ▲ ▼ and Dn, corresponding to each of these columns,
▲ ▼ indicates N channel type data line selection MO
Common data line CD via SFET Q5, Q6 and Q7, Q8, ▲ ▼
Connected to.

The word lines W1 to Wn are connected to the output terminals of the X address decoder circuit 2 and selected by the word line selection signal output from the X address decoder circuit 2. In this embodiment, the high level of the word line selection signal is the selection level of the word line. The X address decoder circuit 2 is supplied with a chip select signal ▲ ▼ as an external signal. Chip select signal ▲ ▼
Is set to the chip non-selection level, the X address decoder circuit 2 brings all the word lines W1 and Wn into the non-selection state.

The gates of the pair of data line selection MOSFETs Q5, Q6 and Q7, Q8 provided corresponding to each column of the memory matrix are respectively connected to the output terminals of the Y address decoder circuit 3 and output from this Y address decoder circuit 3. It is selected by the data line selection signal. In the present embodiment, the high level of the data line selection signal is the selection level of the data line.

The X address decoder circuit 2 has an address input terminal
The address signals supplied to AX1 to AXk are input via the address buffer circuits BX1 to BXk.

Similarly, the address signals supplied to the address input terminals AY1 to AYk are input to the Y address decoder circuit 3 via the address buffer circuits BY1 to BYk.

The pair of common data lines CD, ▲ ▼ are connected to the input terminal of the sense amplifier 4 on the one hand and to the output terminal of the write circuit 5 on the other hand. The output signal of the sense amplifier 4 is supplied to the data output terminal Dout via the output buffer circuit 6, and the signal input from the data input terminal Din is supplied to the write circuit 5 via the input buffer circuit 7.

Each of the data lines D1, ▲ ▼, Dn, ▲ ▼ has a high voltage which is complementarily switch-controlled based on the data line selection signal in order to set the potential of the data line to the reference potential in advance before starting the data reading. A P-channel first data line load MOSFET Q9 exhibiting on-resistance and an N-channel second data line load MOSFET Q10 exhibiting low on-resistance are provided.

The drain of the first data line load MOSFET Q9 is coupled to the data line, and the source thereof is coupled to the power supply terminal Vcc through the N-channel type level shift MOSFET Q11 having the gate and drain coupled. The MOSFET Q9 is turned on when the data line selection signal is set to the non-selection level (low level), that is, when the data line connected to it is not selected, and the bias is applied to the unselected data line. Apply voltage or reference potential. This bias voltage is applied to the data line connected to the memory cell in which the data is not read, and simply keeps the level of the data line at a predetermined level in preparation for the next data read. It is enough if possible. Therefore, the first data line load MOSFET Q9 has a relatively small transconductance, that is, a high resistance, and its size is also small.

Therefore, among the memory cells connected to the word line selected based on the word line selection signal, those connected to the data line not selected based on the data line selection signal, that is, irrelevant to the data reading. Regarding the memory cell, the transfer MOSFET Q3 (Q
The through current flowing from 4) via the differential MOSFET Q1 (Q2) is reduced.

In addition, when the chip is not selected in which all the data lines are not selected, all the first data line load MOSFETs Q9 are turned on and the bias voltage is supplied to each data line. At this time, all the word lines are also brought into the non-selected state by the chip select signal ▲ ▼ at the non-selected level, and all the transfer MOSFETs Q3 and Q4 are turned off. Therefore, even if the chip non-selection period is long, there is no possibility that the stored information in the memory cell is destroyed by the bias voltage supplied to each data line.

Here, the level shift MOSFET Q11 is
The coupling between the drains causes a voltage drop across the source and drain that is approximately equal to the threshold voltage. Therefore, the bias voltage applied to the data line via the first data line load MOSFET Q9 is
Level shift MOSFE for the power supply voltage supplied to Vcc
The voltage is leveled down by TQ11. Therefore, when a predetermined data line is selected based on the data line selection signal, the data line selection MO connected to that data line is selected.
High-speed ON operation of SFETQ5, Q6 (Q7, Q8) is guaranteed, and high-speed reading of data is achieved.

The second data line load MOSFET Q10 has a source coupled to the data line and a drain coupled to the power supply terminal Vcc. The MOSFET Q10 is turned on when the data line selection signal is set to the selection level (high level), that is, when the data line connected to it is selected. A bias voltage is applied to.

Here, the second data line load MOSFET Q10 has a transconductance larger than that of the first data line load MOSFET Q9, that is, is set to have a low resistance. This transconductance is almost the same as that of the data line load MOSFET conventionally arranged in the always-on state between each data line and the power supply terminal, and the potential of the data line to be brought to the low level at the time of reading data is relatively high. It is set to a value that makes it a level. Therefore, when a bias voltage is applied to a predetermined data line by the load MOSFET Q10, the level change speed of the data line is increased, and data can be read at high speed.

In particular, the load MOSFET Q10 is turned on almost in synchronization with the on operation of the MOSFETs Q5, Q6 (Q7, Q8) for selecting the data line. Therefore, the level of the data line to which the bias voltage is applied becomes relatively low as described above, and the transition time until the complementary level of the read data is determined can be shortened.

In the figure, Q12 is a P-channel type equalizer MOSFET that is switch-controlled by a data line selection signal, and its drain / source is a pair of data lines D1, ▲
It is connected to ▼ and Dn, ▲ ▼ and turned on at the non-selection level (low level) of the data line selection signal. This MO
When the SFETQ12 is turned on, the levels between the pair of data lines, which are set to complementary levels by reading the data, are balanced. For example, when memory cells that store different data and are connected to the same data line are sequentially read by switching the address, the potential difference between the data lines caused by the reading of the first memory cell is read out from the next memory cell. Need to flip. That is, the high level data line is lowered to the low level in the memory cell, and the low level data line is raised to the high level by the first data line load MOSFET Q9. The equalizer MOSFET Q12 is
By forcibly balancing the levels between the pair of data lines which are set to the complementary level, the time delay required for inverting the data lines is reduced. Particularly in the case of this embodiment, the first data line load MOSFET Q9 is connected to the data line in the non-selected state as described above.
Bias voltage is supplied by the load MOSFET
Since Q9 is set to a high resistance in order to reduce power consumption, it is significant to provide the equalizer MOSFET Q12 in the sense of compensating for the time delay required for inverting the data line.

According to this embodiment, the low resistance second data line load MOSFET Q1
For 0, only those connected to the data line in the selected one memory cell are turned on, and in the other data lines, the high resistance first data line load MOSFET Q9 is turned on. As a result, the bias voltage required for high-speed reading of data is promptly supplied only to the data line related to the reading of data, and the bias voltage is supplied to the other data lines in a slower state than that of the data line. Therefore, among the memory cells connected to the selected one word line, those connected to the data line that is not selected based on the data line selection signal, that is, the majority of memory cells that are not related to the reading of data, Transfer MOSFET Q3 (Q4) to differential MOSFET Q1 (Q2) of that memory cell
It is possible to reduce the through current flowing through the.

As described above, in the majority of memory cells in the same row other than one memory cell selected when reading data, useless through current flowing therethrough is relaxed, and power consumption can be significantly reduced. Moreover, since the degree of reduction in the power consumption is extremely large, the memory cells can be freely laid out without being restricted by the divided configuration of the memory cell array for the same purpose.

〔The invention's effect〕

As is clear from the above description, according to the invention disclosed in the present application, the following effects can be obtained.

(1) A data line load element that is turned on at the selection level of the data line selection signal is provided in each data line, and this data line load element is turned on according to the selection level of the data line selection signal. Through current flowing through the memory cell on the side can be reduced, and power consumption can be significantly reduced.

(2) Due to the above effects, the memory cells can be freely laid out without being restricted by the divided configuration of the memory cell array for reducing the power consumption.

(3) In particular, when the data line load element is composed of the high resistance first data line load element and the low resistance second data line load element which are switch-controlled complementarily based on the data line selection signal, Besides, high-speed reading of data can be achieved.

Although the invention made by the inventor has been specifically described based on the embodiments, various modifications can be made without departing from the scope of the invention.

In the above embodiment, the case where the data line load element is composed of the high resistance first data line load element and the low resistance second data line load element which are complementarily switch-controlled based on the data line selection signal has been described. However, when the bias voltage at the time of non-selection is replaced by the discharge voltage from the memory cell or the like, the first data line load element can be omitted. The high-resistance first data line load element is not a switchable element such as MOSFET, but is, for example, an element made of high-resistance polysilicon formed on a semiconductor substrate via an insulating film, or a polysilicon high-resistance element. And a PN junction element for forward operation made of polysilicon connected in series to it may be configured as a series circuit.

Furthermore, the equalizer MOSFET described in the above embodiment may be switch-controlled by an internal control signal generated by detecting a change in the address signal, or may be omitted.

[Field of application]

In the above description, the MOS static RAM which is the technical field behind the invention mainly made by the present inventor
However, the present invention is not limited to this and can be widely used in various semiconductor memory devices.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a static RAM which is a first embodiment of the present invention. W1 to Wn …… Word line, D1, ▲ ▼ …… Data line, Dn, ▲
▼ …… Data line, CD, ▲ ▼ …… Common data line, Q
5 to Q8 …… Data line selection element, Q9 …… Data line load element (high resistance first data line load MOSFET), Q10 …… Data line load element (low resistance second data line load MOSFET), Q11 ……
Level shift element (level shift MOSFET), Q12 ... Equalizer MOSFET, 1 ... Memory array, 1a-1d ... Static memory cell.

(72) Inventor Hiromichi Yamauchi 1448, Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra ELS Engineering Co., Ltd. (72) Masanori Odaka, 2326 Imai, Ome, Tokyo Hitachi, Ltd. In the device development center (56) Reference JP-A-56-118369 (JP, A)

Claims (2)

[Claims] 1. A memory array composed of a plurality of static memory cells arranged in a matrix, a plurality of word lines and a plurality of data lines, and a plurality of data arranged between each data line and a power supply terminal. Line load element, common data line,
A semiconductor memory device comprising a plurality of data line selection MOSFETs provided between each data line and the common data line, each selected by a data line selection signal, wherein each data line load element comprises: A relatively high-resistance first data line load MOSFET that has a conductivity type different from that of the data line selection MOSFET and is turned on when the corresponding data line is not selected by the data line selection signal, and the same conductivity type as the data line selection MOSFET. A semiconductor memory device comprising a second data line load MOSFET having a relatively low resistance which is turned on when a corresponding data line is selected by the data line selection signal. 2. The semiconductor memory device according to claim 1, wherein the first data load MOSFET is connected to a power supply terminal via a level shift element.