JP2610894B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device, and is used, for example, for a bipolar CMOS random access memory (hereinafter referred to as a bipolar CMOS RAM). And effective technology.

[Conventional technology]

A so-called ECL interface bipolar CMOS RAM compatible with ECL (Emitter Coupled Logic) circuits
There is.

The bipolar CMOS type RAM has a plurality of input buffers provided corresponding to input signals such as address signals for each bit. Each input buffer includes a bipolar current switch circuit, two sets of CMOS current mirror circuits, and a combined bipolar / CMOS drive circuit.

Such a bipolar CMOS type RAM is described, for example, in "Nikkei Electronics", March 10, 1986, pages 199 to 217, published by Nikkei McGraw-Hill.

[Problems to be solved by the invention]

In the bipolar CMOS type RAM described above,
An input signal such as an X address signal AX0 input from the outside at an ECL level passes through a corresponding external terminal and an input level shift circuit, as shown in FIG. 4, and the bipolar current switch of the X address buffer XADB. It is supplied to the circuit CS1. The amplitude of the input signal is, for example, about 0.8V. The current switch circuit CS1 sets the reference potential Vbb supplied to the base of the transistor T3 as a logic threshold level, and performs the level determination operation of the small-amplitude input signal as described above. The output signal of the current switch circuit CS1 has a signal amplitude slightly larger than the input signal.

The output signal of the current switch circuit CS1 is supplied to the current mirror circuits CM1 and CM2 via the emitter follower circuit. The current mirror circuits CM1 and CM2 are composed of CMOS, and the complementary output signal of small amplitude supplied from the current switch circuit CS1 is used as a CMOS level internal signal which is fully swinged between the circuit ground potential and the power supply voltage Vee. Convert to The output signals of the CMOS current mirror circuits CM1 and CM2 are output from the address distribution circuit AD composed of a bipolar CMOS composite drive circuit.
3 and AD4, and the non-inverted internal address signal ax
These are transmitted to the X address decoder XDCR as 0 and the inverted internal address signal ▼ respectively.

However, the input buffer of the bipolar CMOS type RAM has the following problems.
It has been clarified by the present inventors. That is, the above-mentioned input buffer is used for the ECL supplied through each external terminal.
It is assumed that a level input signal is changed with two stable points, for example, a high level such as -0.9 V and a low level such as 1.7 V. Therefore, the reference potential Vbb supplied to the current switch circuit CS1 is, for example, the base-emitter circuit V _BE of the transistor T1 of the input level shift circuit.
Is set to 0.8V, the intermediate level of the input signal at the emitter of the transistor T1, that is, -2.1V. However, for some reason, when the input signal becomes an intermediate level between the high level and the low level of the ECL level and the emitter potential of the transistor T1 becomes the same level as the reference potential Vbb, the differential transistors T2 and T3 of the current switch circuit CS1 Both collector voltages have the same intermediate level. Therefore, the output signals of the CMOS current mirror circuits CM1 and CM2 are both at the intermediate level, and as a result, the transistors T10 and T11 and T12 and T12 and T12 of the address distribution circuits AD3 and AD4.
13 are both on weekly. As a result, a through current flows through the transistors T10 and T11 or T12 and T13, and the CMOS inverter circuit provided on the chip enters a latch-up state.

That is, as shown in the cross-sectional view of FIG. 3, for example, when a through current flows through the transistors T10 and T11, a voltage drop occurs due to the collector resistance of the transistor T11, and the collector voltage becomes lower than the base voltage, so that the transistor T11 Becomes saturated. Therefore, transistor T11
And the N-type buried layer NBL as the base, the base of the transistor T11 as the emitter, and the P-type semiconductor substrate PSU
The parasitic transistor Trs having B as a collector is turned on, and a relatively large substrate current Is flows through the P-type semiconductor substrate PSUB.

The power supply voltage Vee is supplied to the P-type semiconductor substrate PSUB via a contact (not shown), and the power supply voltage Vee 'is supplied to the P-type well region Pwell of the MOSFET Q39 by being coupled to the P-type semiconductor substrate PSUB. . When the input signal is at the intermediate level and the substrate current Is flows through the P-type semiconductor substrate PSUB, the substrate potential, that is, the power supply voltage Vee 'increases. Therefore, the P-type semiconductor substrate PSUB, ie, the MOSFET Q3
The parasitic thyristor Tsn having the P-type well region Pwell of 9 as a base, the source region S of the MOSFET Q39 as an emitter, and the N-type well region Nwell of the MOSFET Q15 as a collector is turned on. Therefore, the parasitic thyristor Tsp having the gate of the N-type well region Nwell of the MOSFET Q15, the source region S of the MOSFET Q15 as an emitter, and the P-type semiconductor substrate PSUB as a collector is turned on. Thereby, the parasitic thyristors Tsn and Tsp, that is, the P-channel MOSFET Q15
And CMOS inverter circuit consisting of N-channel MOSFET Q39 is latched up, and bipolar CMOS type RAM
Is destroyed.

It is an object of the present invention to provide a semiconductor memory device such as a bipolar CMOS type RAM which prevents latch-up of an input buffer.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
The power supply voltage terminal of the CMOS inverter circuit provided between the base of one transistor of the bipolar CMOS composite drive circuit of the input buffer and the output terminal of the corresponding one of the CMOS current mirror circuits is replaced with the corresponding CMOS current mirror circuit of the other one. Is connected to the output terminal.

[Action]

According to the above-mentioned means, when the level of the input signal becomes the intermediate level and the output levels of the CMOS current mirror circuits both become the intermediate level, the P-channel MOSFETs of the respective CMOS inverter circuits cannot be turned on and the CMOS inverter circuits are not turned on. Since the output level is fixed to the low level, it is possible to prevent a through current through the output transistor connected to the totem pole of the bipolar / CMOS composite drive circuit, and to prevent latch-up of the CMOS inverter circuit.

〔Example〕

FIG. 2 shows a bipolar CMOS to which the present invention is applied.
A circuit block diagram of one embodiment of the type RAM is shown. The circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate such as single-crystal silicon, though not particularly limited, by a known bipolar CMOS integrated circuit manufacturing technique. In the following figures, MOSFETs with an arrow added to the channel (back gate) portion are of the P-channel type and are distinguished from N-channel MOSFETs without the arrow. The illustrated bipolar transistors are all NPN transistors.

In FIG. 2, the memory array M-ARY includes (m + 1) word lines W0 to Wm arranged in the horizontal direction in FIG. 2 and n + 1 pairs of complementary data lines D0.multidot.
▼ to Dn · ▲ and (m + 1) × (n + 1) static memory cells MC arranged at the intersections of these word lines and complementary data lines.

Each memory cell MC includes N-channel type drive MOSFETs Q35 and Q36, as exemplarily shown in FIG. The gates and drains of these MOSFETs Q35 and Q36 are cross-coupled to each other. Between the drains of the MOSFETs Q35 and Q36 and the ground potential (first power supply voltage) of the circuit, although not particularly limited, load resistors R5 and R6 having a high resistance value made of a polysilicon (polycrystalline silicon) layer are provided, respectively. Can be MO
The sources of the SFETs Q35 and Q36 are connected to the power supply voltage Vee (second
Power supply voltage). The power supply voltage Vee is not particularly limited, but is, for example, a negative power supply voltage of −5.2 V. The drive MOSFETs Q35 and Q36, together with the load resistances R5 and R6, constitute a flip-flop serving as a storage element of the bipolar CMOS RAM.

MOSFET Q35 used as input / output node of flip-flop
The drain of Q36 and N-channel transmission gate MOS
Via FETs Q37 and Q38, they are coupled to the corresponding non-inverted signal line 0 and inverted signal line ▼ of the complementary data line, respectively. The gates of transmission gate MOSFETs Q37 and Q38 are commonly coupled to corresponding word line W0.

All other memory cells MC have the same circuit configuration as the above-mentioned memory cell MC, and are arranged in a grid at the intersections of the corresponding word lines and complementary data lines, so that the memory array M
Construct -ARY.

Word lines W0 to Wm constituting the memory array M-ARY are:
It is coupled to an X address decoder XDCR, one of which is alternatively set to a high level selection state.

The X address decoder XDCR has an X address buffer XA
From DB, complementary internal address signals a x0 to a xi (here, for example, the non-inverted internal address signal ax0 and the inverted internal address signal ▼ are collectively represented as a complementary internal address signal a x0; the same applies hereinafter), A timing signal φce is supplied from the chip control circuit TC. X address decoder
The XDCR is selectively activated when the timing signal φce is set to a high level. In this operating state,
The X address decoder XDCR outputs the complementary internal address signal
decodes a x0~ a xi, a selected state of one word line to a high level designated by the X address signal AX0～AXi.

As will be described later, the X address buffer XADB includes i + 1 input level shift circuits and bipolar current switch circuits provided corresponding to the external terminals AX0 to AXi, and 2 × (i + 1) provided two by two corresponding thereto. ) CMOS
It includes a current mirror circuit and an address distribution circuit.

X address buffer XADB the levels of the X address signal AX0～AXi supplied via the external terminals AX0～AXi, determined according to the reference potential, the complementary internal address signals a X0～
Form a xi.

The specific circuit configuration and operation of the X address buffer XADB will be described later in detail.

On the other hand, the complementary data lines D constituting the memory array M-ARY
On the other hand, 0 • ▲ ▼ to Dn • ▲ ▼ are connected via the corresponding P-channel MOSFETs Q7, Q8 to Q9, Q10,
It is coupled to the ground potential of the circuit. These MOSFETs Q7 and Q8
Q9 and Q10 are always turned on when their gates are coupled to the power supply voltage Vee of the circuit, and the complementary data lines D0 and ▲
Functions as a load MOSFET for ▼ ~ Dn ・ ▲ ▼.

Complementary data lines D0 and ▲ constituting the memory array M-ARY
▼ to Dn ・ ▲ ▼ indicate switch MOSFETs Q15, Q33 and Q16
It is coupled to Q34 to Q17.Q35 and Q18.Q36, respectively. These switch MOSFETs Q15 / Q33 and Q16 / Q34 to Q17 / Q35 and Q18 / Q36
When Y0 to Yn are alternatively set to the high level, they are simultaneously turned on, and the corresponding complementary data lines D0 and ▲
〜 To Dn ・ and the complementary common data lines CD ・ are selectively connected.

The Y address decoder YDCR has a Y address buffer YA
Complementary internal address signals a y0 to a yj are supplied from DB, and the above-mentioned timing signal φce is supplied from the chip control circuit TC. The Y address decoder YDCR receives the timing signal φce
Is set to a high level to be selectively activated. In this operation state, the Y address decoder YDCR
Decodes the complementary internal address signals a y0 to a yj to form the data line selection signals Y0 to Yn.

Y address buffer YADB receives Y address signal AY0～AYj supplied via the external terminals AY0～AYj, forming the complementary internal address signals a y0~ a yj. Although not particularly limited, the Y address buffer YADB has the same configuration as the X address buffer XADB.

The complementary common data lines CD • ▲ ▼ are coupled to the input terminal of the sense amplifier SA, and further coupled to the output terminal of the write amplifier WA. The output terminal of the sense amplifier SA is coupled to the input terminal of the data output buffer DOB, and the output terminal of the data output buffer DOB is further coupled to the data output terminal DO. On the other hand, the input terminal of the write amplifier WA is coupled to the output terminal of the data input buffer DIB,
Are further coupled to a data input terminal DI. The timing signal φsa and φoe are supplied from the chip control circuit TC to the sense amplifier SA and the data output buffer DOB, respectively. The timing signal φwe is supplied to the write amplifier WA.

The sense amplifier SA is selectively activated by the timing signal φsa being set to a high level. In this operation state, the sense amplifier SA amplifies the small-amplitude read signal transmitted from the selected memory cell MC via the complementary common data line CD ・ to make the logical-level complementary read signal. These complementary read signals are
The data is transmitted to the data output buffer DOB.

The data output buffer DOB is selectively activated in the read operation mode of the bipolar CMOS type RAM by setting the timing signal φoe to a high level. In this operating state, the data output buffer DOB converts the complementary read signal of the logic level output from the sense amplifier SA to the ECL level, and sends it to the external device from the data output terminal DO via the open-emitter output transistor. I do.

On the other hand, the data input buffer DIB is a bipolar CMOS
In the write operation mode of the type RAM, the data input terminal D
The ECL level write data supplied from outside via I is used as a MOS level complementary write signal, and the write amplifier W
Communicate to A.

The write amplifier WA is selectively activated by the timing signal φwe being set to the high level. In this operation state, the write amplifier WA operates in the data input buffer DI
In accordance with the complementary write signal supplied from B, a write current is supplied to the complementary common data lines CD.

The chip control circuit TC forms the above-mentioned various timing signals based on a chip select signal ▼ and a write enable signal ▼ which are externally supplied as control signals, and supplies the signals to each circuit.

FIG. 1 is a circuit diagram showing one embodiment of the X-address buffer XADB of the bipolar CMOS type RAM shown in FIG. FIG. 2 exemplarily shows a set of input buffers corresponding to the X address signal AX0. X address buffer
XADB is provided with similar i sets of input buffers corresponding to the other X address signals AX1 to AXi. Although not particularly limited, the Y address buffer YADB or the like is provided with a similar input buffer corresponding to each input terminal.

In FIG. 1, an X address signal AX0 supplied from an external terminal AX0 through an input protection circuit (not shown) is supplied to a bipolar current switch circuit via an input level shift circuit including a bipolar transistor T1 and a constant current source Is1.
It is supplied to the base of transistor T2 of CS1.

The bipolar current switch circuit CS1 includes differential transistors T2 and T3, and a constant current source Is2 provided between a commonly connected emitter of the differential transistors and a power supply voltage Vee of the circuit. A predetermined reference potential Vbb is supplied to the base of the transistor T3. The load resistors R1 and R2 are connected between the collectors of the transistors T2 and T3 and the ground potential of the circuit.
Are respectively provided. The collector voltages of the transistors T2 and T3 are supplied to the bases of the transistors T4 and T5, respectively.

The collectors of the transistors T4 and T5 are coupled to the ground potential of the circuit, and load resistors R3 and R4 are provided between the respective emitters and the power supply voltage Vee of the circuit. These transistors T4 and T5, together with the corresponding load resistors R3 and R4, form an emitter follower circuit. Transistor T4
The emitter voltages of T5 and T5 are output as the output signal of the current switch circuit CS1, that is, the complementary output signals x0 and ▼, respectively, and the corresponding current mirror circuits CM1 (first CMOS current mirror circuit) and CM2 (second CMOS current mirror circuit) Supplied to

The bipolar current switch circuit CS1 includes the transistor T3
A level determination operation is performed in which the reference potential Vbb applied to the base is set to a logic threshold level. That is, the X address signal AX0 is set to the high level of the ECL level, and the level is set to the reference potential Vb at the base of the transistor T2.
Above b, the collector current of transistor T2 increases. At this time, on the contrary, the collector current of the transistor T3 decreases, and as a result, the transistor T3 is cut off. Accordingly, the collector voltage of the transistor T3 is at the high level such as the ground potential of the circuit, the collector voltage of the transistor T2 is a predetermined low level determined by the current value I ₂ and the resistance R1 of the current source IS2. On the other hand, when the X address signal AX0 is set to the low level of the ECL level and becomes lower than the reference potential Vbb at the base of the transistor T2, the collector current of the transistor T3 increases. At this time, on the contrary, the collector current of the transistor T2 decreases, and as a result, the transistor T2 is cut off. Accordingly, the collector voltage of the transistor T2 becomes substantially circuit high level such as the ground potential, the collector voltage of the transistor T3 and the current value I ₂ of the current source IS2 resistor R
It becomes a predetermined low level determined by 2. The collector voltages of the differential transistors T2 and T3 are further reduced by the base-emitter voltages of the transistors T4 and T5 constituting the emitter follower circuit, and the complementary output signal x0.
▼

Complementary output signal x0, ▲ ▼ of current switch circuit CS1
Is the P-channel MOSFET Q that constitutes the current mirror circuit CM1
It is supplied to the gates of 1 and Q2, respectively. After being inverted by crossing the non-inverting and inverting signal lines, they are supplied to the gates of P-channel MOSFETs Q3 and Q4 constituting another current mirror circuit CM2.

MOSFET Q1 (first MOSFET) and Q of current mirror circuit CM1
The source of 2 (third MOSFET) is coupled to the ground potential of the circuit. Between the drain of MOSFET Q1 and the power supply voltage Vee of the circuit, an N-channel MOSFET Q21 having a gate and a drain connected in common to form a diode is provided.
(A second MOSFET) is provided. Further, between the drain of the MOSFET Q2 and the ground potential of the circuit, the MOSFET Q21 and the N-channel MOSFET Q22 (the fourth M
OSFET) is provided. The voltage at the drains of the MOSFETs Q2 and Q20 that are commonly coupled is used as the output signal of the current mirror circuit CM1, that is, the inverted output signal ▼.

Complementary internal signal x0 output from current switch circuit CS1
When ▲ is a logic “0”, that is, when the inverted internal signal ▼ is at a high level and the non-inverted internal signal x0 is at a low level, the conductance of the MOSFET Q1 is reduced and its drain current is reduced. This drain current is transmitted by the MOSFETs Q21 and Q22 in the form of a current mirror, and as a result, the conductance of the MOSFET Q22 is reduced. MOSFET Q2 has its gate voltage raised,
On the contrary, its conductance is increased. This allows
The inverted output signal ▼ of the current mirror circuit CM1 is almost at the high level of the MOS level such as the ground potential of the circuit.

On the other hand, when the complementary internal signal x0 • ▲ ▼ becomes logic “1”, the reverse operation is performed, and the current mirror circuit CM1
Is almost at the low level of the MOS level like the power supply voltage Vee of the circuit.

The current mirror circuit CM2 has exactly the same circuit configuration as the current mirror circuit CM1, and performs an operation complementary to the current mirror circuit CM1. The current mirror circuit CM2 detects the complementary internal signal x
The non-inverted output signal cx0 having a level complementary to the inverted output signal ▼ is formed by inverting and supplying 0 供給.

The inverted output signal ▲ ▼ of the current mirror circuit CM1 is output from the corresponding address distribution circuit AD1 (first bipolar CMOS
It is supplied to the gates of a P-channel MOSFET Q5 and an N-channel MOSFET Q25 constituting a CMOS inverter circuit of a composite drive circuit, and is further supplied to an N-channel MOSFET Q26 (a fifth MOSFET).
T) is supplied to the gate. Also, the CMO of the other address distribution circuit AD2 (second bipolar / CMOS composite drive circuit)
It is supplied to the source of the P-channel MOSFET Q6 constituting the S inverter circuit, that is, the power supply voltage terminal. Similarly, the non-inverted output signal cx0 of the current mirror circuit CM2 is supplied to the gates of the P-channel MOSFET Q6 and the N-channel MOSFET Q28 constituting the CMOS inverter circuit of the corresponding address distribution circuit AD2, and the N-channel MOSFET Q29 (the fifth MOSFE
T) is supplied to the gate. Also, a P-channel M constituting the CMOS inverter circuit of the other address distribution circuit AD1 is used.
It is supplied to the source of OSFET Q5, that is, the power supply voltage terminal.

The commonly coupled drains of the MOSFETs Q5 and Q25 of the address distribution circuit AD1 are connected to the output bipolar transistor T6 (first
Bipolar transistor). The collector of transistor T6 is coupled to the circuit's ground potential. An output bipolar transistor T7 (second bipolar transistor) is provided between the emitter of the transistor T6 and the power supply voltage Vee of the circuit. The base of transistor T7 is coupled to the source of MOSFET Q26. Between the base of the transistor T7 and the power supply voltage Vee of the circuit,
An N-channel MOSFET Q27 (sixth MOSFET) is provided. The drain of MOSFET Q26 is coupled to the gate of MOSFET Q27 and is commonly coupled to the collector of transistor T7. The collector voltage of the transistor T7 is equal to the output signal of the address distribution circuit AD1, that is, the non-inverted internal address signal a.
It is supplied to the X address decoder XDCR as x0.

Similarly, the commonly coupled drains of MOSFETs Q6 and Q28 of address distribution circuit AD2 are output bipolar transistors.
It is coupled to the base of T8 (first bipolar transistor). The collector of transistor T8 is coupled to the circuit's ground potential. An output bipolar transistor T9 (second bipolar transistor) is provided between the emitter of the transistor T8 and the power supply voltage Vee of the circuit. The base of transistor T9 is coupled to the source of MOSFET Q29. An N-channel MOSFET Q30 (sixth MOSFET) is provided between the base of the transistor T9 and the power supply voltage Vee of the circuit. The drain of MOSFET Q29 is coupled to the gate of MOSFET Q30 and is commonly coupled to the collector of transistor T9. The collector voltage of the transistor T9 is supplied to the X address decoder XDCR as an output signal of the address distribution circuit AD2, that is, an inverted internal address signal ▼.

When the X address signal AX0 is set to logic “1” and the inverted output signal ▲ ▼ of the current mirror circuit CM1 is low level or the non-inverted output signal cx0 of the current mirror circuit CM2 is high level, the MOSFET Q5 constituting the CMOS inverter circuit Is
The source is set to a high level such as the ground potential of the circuit, and the gate is set to a low level such as the power supply voltage Vee of the circuit, thereby turning on the circuit. Therefore, the base voltage of the transistor T6 becomes high level,
T6 is turned on. At this time, the MOSFET Q26 is turned off and the base current of the transistor T7 is cut off, so that the collector current is reduced. This causes the collector voltage of the transistor T7 to rise,
Q27 turns on. When the MOSFET Q27 is turned on, the transistor T7 has its base capacitance discharged to a low level such as the power supply voltage Vee of the circuit, and is turned off. As a result, the collector voltage of the transistor T7, that is, the non-inverted internal address signal ax0 is set to a high level such as the ground potential of the circuit.

In the address distribution circuit AD2, the inverted output signal ▲ ▼ of the current mirror circuit CM1 is set to low level,
By setting the non-inverted output signal cx0 of CM2 to high level,
N-channel MOSFET Q28 for CMOS inverter circuit
However, although the source voltage of the P-channel MOSFET Q6 is at a low level, the transistor is turned on. Therefore, the base voltage of the transistor T8 becomes low level, and the transistor T8 is cut off. At this time, MOSFET Q2
9 turns on, and the transistor T9 and the MOSFET Q30
The transistor T9 is temporarily turned on until the collector voltage of the transistor T9 sufficiently decreases. This allows the transistor T9
Collector voltage, that is, the inverted internal address signal ▲
▼ indicates a low level like the power supply voltage Vee of the circuit.

On the other hand, when the X address signal AX0 becomes logic “0”, the inverted output signal ▼ of the current mirror circuit CM1 is set to the high level, and the non-inverted output signal cx0 of the current mirror circuit CM2 is set to the low level. As a result, the address distribution circuits AD1 and AD2 execute the operations described above, respectively. As a result, the output signal of the address distribution circuit AD1, that is, the non-inverted internal address signal ax0 becomes low level,
The output signal of the address distribution circuit AD2, that is, the inverted internal address signal ▼ becomes high level.

By the way, for some reason, the X address signal
When AX0 becomes an intermediate level of the ECL level and becomes the same level as the reference potential Vbb at the base of the transistor T2,
Both complementary internal signals x0 and ▼ of the current switch circuit CS1 have the same intermediate level. As a result, the inverted output signal ▼ and the non-inverted output signal cx0 of the CMOS current mirror circuits CM1 and CM2 also have the same intermediate level. As described above, the inverted output signal ▼ and the non-inverted output signal cx0 are output to the CMOS of the corresponding address distribution circuits AD1 and AD2.
In addition to being supplied to the input terminals of the inverter circuit, they are also supplied to the power supply voltage terminals on the P-channel MOSFET side of the CMOS inverter circuits of the other address distribution circuits AD2 and AD1.

In the address distribution circuits AD1 and AD2, the current mirror circuit CM
When the inverted output signal ▲ ▼ and the non-inverted output signal cx0 supplied from 1 and CM2 are both at the intermediate level, the CMO
N-channel MOSFET Q25 that constitutes the S inverter circuit and
Q28 turns on. However, one P channel M
The OSFETs Q5 and Q6 have their source voltages similarly at the intermediate level, so that the gate-source voltage becomes 0V, and eventually remains off. As a result, the base voltages of the transistors T6 and T8 become low levels like the power supply voltage Vee of the circuit, and the transistors T6 and T8 are both cut off. MOSFETs Q26 and Q29 output inverted signal ▲
▼ and the non-inverted output signal cx0 attain an intermediate level, thereby turning on a weekly ON state. Therefore, the transistors T7 and T9 are similarly turned on weekly,
Since the transistors T6 and T8 are in the cutoff state, no through current flows through the transistors T6 and T7 or the transistors T8 and T9. That is, in the bipolar CMOS type RAM of this embodiment, even when the X address signal AX0 is set to the intermediate level, the above-described latch-up does not occur.

As described above, the bipolar CMOS type RAM of this embodiment
Has a current switch circuit and CMOS for each input terminal.
An input buffer including a current mirror circuit and a bipolar / CMOS composite driving circuit is provided. In each input buffer, the output signal of the CMOS current mirror circuit is supplied as an input signal to one corresponding bipolar / CMOS composite drive circuit, and the corresponding other bipolar / CM
P channel MO of CMOS inverter circuit of OS composite drive circuit
It is supplied to the power supply voltage terminal on the SFET side. For this reason, even when the input signal is at an intermediate level of the ECL level and the output signals of the current mirror circuits are both at the intermediate level, the output signal of the CMOS inverter circuit of the bipolar / CMOS composite drive circuit is fixed at the low level. This prevents through current through the two output transistors connected in totem pole connection, thereby preventing latch-up of the CMOS inverter circuit.

As shown in the present embodiment, when the present invention is applied to a semiconductor memory device such as an ECL interface bipolar CMOS RAM, the following effects can be obtained. (1) One CMOS corresponding to the base of one output transistor of the bipolar / CMOS composite drive circuit of the input buffer
The power supply voltage terminal on the P-channel MOSFET side of the CMOS inverter circuit provided between the output terminal of the current mirror circuit and
When the input signal is set to an intermediate level and both output signals of the CMOS current mirror circuit are set to the intermediate level by coupling to the output terminal of the corresponding other CMOS current mirror circuit, the CMOS
Turn off the P-channel MOSFET of the inverter circuit,
The effect is obtained that the output signal of the CMOS inverter circuit can be fixed at a low level.

(2) According to the above item (1), one of the output transistors connected to the totem pole of the bipolar / CMOS composite driving circuit can be reliably cut off, and the through current by these output transistors can be prevented. Is obtained.

(3) According to paragraphs (1) and (2) above,
The effect is obtained that the latch-up of the CMOS inverter circuit of the CMOS composite drive circuit can be prevented.

(4) According to the above items (1) to (3), it is possible to prevent a malfunction of a bipolar CMOS type RAM or the like including the input buffer as described above, and to obtain an effect of improving the reliability.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in the circuit diagram of FIG. 1, the bipolar current switch circuit CS1 may be configured as a multiple-input logic gate circuit by providing a plurality of transistors in parallel with the transistor T2. Further, the input level shift circuit and the bipolar current switch circuit may further include a diode or the like for correcting the level of the internal signal. In the circuit block diagram of FIG.
The resistances R5 and R6 of each memory cell MC of −ARY are P
It may be replaced with a channel MOSFET. Further, the memory array M-ARY may be configured by a plurality of memory mats, and at this time, each address decoder may be shared by the plurality of memory mats. Further, various embodiments such as a specific circuit configuration of the X address buffer XADB shown in FIG. 1, a block configuration of the bipolar CMOS type RAM shown in FIG. 2, and a combination of control signals, address signals, and the like are described. Can be taken.

In the above description, the invention made by the present inventor has been mainly applied to the bipolar / CMOS
The case where the present invention is applied to the X address buffer XADB of the type RAM has been described. However, the present invention is not limited to this. For example, the Y address buffer YADB of the bipolar CMOS type RAM may be used.
And other types of semiconductor memory devices including an input circuit or a similar input buffer. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device including an input buffer including at least a bipolar current switch circuit, a CMOS current mirror circuit, and a bipolar / CMOS composite drive circuit, and a digital device including such a semiconductor memory device.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, the power supply voltage terminal on the P-channel MOSFET side of the CMOS inverter circuit provided between the base of one output transistor of the bipolar / CMOS composite drive circuit of the input buffer and the output terminal of the corresponding one of the CMOS current mirror circuits, By coupling to the output terminal of the other corresponding CMOS current mirror circuit, the output signal of the CMOS inverter circuit can be determined to be low level when the input signal is at the intermediate level, so the through current of the bipolar / CMOS composite drive circuit can be reduced. This prevents the CMOS inverter circuit from latching up.

[Brief description of the drawings]

FIG. 1 shows a bipolar CMOS type RA to which the present invention is applied.
FIG. 2 is a circuit diagram showing an embodiment of an X address buffer of M, FIG. 2 is a block diagram of an embodiment of a bipolar CMOS type RAM including the X address buffer of FIG. 1, and FIG. FIG. 4 is a cross-sectional view for explaining latch-up of a CMOS type RAM. FIG. 4 is a circuit diagram showing an example of an X address buffer of a conventional bipolar CMOS type RAM. XADB: X address buffer, CS1-: Bipolar current switch circuit, CM1, CM2: CMOS current mirror circuit, AD1
~ AD4 ... Address distribution circuit. T1-T13 …… NPN type bipolar transistor, Q1-Q16…
... P-channel MOSFET, Q21-Q44 ... N-channel MOSF
ET, R1 to R6: resistor, N1, N2: CMOS inverter circuit, I
S1, IS2: Constant current source. M-ARY: Memory array, MC: Memory cell, CSW ...
Column switch, XDCR ... X address decoder, YDCR ...
... Y address decoder, YADB ... Y address buffer,
SA: Sense amplifier, DOB: Data output buffer, WA
…… Write amplifier, DIB …… Data input buffer, TC…
... Chip control circuit. PSUB: P-type semiconductor substrate, Nwell: N-type well region, P
well: P-type well region, PIs: P-type isolation, NBL: N-type buried layer, Tcs: Parasitic transistor, Ts
n, Tsp …… parasitic thyristor, Rss …… substrate resistance, Rcs ……
Parasitic resistance.

Claims (3)

(57) [Claims] A bipolar current switch circuit for determining a level of an input signal according to a predetermined reference potential; first and second CMOS current mirror circuits for respectively receiving a complementary output signal of the bipolar current switch circuit and an inverted signal thereof; One CMOS current mirror corresponding to the first and second bipolar transistors provided in correspondence with the first and second CMOS current mirror circuits and provided in series between the first and second power supply voltages A CMOS inverter circuit provided between the output terminal of the circuit and the base of the first bipolar transistor and receiving an output signal of the other CMOS current mirror circuit corresponding to the power supply voltage terminal;
And a second bipolar / CMOS composite driving circuit. 2. The first and second CMOS current mirror circuits receive a first power supply voltage at a source thereof and receive an inverted output signal or a non-inverted output signal of the bipolar current switch circuit corresponding to a gate thereof. 1st conductivity type first MOSFET
And a second conductive type second diode provided between the drain of the first MOSFET and a second power supply voltage.
And a third MOSFET of a first conductivity type provided between its output node and a first power supply voltage and receiving a non-inverted output signal or an inverted output signal of the bipolar current switch circuit corresponding to its gate. And a second MOSFET provided between the output node and a second power supply voltage, and a fourth MOSFET of a second conductivity type in a current mirror configuration. The second bipolar / CMOS composite drive circuit further includes a second bipolar transistor provided between the collector and the base of the second bipolar transistor for receiving an output signal of the CMOS current mirror circuit corresponding to the gate of the second bipolar transistor.
A fifth conductive type MOSFET, a second conductive type second MOSFET provided between the base of the second bipolar transistor and a second power supply voltage, and having a gate coupled to the collector of the second bipolar transistor. 6. The semiconductor memory device according to claim 1, wherein each of said semiconductor memory devices includes a MOSFET. 3. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a bipolar CMOS type RAM having an ECL interface.