JP3251281B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and for example, its input and output signal levels are ECL (Emitter Coupled L).
ogic) level, and the internal signal level is MOS level. Bipolar CMOS (hereinafter abbreviated as BiCMOS) type
The present invention relates to a technique particularly effective when used for a RAM (random access memory) or the like.

[Conventional technology]

MOSFET (metal oxide semiconductor type field effect transistor.
In this specification, a memory array in which static memory cells each including a MOSFET and an insulated gate field effect transistor are collectively arranged, and a peripheral circuit including an ECL circuit and a Bi-CMOS circuit are described. Bi ・ CM with
There is OS type RAM.

For the Bi-CMOS type RAM, see, for example, October 1986, Journal of Solid State Stats (IEEE) Journal of Solid State Circuits.
e Circuits), Vol. SC-21, No. 5 ”, pp. 681-684.

[Problems to be solved by the invention]

In the Bi-CMOS type RAM described above, an input signal such as an address signal input from the outside is set to an ECL level having a signal amplitude of, for example, 0.8 V, and an internal signal such as an internal address signal transmitted internally is used. The signal has a MOS level with a signal amplitude of, for example, 5V. For this reason, Bi
As shown by the X address buffer XAB in FIG. 6, the CMOS type RAM has an ECL level X address signal AX0.
And a unit address drive circuit U that outputs a MOS-level internal address signal ax0 and the like.
A unit level conversion circuit ULC composed of MOSFETs Q7 and Q8 and Q21 and Q22 is provided between AD and AD. These unit level conversion circuits are required for each bit of an input signal such as an address signal. As a result, Bi-CMOS type RA
As the number of circuit elements of M increases, the chip area increases, and the transmission delay time of each input signal increases.
Access time of BI / CMOS type RAM becomes slow.

An object of the present invention is to provide a semiconductor integrated circuit device such as a Bi-CMOS type RAM in which an address buffer and the like are simplified.

It is another object of the present invention to reduce the chip area and stabilize the operation of a Bi-CMOS type RAM without hindering high-speed operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
A semiconductor substrate on which a Bi-CMOS type RAM or the like is formed is a so-called SOI substrate in which an element substrate is bonded to a structural substrate via an insulating layer such as silicon oxide, for example. The islands are divided into a plurality of islands, and different absolute values of the electric field voltage and the substrate potential are supplied to each island.

Specifically, a first substrate, a second substrate bonded to the first substrate via an insulating layer, and a plurality of different substrates arranged on the second substrate and different from one input power supply voltage. And a voltage generation circuit for generating a power supply voltage of the second substrate. The element region of the second substrate is divided into a plurality of islands made of single-crystal silicon by an isolation region, and at least one of the plurality of islands Is configured such that a power supply voltage or a substrate potential having an absolute value different from that of any of the other islands is supplied from the voltage generation circuit.

Further, one of the plurality of islands is formed with an ECL circuit that uses a first power supply voltage as an operation power supply, and the other has an operation power supply voltage that is different from the first power supply voltage. And a CMOS or bipolar CMOS circuit that transmits and receives signals to and from the ECL circuit is formed, and at least one of the first power supply voltage and the second power supply voltage is supplied from the voltage generation circuit and included in the ECL circuit The collector electrode of the bipolar transistor and the gate electrode of the MOSFET included in the CMOS or bipolar CMOS circuit are electrically connected without a level conversion circuit.

Alternatively, instead of the above, MOSFETs having different threshold voltages may be respectively formed in a plurality of islands.

(Operation)

According to the above means, for example, ECL circuit and CMOS or Bi
・ Signals can be sent to and received from the CMOS circuit without passing through the level conversion circuit, and formed on each island.
The threshold voltage of the MOSFET can be changed intentionally.
This simplifies the circuit configuration of an address buffer or the like such as a Bi-CMOS RAM and reduces the transmission delay time of an input signal or the like. As a result, the chip area can be reduced and the operation can be stabilized without hindering the high-speed operation of the Bi-CMOS type RAM or the like.

〔Example〕

FIG. 1 shows a substrate layout diagram of an embodiment of a Bi-CMOS type RAM to which the present invention is applied, and FIG. 2 shows a circuit block diagram of the embodiment. FIGS. 3 and 4 are partial circuit diagrams of an embodiment of the X address buffer XAB and the data output buffer DOB included in the Bi-CMOS type RAM of FIG. 2, and FIG. As shown in Fig. 1, Bi
An AB sectional view of one embodiment of the CMOS type RAM is shown. Based on these figures, the Bi-CMOS type RAM of this embodiment
An outline of the configuration, operation, layout, and features of the configuration will be described. In each of the circuit diagrams, the MOSFET with an arrow at its channel (back gate) portion is a P-channel type MOSFET, and an N-channel MOSFET without an arrow is added.
Shown separately from ET. Although not particularly limited, the illustrated bipolar transistors are all NPN transistors.

In FIG. 1, the Bi.CMOS type RAM according to this embodiment has, as a basic configuration, a pair of memory arrays ARYU and ARYL arranged so as to occupy most of the area of the semiconductor substrate SUB. A Y address decoder YD is arranged in the middle of these memory arrays, and a corresponding column switch CS is provided between the Y address decoder and each memory array.
WU and CSWL are arranged respectively. On the left side of the memory arrays ARYU and ARYL, corresponding X address decoders XDU and XDL are arranged, respectively. Outside these X address decoders, an X address buffer XAB and a Y address buffer YAB are arranged, respectively. Column switch CSW
On the left side of U, write amplifier WA and data input buffer D
IB is arranged, and a sense amplifier SA and a data output buffer DOB are arranged on the left side of the column switch CSWL. Further, on the left side of the Y address decoder YD, a voltage generation circuit is provided.
VG and a timing generation circuit TG are arranged.

In this embodiment, a semiconductor substrate SUB is a P-type element substrate for forming a circuit element as shown in FIG.
A so-called SOI (Silicon On Insulator) substrate in which a PSUB (second substrate) is bonded to a structural substrate CSUB (first substrate) via an insulating layer made of, for example, silicon oxide.
The element substrate PSUB is usually formed of single crystal silicon. Although not particularly limited, the element substrate PSUB is divided into a plurality of islands IL1 to IL4 by separation regions such as U-shaped separation grooves U2 and U4, as exemplified by dotted lines in FIG.

Among them, the island IL1 includes, although not particularly limited to, a voltage generation circuit VG and an ECL circuit of an X address buffer XAB, a Y address buffer YAB, a data input buffer DIB, a data output buffer DOB, and a timing generation circuit TG. Power supply voltage VEE1 with a relatively large absolute value such as -5V
(First power supply voltage) is supplied as operating power. The island IL2 includes the X address buffers XAB, Y
Bi-CMOS circuits for the address buffer YAB, the data input buffer DIB, the data output buffer DOB and the timing generator TG are formed, and the X address decoders XDU and X
DL and the write amplifier WA and the sense amplifier SA are formed, and the power supply voltage VEE2 having a relatively small absolute value such as -3 V
(Second power supply voltage) is supplied as operating power. Furthermore, the islands IL3 and IL4 have memory arrays ARYU and
ARYL are formed, and the power supply voltage VEE2 is supplied as operating power.

On the other hand, as shown in FIG. 5, P-type element substrates PSUB1 and PSUB2 divided as islands IL1 or IL2 have
The corresponding power supply voltages VEE1 and VEE2 are supplied as substrate potentials, respectively, and the P-type element substrates PSUB3 and PSUB4 divided as islands IL3 are not particularly limited, but the absolute values thereof are slightly larger than the power supply voltage VEE2. VE
E3 is supplied. As a result, the memory arrays ARYU and ARYL
Is relatively large,
As a result, the leakage current in the memory array of the Bi-CMOS type RAM is reduced, and the operation is stabilized.

In FIG. 2, memory arrays ARYU and ARYL are each composed of (m + 1) word lines W0 to Wm arranged in the horizontal direction and (n + 1) A set of complementary data lines D0 to Dn (where
For example, the non-inverted data line D0 and the inverted data line D0B are collectively represented as a complementary data line D0. A so-called inverted signal which is normally set to a high level and selectively set to a low level when the signal is made valid is represented by adding a B to the end of the signal name, as in an inverted data line D0B. Hereinafter, the same applies to complementary signals or complementary signal lines). At the intersection of these word lines and complementary data lines, (m + 1)
× (n + 1) static memory cells MC are arranged in a lattice pattern.

As shown in FIG. 2, each of the memory cells MC constituting the memory arrays ARYU and ARYL is a so-called high resistance load type static memory cell, and includes N-channel drive MOSFETs Q11 and Q12. These drive MOSFETs
The gate and the drain are cross-coupled to each other, and between the drain and the ground potential of the circuit, although not particularly limited, high-resistance load resistors R1 and R2 made of a polysilicon (polycrystalline silicon) layer are provided, respectively. Can be Also drive
The sources of MOSFETs Q11 and Q12 are coupled to power supply voltage VEE2. The power supply voltage VEE2 is a negative power supply voltage such as -3 V as described above. This makes the drive MOSFET
Q11 and Q12, together with the load resistors R1 and R2,
A flip-flop circuit serving as a storage element of the OS-type RAM is formed.

Driving MOSFETs Q11 and Q12 serving as non-inverting and inverting input / output nodes of a flip-flop circuit constituting each memory cell MC
Of the N-channel type control MOSFET Q1
Via 3 or Q14, it is coupled to the non-inverted or inverted signal line of the corresponding complementary data line D0-Dn, respectively. The gates of these control MOSFETs Q13 and Q14 are connected to the corresponding word lines.
Commonly coupled to W0 to Wm, respectively.

Word lines W0 to Wm forming memory arrays ARYU and ARYL
Is not particularly limited, but the corresponding X address decoder
It is coupled to XDU or XDL and is alternatively selected. Although these X address decoders are not particularly limited,
An i + 1-bit internal address signal ax0 to axi is commonly supplied from an X address buffer XAB, and a timing generation circuit
The timing signal φce is commonly supplied from the TG.

The X address decoder XDU is not particularly limited, but is selectively activated when the timing signal φce is at a high level and the internal address signal axi of the most significant bit is at a low level. In this operation state, the X address decoder XDU decodes the other internal address signals ax0 to axi-1, and selectively sets the corresponding word line of the memory array ARYU to a high level selection state. At the same time, the X address decoder XDL is selectively activated by setting the timing signal φce to high level and the internal address signal axi to high level. In this operation state, the X address decoder XDL
Decodes the internal address signals ax0 to axi-1 and selectively sets the corresponding word line of the memory array IARY to a high level selection state.

X address buffer XAB has address input terminals AX0 to AX
i + 1 bit X address signal AX0 supplied through i
AXAXi, and forms the internal address signals ax0〜axi based on these X address signals. These internal address signals are supplied to X address decoders XDU and XDL, and the most significant bit is supplied to the Y address decoder.
Supplied to YD.

Here, the X address buffer XAB is not particularly limited, but is provided corresponding to the X address signals AX0 to AXi.
Includes +1 unit circuits. Although these unit circuits are not particularly limited, as illustrated in FIG.
It includes a unit address input circuit UAR formed in IL1 and a unit address drive circuit UAD formed in island IL2.

Among them, the unit address input circuit UAR is, although not particularly limited, a so-called ECL circuit, and a transistor T1 receiving an X address signal AX0 or the like corresponding to the base thereof,
An input emitter follower circuit including a diode D1 for level shift and a constant current source S1 is included. Further, it includes a transistor T2 for receiving an output signal of the input emitter follower circuit, a transistor T3 for receiving a predetermined reference potential VBB1, a current switch circuit including a diode D2, resistors R3 and R4, and a constant current source S2. The other of the constant current sources S1 and S2 is coupled to the power supply voltage VEE1, whereby the unit address input circuit UAR uses the power supply voltage VEE1 having a relatively large absolute value such as -5V as its operation power supply.

On the other hand, the unit address drive circuit UAD is, but not limited to, a so-called Bi-CMOS circuit, and includes a pair of output transistors T4 and T5 provided in a totem pole configuration between the ground potential of the circuit and the power supply voltage VEE2. The base of the output transistor T4 is via a CMOS inverter circuit composed of a P-channel MOSFET Q5 and an N-channel MOSFET Q17,
It is coupled to the inverted output terminal of the unit address input circuit UAR. Further, between the collector and the base of the output transistor T5, an N-channel MOSFET Q18 for receiving the inverted output signal of the unit address input circuit UAR is provided at the gate thereof, and the gate is provided between the base and the power supply voltage VEE2. An N-channel MOSFET Q19 is provided which is coupled to the collector of output transistor T5, the output terminal of the circuit. M
The source of OSFET Q17 is coupled to power supply voltage VEE2. Thus, the unit address drive circuit UAD uses the power supply voltage VEE2 having a relatively small absolute value such as −3 V as its operation power supply.

By the way, as shown in FIG. 5, the semiconductor substrate SUB on which the Bi.CMOS type RAM of this embodiment is formed includes, for example, a structural substrate CSUB made of low-purity silicon and a P-type substrate made of high-purity single-crystal silicon. Is formed by chemically bonding the element substrate PSUB of this example via an insulating layer INS made of, for example, silicon oxide. As a result, a large-diameter semiconductor substrate is formed at low cost, and the cost of the Bi-CMOS RAM is reduced.

In this embodiment, the element substrate PSUB is not particularly limited, but is further divided into four P-type element substrates PSUB1 to PSUB4, that is, islands IL1 to IL4 by relatively deep isolation regions such as U-shaped isolation grooves U2 and U4. . Of these, islands
The transistor T1 and the like constituting the unit address input circuit UAR of the X address buffer XAB are formed in IL1, and the element substrate PSUB1 is supplied with the lowest potential of the unit address input circuit UAR, that is, the power supply voltage VEE1 as the substrate potential. . The islands IL2 are formed with MOSFETs Q5 and Q17 constituting the unit address drive circuit UAD of the X address buffer XAB, and the element substrate PSUB2 is provided with the lowest potential of the unit address drive circuit UAD, that is, the power supply voltage VEE2. Supplied as

From these facts, in the unit address drive circuit UAD of the X address buffer XAB, for example, the P-channel MOSFET Q5
As a result, the absolute value of the logic threshold level of the CMOS inverter circuit including Q17 and Q17 is reduced, whereby the output signal of the unit address input circuit UAR formed on the island IL1 can be converted to the unit address without passing through the level conversion circuit. It can be transmitted to the drive circuit UAD. Therefore, an X address buffer XA having many unit circuits
B and Bi ・ C with such various input buffers
The number of circuit elements of the MOS RAM is reduced, and the chip area is reduced.

Needless to say, the islands IL1 and IL2 are insulated by the U-shaped separation groove U2 as described above, so that the corresponding element substrates PSUB1 and PSUB2 have different absolute power supply voltages VE.
E1 or VEE2 can be supplied as its substrate potential. As a result, the circuits formed on these islands can operate in optimal conditions, and Bi ・ CM
The access time of the OS type RAM is shortened.

Incidentally, the control MOSFETs constituting the memory cells MC of the memory array ARYU or ARYL are provided in the islands IL3 and IL4.
Q13 and the like are formed, and the element substrates PSUB3 and PSUB4 include:
Although not particularly limited, a power supply voltage VEE3 whose absolute value is higher than the lowest potential of the memory arrays ARYU and ARYL, that is, the power supply voltage VEE2 is supplied as the substrate potential. As a result, the control MOSFET Q13 and the like have a relatively large threshold voltage, thereby reducing the leakage current of the Bi-CMOS RAM and stabilizing its operation.

Incidentally, between the element substrates PSUB1 to PSUB4 and the structural substrate CSUB, as shown in FIG. 5, capacitors C1 to C3 and the like having the insulating layer INS as a dielectric are formed. In this embodiment, the structural substrate CSUB is formed of a dielectric material made of low-purity silicon and is coupled to the circuit ground potential GND. Therefore, the capacitors C1 to C3 and the like function as power supply smoothing capacitors for the corresponding substrate potential, that is, the power supply voltages VEE1 to VEE3. As a result, fluctuations in the power supply voltages VEE1 to VEE3 are suppressed, and the operation of the Bi-CMOS RAM is stabilized.

In FIG. 2, the complementary data lines D0 to Dn forming the memory arrays ARYU and ARYL are coupled on one side to the ground potential of the circuit via the corresponding P-channel MOSFETs Q1 and Q2, and on the other side are connected to the column switch CSWU. Or
It is selectively connected to the complementary common data line CD via the corresponding switch MOSFETs Q3 and Q15 and Q4 and Q16 of CSWL. Among them, the MOSFETs Q1 and Q2 are constantly turned on when the power supply voltage VEE2 is supplied to their gates, and function as load MOSFETs for the corresponding complementary data lines D0 to Dn.

On the other hand, the gates of the switch MOSFETs Q3 and Q15 and Q4 and Q16 that constitute the column switches CSWU and CSWL are supplied with the corresponding data line selection signals Y0 to Yn or the inverted signal of the inverter circuit N1 from the Y address decoder YD. You. As a result, these switch MOSFETs are selectively and simultaneously turned on simultaneously when the corresponding data line selection signals Y0 to Yn are alternatively set to the high level, and the corresponding complementary data lines D0 to Dn are connected to the corresponding switch MOSFETs. Complementary common data line CD
Connect selectively.

Although not particularly limited, the Y address decoder YD has a Y address decoder YD.
The address buffer YAB supplies j + 1-bit internal address signals ay0 to ayj. X address buffer
The internal address signal axi of the most significant bit is supplied from XAB, and the timing signal φce is supplied from the timing generation circuit TG.

The Y address decoder YD is selectively activated by setting the timing signal φce to a high level. In this operation state, the Y address decoder YD
The internal address signals ay0 to ayj are decoded. When the internal address signal axi is at a low level, the data line selection signals Y0 to Yn corresponding to the memory array ARYU are alternatively set to a high level, and when the internal address signal axi is at a high level, the memory array The data line selection signals Y0 to Yn corresponding to ARYL are alternatively set to a high level.

The Y address buffer YAB has address input terminals AY0 to AY
j + 1-bit Y address signal AY0 supplied via j
AAYj, and forms the internal address signals ay0〜ayj and supplies them to the Y address decoder YD.

Next, the complementary data lines D0-D of the memory array ARYU or ARYL
The complementary common data line CD to which Dn is selectively connected is not particularly limited, but is coupled to the input terminal of the sense amplifier SA.
Further, it is coupled to the output terminal of the write amplifier WA. The output terminal of the sense amplifier SA is coupled to the input terminal of the data output buffer DOB, and the output terminal of the data output buffer DOB is further coupled to the data output terminal DO. On the other hand, the input terminal of the write amplifier WA is coupled to the output terminal of the data input buffer DIB, and the input terminal of the data input buffer DIB is further coupled to the data input terminal DI. Timing signals φsa and φoe are supplied from the timing generation circuit TG to the sense amplifier SA and the data output buffer DOB, respectively, and a timing signal φwe is supplied to the write amplifier WA.

The sense amplifier SA is selectively activated by the timing signal φsa being set to a high level. In this operation state, the sense amplifier SA operates the memory array ARYU
Alternatively, a small-amplitude read signal transmitted from the selected memory cell MC of the ARYL via the complementary common data line CD is amplified to obtain a MOS-level complementary read signal. These complementary read signals are transmitted to the data output buffer DOB.

When the Bi-CMOS type RAM is selected in the read mode, the data output buffer DOB is set to the timing signal φ.
When oe is set to the high level, it is selectively activated. In this operating state, the data output buffer DOB
Converts the MOS-level read signal output from the sense amplifier SA to the ECL level, and sends it out via the data output terminal DO.

Here, the data output buffer DOB is not particularly limited, but as shown in FIG.
A unit output buffer circuit UOB receiving internal output data do gate-controlled according to oe, and a unit output drive circuit UOD receiving an output signal of the unit output buffer circuit. Among these, the unit output buffer circuit UOB is not particularly limited, but the P-channel MOSFET Q6 and the N-channel MO
CMOS inverter circuit consisting of SFETQ20 and transistor T
6 and an emitter follower circuit including a constant current source S3. These circuits are formed in the island IL2 and use the power supply voltage VEE2 as an operation power supply.

On the other hand, the unit output drive circuit UOD of the data output buffer DOB
Includes a current switch circuit including a pair of differential transistors T7 and T8, load resistors R5 and R6, and a constant current source S4. These circuits are formed in the island IL1 and use the power supply voltage VEE1 as an operation power supply.

From these facts, the unit output buffer circuit UOB and the unit output drive circuit UOD constituting the data output buffer DOB
Can transmit a signal without passing through a level conversion circuit, like the unit address input circuit UAR and the unit address drive circuit UAD which constitute the X address buffer XAB described above. Is simplified.

The data input buffer DIB converts the ECL level write data supplied via the data input terminal DI into a MOS level complementary write signal when the BiCMOS RAM is selected in the write mode, Transmit to the light amplifier WA.

The write amplifier WA is selectively activated by setting the timing signal φwe to a high level. In this operation state, the write amplifier WA forms a write current according to the complementary write signal supplied from the data input buffer DIB, and selects the selected memory cell of the memory array ARYU or ARYL via the complementary common data line CD. Write to MC.

The timing generation circuit TG forms the above various timing signals based on the chip selection signal CS and the write enable signal WE supplied as the start control signal,
Supply to each circuit of RAM.

The Bi-CMOS type RAM of this embodiment further includes the voltage generation circuit VG as described above. The voltage generating circuit VG forms the power supply voltages VEE2 and VEE3 based on the power supply voltage VEE supplied via the power supply voltage supply terminal VEE, and generates a BiCMOS CMOS RA.
Supply to each part of M. Although the power supply voltage VEE is not particularly limited, it is a negative power supply voltage such as -5 V, and is supplied as it is to the respective parts of the Bi-CMOS RAM as the power supply voltage VEE1.

As shown in the above embodiment, the present invention is
By applying the present invention to a semiconductor integrated circuit device such as an OS type RAM, the following operation and effect can be obtained. (1) A semiconductor substrate on which a Bi-CMOS type RAM or the like is formed is a so-called SOI substrate in which an element substrate is bonded to a structural substrate via an insulating layer such as silicon oxide, for example. For example, by dividing the island into a plurality of islands by a separation region such as a U-shaped separation groove and supplying power supply voltages having different absolute values to these islands, for example, an ECL circuit and a CMO
An effect is obtained that a signal can be exchanged with the S or Bi.CMOS circuit without passing through the level conversion circuit.

(2) According to the above item (1), the circuit configuration of an input circuit such as an address buffer such as a Bi-CMOS RAM and an output circuit such as a data output buffer can be simplified, and the transmission delay time of input signals and the like can be reduced. The effect is obtained.

(3) According to the above items (1) and (2), Bi / CMOS type RA
The effect is obtained that the number of circuit elements can be reduced and the chip area can be reduced without hindering the high-speed operation of M or the like.

(4) In the above item (1), by supplying substrate potentials having different absolute values to a plurality of islands using the same power supply voltage as an operation power supply, MOs formed on these islands are supplied.
The effect is obtained that the threshold voltage of the SFET can be intentionally changed.

(5) According to the above item (4), it is possible to reduce the leakage current in a memory array such as a Bi-CMOS type RAM and to stabilize the operation.

(6) In the above item (1), the capacitance formed by forming the structural substrate based on the conductive material, supplying an installation potential of the circuit, and using the insulating layer as a dielectric between the element substrate and the structural substrate. Is used as a power supply smoothing capacitor, the effect of suppressing fluctuations in the power supply voltage of a Bi-CMOS RAM or the like can be obtained.

(7) According to the above item (6), the effect of stabilizing the operation of the Bi-CMOS RAM or the like can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in FIG. 1, the power supply voltage VEE2 may be supplied as the substrate potential to the element substrate on which the memory arrays ARYU and ARYL are formed, similarly to the island IL2. In addition, Bi ・ CM shown in the figure
The board layout of the OS type RAM is only one example, and various embodiments can be considered. The number of islands formed by dividing the element substrate PSUB is not limited by this embodiment. In FIG. 2, the memory array ARYU
And ARYL include load resistors R1 and R2
Instead, a load means comprising a MOSFET may be used, or a so-called CMOS memory cell in which a pair of CMOS inverter circuits are cross-coupled. Bi ・ CMOS
The type RAM can include four or more memory arrays, and each memory array may be configured by a plurality of memory mats. The Bi-CMOS RAM can adopt a so-called multi-bit configuration for simultaneously inputting and outputting a plurality of stored data. In FIG. 3, an X address buffer XAB
Another unit address driving circuit UAD for forming the inverted internal address signal ax0B and the like can be provided. In this case, the input terminal may be coupled to the non-inverted output terminal of the unit address input circuit UAR. Unit address drive circuit UA
D may be a so-called CMOS circuit composed of only MOSFETs. In FIG. 5, various embodiments can be considered for the specific structure and combination of the SOI substrate, each island, and the circuit element. Further, the block configuration of the Bi-CMOS type RAM shown in FIG. 2, the specific circuit configuration of the X address buffer XAB and the data output buffer DOB shown in FIGS. 3 and 4, and the absolute value and Various embodiments such as polarity can be adopted.

In the above description, the case where the invention made by the present inventor is applied to a Bi-CMOS type RAM, which is the background of the application, has been described. However, the present invention is not limited thereto. The present invention can also be applied to various semiconductor memory devices and logic integrated circuit devices such as gate arrays. INDUSTRIAL APPLICABILITY The present invention can be widely applied to various types of semiconductor integrated circuit devices in which at least different signal transmission levels are mixed or an effect of dividing an element substrate into a plurality is expected.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, a semiconductor substrate on which a Bi-CMOS type RAM or the like is formed is a so-called SOI substrate in which an element substrate is bonded to a structural substrate via an insulating layer such as silicon oxide, for example. Dividing into a plurality of islands by a separation region such as a separation groove and supplying a different absolute value of a power supply voltage and a substrate potential to each island, specifically, a first substrate and an insulating layer provided on the first substrate And a voltage generation circuit disposed on the second substrate and configured to generate a plurality of different power supply voltages from one input power supply voltage. The element region of the substrate is divided into a plurality of islands made of single crystal silicon by an isolation region, and at least one of the plurality of islands has a power supply voltage or an absolute value different from any of the other islands. ECL substrate potential is configured to be supplied from the voltage generating circuit, further, the one of the plurality of islands, where the first power supply voltage and operating power supply
A CMOS or bipolar CMOS circuit is formed, which uses a second power supply voltage different from the first power supply voltage as an operation power supply and exchanges signals with the ECL circuit, At least one of the first power supply voltage and the second power supply voltage is supplied from a voltage generation circuit, and a collector electrode of a bipolar transistor included in the ECL circuit and a CMOS.
Alternatively, by connecting electrically to the gate electrode of the MOSFET included in the bipolar CMOS circuit without passing through the level conversion circuit, for example, the ECL circuit and the CMOS or BiCMOS
Signals can be sent to and received from the circuit without passing through the level conversion circuit, and MOSFETs formed on each island
Can be intentionally changed. This simplifies the circuit configuration of an address buffer or the like such as a Bi-CMOS RAM, reduces the transmission delay time of an input signal or the like, and reduces the leakage current of a memory array or the like. As a result, the chip area can be reduced and the operation can be stabilized without hindering the high-speed operation of the Bi-CMOS type RAM or the like.

[Brief description of the drawings]

FIG. 1 is a board layout diagram showing an embodiment of a Bi-CMOS type RAM to which the present invention is applied. FIG. 2 is a circuit block diagram showing an embodiment of the Bi-CMOS type RAM of FIG. FIG. 3 is a partial circuit diagram showing an embodiment of an X-address buffer included in the Bi-CMOS type RAM of FIG. 2, and FIG. 4 is a data diagram included in the Bi-CMOS type RAM of FIG. FIG. 5 is a partial circuit diagram showing an embodiment of an output buffer. FIG. 5 is a circuit diagram showing an embodiment of a Bi-CMOS type RAM shown in FIG.
FIG. 6 is a partial circuit diagram showing an example of an X address buffer included in a conventional Bi-CMOS RAM. SUB: Semiconductor substrate, IL1 to IL4: Island. ARYU, ARYL …… Memory array, MC …… Memory cell, CSWU,
CSWL ... column switch, XDU, XDL ... X address decoder, YD ... Y address decoder, XAB ... X address buffer, YAB ... Y address buffer, WA ... write amplifier, SA ... sense amplifier, DIB ... … Data input buffer, DOB… Data output buffer, TG… Timing generation circuit, VG… Voltage generation circuit, C1 to C3… Power supply smoothing capacitance. Q1-Q8: P-channel MOSFET, Q11-Q22: N-channel MOSFET, N1: CMOS inverter circuit, R1-R6: Resistor, T1-T8: NPN bipolar transistor, D1-D2
... Diodes, S1 to S4 ... Constant current sources. UAR: Unit address input circuit, ULC: Unit level conversion circuit, UAD: Unit address drive circuit, UOB: Unit output buffer circuit, UOD: Unit output drive circuit. CSUB …… Structure substrate, PSUB1 to PSUB3 …… P-type element substrate, IN
S: insulating layer, U1 to U4: U-shaped separation groove, NWELL: N-well region, PWELL: P-well region, NBL: N-type buried layer
B: Base region, E: Emitter region, C: Collector region, S: Source region, G: Gate region, D ...
Drain region.

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/10 371 H01L 27/04 G (72) Inventor Kazuhisa Miyamoto 2326 Imai, Ome-shi, Tokyo Device Development Center, Hitachi, Ltd. (72) Inventor Masanori Odaka 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi Ltd. (72) Inventor Takahide Ikeda 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi Ltd. (56) References JP-A-63-211193 (JP, A) JP-A-2-168646 (JP, A) JP-A-2-49464 (JP, A) JP-A-2-49448 (JP, A) JP-A-62 JP-A-119958 (JP, A) JP-A-1-164064 (JP, A) JP-A-2-3149 (JP, A) JP-A-2-171024 (JP, A) JP-A-1-298763 (JP, A ) Patent Akira 62-181464 (JP, A) JP flat 2-181962 (JP, A)

Claims (2)

(57) [Claims] 1. A first substrate, a second substrate joined to the first substrate via an insulating layer, and a first power supply voltage disposed on the second substrate and input from one power supply voltage. A voltage generating circuit for generating a plurality of different power supply voltages; the element region of the second substrate is divided into a plurality of islands made of single-crystal silicon by an isolation region; At least one of the islands is configured such that a power supply voltage or a substrate potential having an absolute value different from that of any of the other islands is supplied from the upper voltage generation circuit, and one of the plurality of islands operates the first power supply voltage An ECL circuit serving as a power supply is formed, and the other is a CMOS or bipolar circuit which uses a second power supply voltage different from the first power supply voltage as an operation power supply and transmits / receives a signal to / from the ECL circuit. CMOS circuit At least one of the first power supply voltage and the second power supply voltage is supplied from the voltage generation circuit and is supplied to the collector electrode of a bipolar transistor included in the ECL circuit and the CMOS or bipolar CMOS circuit. A semiconductor integrated circuit device which is electrically connected to a gate electrode of a MOSFET included therein without passing through a level conversion circuit. 2. A first substrate, a second substrate joined to the first substrate via an insulating layer, and a first power supply voltage arranged on the second substrate and input from one power supply voltage. A voltage generating circuit for generating a plurality of different power supply voltages; the element region of the second substrate is divided into a plurality of islands made of single-crystal silicon by an isolation region; At least one is configured such that a power supply voltage or a substrate potential having an absolute value different from that of any of the other islands is supplied from the voltage generation circuit, and the plurality of islands each include a MOSFET having a different threshold voltage. A semiconductor integrated circuit device formed.