JPS61218166A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce a noise level generated in a power source voltage wirings or a ground wire of a circuit by dividing two memory mats at right and left sides of an X-address decoder, and symmetrically assigning addresses to the divided memory. CONSTITUTION:Two memory mats M-ARYR, M-ARYL are disposed at right and left sides on X-address decoder XDCR as a center. The mats are divided in data line direction to form a plurality of memory arrays M0-M7. Addresses are assigned symmetrically to the memory arrays at the decoder XDCR as a center. Thus, the wiring length for connecting between the memory arrays of pairs become different according to word line length at the decoder as a center in the two mats. As a result, since a current flowed to the power source voltage line of an integrated circuit or the ground line of a circuit is averaged, a noise level can be reduced.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor memory, for example, 0MO5 (complementary MO
S') Static RAM (Random access)
It is about effective technology that can be used for memory (memory).

[Background technology]

In a semiconductor memory, a relatively large load capacitance (parasitic capacitance II ) is required. Therefore, the output switching element is
In order to charge up or discharge the load capacitance, a relatively large current is caused to flow through the power supply line and the ground line of the circuit. A power supply voltage line Vcc in a semiconductor memory such as a RAM and a circuit ground line Vss each have non-negligible resistance and inductance, so relatively large noise is generated in each. In particular, noise on the ground line of the circuit causes deterioration of the level margin of the sense amplifier that amplifies the minute read signal from the memory cell and the input cover 77a that receives the address signal etc. supplied from the external terminal. Therefore, in a semiconductor integrated circuit device having multiple output circuits, such as a RAM that is accessed in units of multiple bits such as ×4 or ×8 bits, the above-mentioned noise level increases according to the number of output circuits. (For static RAMs that are accessed in units of multiple bits, see, for example, ``Hitachi IC Memory Data Book,'' published by Hitachi, September 1988, p. 103).

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory in which noise generation is reduced with a simple configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a memory mat M-ARYL and M-ARYR divided into two is arranged around the X address decoder, and each of the memory mats M-ARYL and M-ARYR is divided in the data line direction to form a plurality of memories. Among these memory arrays, the above
By providing a plurality of input circuits and output circuits in common for a pair of memory arrays arranged symmetrically around the address decoder, multiple bits can be generated using the difference in word line selection delay time and the read signal delay time. This is to output signals in time series.

〔Example〕

FIG. 1 shows a static type RA to which this invention is applied.
A block diagram of M is shown. This figure shows the internal configuration of a RAM with a storage capacity of approximately 64 bits and an output of 8 bits. Each of the main circuit blocks in the figure is drawn in an actual geometric arrangement and is formed on a single semiconductor substrate such as single crystal silicon using semiconductor integrated circuit technology.

In the static RAM of this embodiment, two memory mats M-ARYL and M-ARYR are formed on the left and right sides of the X address decoder XDCR. The respective memory mats M-ARYL and M-ARYR are
Each is 256 columns (rows) x 16 rows (columns) - 40
Eight matrices (memory arrays MO to M7) with a storage capacity of 964 bits (approximately 4 bits) are grown, resulting in a total storage capacity of approximately 64 bits. In this embodiment, in order to reduce the peak level of noise generated in the power supply line or the ground line of the circuit during the read operation, the two memory mats M-ARYL
, M-ARYR, each of the eight memory arrays MO to M7 is connected to the X address decoder XDC.
They are arranged symmetrically with R as the center. In other words, the memory arrays MO are arranged in order from the memory array located farthest from the X address decoder XDCR.

They are arranged like M1 to M7. As a result, the memory array M7 is arranged adjacent to the left and right sides of the X address decoder XDCR.

An address circuit for selecting a desired memory cell from each memory array MO to M7 having a plurality of memory cells is an address buffer ADB1. It is composed of ADB2, an X address decoder XDCR, a Y address decoder YDCR, column switches CW-L, CW-R, and the like. In the same figure,
Y address decoder YDCR and column switch CW-L
and CW-R together to form YDCR & CW-L and YDC
It is expressed as R&CW-R.

In the same figure, the memory mats M-ARYL and M-A
At the top of RYR are provided load circuits RLI and RL2 coupled to its data lines. Although not particularly limited, the far ends of the word lines in the memory mats M-ARYL and M-ARYR, in other words, the end opposite to the end of the word line coupled to the output terminal of the X address decoder , monitor circuits WLML and WLMR are provided, respectively, for detecting the selection level of the word line. The detection signals φL and φR formed by the monitor circuits WLML and WLMR are supplied to the timing control circuit C0.
The signal is supplied to the NT, where a timing signal such as a sense amplifier operation timing signal saC, which will be described next, is formed.

Signal circuits that handle reading/writing of information are not particularly limited, but include the memory mats M-A arranged on the left and right sides.
Sense amplifiers SAO to SA7 and SAO' to SA? are provided corresponding to the divided memory array MO-M7 in RYL and M-ARYR, respectively. ', and a data input/output circuit 00-107 consisting of a data input circuit and a data output circuit. Among these sense amplifiers, the corresponding sense amplifiers SAO and SAo
The outputs of o are commonly connected by an output line LO.

Other sense amplifiers are sense amplifiers SAI and SAI゛~S.
A7 and SA? They are commonly connected by output lines L1 to L7 as shown in '. As a result, sense amplifier SAO and S
The output line LO that commonly connects the outputs of AO' is made the longest, and the lengths of the output lines are made shorter in the order of the outputs IJI L1 to L7. Correspondingly, the parasitic capacitance is also reduced in order according to the length of the output line.

The timing circuit for controlling the information read/IF write operation is composed of a timing generation circuit TG that receives a chip selection signal CS, an output enable signal OE, and a write enable signal WE supplied from an external terminal.

256 decoded output signals obtained based on address signals AO to A7 are sent from the X address decoder X to the row-related address selection line (word line). This decode output signal is not particularly limited, but may be applied to the memory mats M-AR arranged on the left and right depending on the address signal A8.
For example, if the address signal A8 is at a low level, one word line out of 256 in the left memory mat M-ARYL is selected, and the right memory mat M-ARYL is selectively brought into a selected state. Matt M-A
All word lines of RYR are made unselected. Conversely, if the address signal 8 is at a high level, the right memory mat M-
One word line out of 256 in ARYR is selected, and all word lines in the left memory mat M-ARYL are rendered unselected. This can prevent the generation of meaningless current consumption flowing through the load circuit and memory cells in unselected memory mats.

The column system address selection line (column switch selection line) has 16 bits obtained based on address signals A9 to A12.
The decoded output signal is the Y address decoder YDCR.
Sent from In addition, the left and right memory mat M-ARY
Y address decoder YD provided on L and M-ARYR
CR selectively forms the 16 decoded output signals according to the address signal A8.

Address buffers ADB1 and ADB2 are connected to address signals AO to A8 and address signal A supplied from external terminals.
9 to A12, respectively, and form internal complementary address signals aO to a8 and a9 to a12 (not shown) consisting of an in-phase address signal and an opposite-phase address signal.

The internal complementary address signal formed by address buffer ADB1 is supplied to the X address decoder XDCR, and the internal complementary address signal formed by address buffer ADB2 is supplied to the Y address decoder Y.
Supplied to DCR.

Memory mats M-ARYL or M arranged on the left and right sides of the above
- Address signal AO from the outside among word lines W1 to W256 in each memory array MO to M7 of ARYR
One word line specified by the combination of ~A8 is selected by the above-mentioned X address decoder XDCR, and is selected by the above-mentioned Y address decoder YDCR-L or YD.
CR-R outputs address signals A9 to Al from the outside.
A pair of complementary data lines specified by a combination of 2 is selected from 16 pairs of complementary data lines. As a result, in each memory array MO to M7, one memory cell arranged at the intersection of the selected word line and the selected complementary data line is selected.

The storage information read from the selected memory cell is transmitted to a subcommon complementary data line SCD, which will be described later, provided for each memory array MO to M7.

Appears on SCD.

The purpose of providing sub-common complementary data lines SCD, STE) for each memory array MO-MA7 and providing sense amplifiers SAO-SAT (SAG'-SA7°) for each memory array is to Parasitic capacitance is reduced to speed up information read operations from memory cells and write operations to memory cells.

Sense amplifier 5A (l N5AT and SAO° ~ SAT
' is the operation timing signal of the sense amplifier formed by the timing generation circuit TG and the address signal A.
Memory mat M-ARYL or M selected according to 8
- activated according to ARYR. As a result, the sense amplifiers on the non-selected memory mat side are maintained in a non-operating state, thereby preventing the generation of meaningless current consumption.

The timing generation circuit TG receives three external control signals C5 (
In response to chip selection signal), WE (write enable signal), and 3 (output enable signal), an internal chip selection signal, a sense amplifier operation timing signal, a write control signal, a data input control signal, a data output control signal, etc., which will be described later, are generated. (not shown).

FIG. 2 shows a circuit diagram of an embodiment of the static RAM.

The MOSFET constituting the memory cell is of an N-channel type and is formed on a P-type level region formed on an N-type semiconductor substrate. A P-channel O5FET is formed on an N-type semiconductor substrate.

The P-type well region as the base gate of the N-channel MOSFET is coupled to the ground terminal of the circuit, and the N-type semiconductor substrate as the common base gate of the P-channel MOSFET is coupled to the power supply terminal of the circuit. Ru. Note that the configuration in which the MOSFETs constituting the memory cells are formed in the well region is effective in preventing erroneous inversion of stored information in the memory cells caused by α rays or the like.

The figure exemplarily shows a circuit diagram of one memory array MO out of the plurality of memory arrays M 0-M 7 provided in the memory mat M-ARYL.

This memory array MO is composed of a plurality of memory cells MC arranged in a matrix, word lines WO to Wn, and complementary data lines DO, ``i5'' 0 to DI, bottom 1.

Each of the memory cells MC has the same configuration as each other,
One specific circuit is shown as a representative of a memory MO5FET QI whose gate and drain are cross-wired to each other and whose source is coupled to the ground point GND of the circuit.
, Q2, and the above M0SFETQ1. It includes high resistances R1 and R2 made of polysilicon layers provided between the drain of Q2 and the power supply terminal Vcc. And the above MO5FETQ1. A transmission gate MO3FET Q3.Q2 is connected between the common connection point of Q2 and the complementary data lines Do, DO.
Q4 is provided. The gates of the transmission gates MO3FETQ3゜Q4, etc. of the memory cells arranged in the same row are commonly connected to the corresponding word lines WO, Wl, Wn, etc. shown as examples, respectively, and the gates of the transmission gates MO3FETQ3゜Q4, etc. of the memory cells arranged in the same row are commonly connected to the corresponding word lines WO, Wl, Wn, etc. The input/output terminals of are connected to a pair of illustratively shown corresponding complementary data (or bit) lines DO, Do and D, respectively.
1, Dl, etc.

In the memory cell, MO3FETs QI and Q2 and resistors R1 and R2 constitute a kind of flip-flop circuit, but the operating point in the information retention state is quite different from that of a flip-flop circuit in the ordinary sense. That is, in the memory cell MC, in order to reduce power consumption, the resistor R1 maintains the gate voltage of MO5FETQ2 at a voltage slightly higher than its threshold voltage when MO5FETQI is turned off. The resistance value is set to a significantly high value to the extent that it can be used.

Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistors R1 and R2 are made to have a high resistance enough to compensate for the drain leakage current of the MO3FETs QI and Q2. The resistors R1 and R2 have enough current supply capability to prevent information charges stored in the gate capacitance (not shown) of the MO3FET Q2 from being discharged.

According to this embodiment, although the RAM is manufactured by OMO3-fc technology, the memory cell MC is constructed from an N-thin channel MO5FET and a polysilicon resistance element as described above.

The memory cell and memory array of this embodiment are made of P-channel MOS F E instead of the polysilicon resistance element described above.
Compared to the case where T is used, the size can be made smaller. That is, when using a polysilicon resistor, the drive MO3F
It can be formed integrally with the gate electrode of ETQI or Q2, and its size can be reduced. And P
As when using the channel MO3FBT, the drive M
O3FETQ1. There is no need to separate it from Q2 by a relatively large distance, so no unnecessary blank space is created.

A pair of complementary data lines DO, D in the memory array
O, Di, DI are transmission gates MO8FETQIO, Q11, Q12 . Q1
The subcommon complementary data lines SCD and SCD are connected to each other via a column switch circuit composed of three subcommon complementary data lines SCD. These subcommon complementary data lines SCD, SCD are connected to an input terminal of a sense amplifier and an output terminal of a write amplifier, which will be described later.

MOSFETQ10, Q that constitutes the column switch circuit
ll and Q12. A selection signal formed by a Y address decoder YDCR is supplied to each gate of Q13. Although not shown, this Y address decoder Y-DCR is constituted by a NOR gate circuit or the like having a similar configuration.

Although not particularly limited, an equalizing MO3FET Q5 constituted by a P-channel MOS FET is provided between the complementary data lines Do and DO. A similar MO3FETQ6 is also provided between complementary data lines DI and DI, which are shown as other representative lines. An equalizing timing signal φeq is supplied to the gates of these equalizing MO3FETs Q5°Q6. This timing signal φeq is formed by an address signal change detection circuit (not shown). It should be understood that this address signal change detection circuit is included in the timing control circuit C0NT shown in FIG. This address signal change detection circuit detects a change in any one of the address '(words AO-A12) and sets the timing signal φeq to a low level for a relatively short period of time. MO3FBTQ5 and Q6 are turned on during the low level period of the timing signal φeq, and short-circuit the complementary data lines DO1DO, DI, DI, etc. to make their potentials equal to 0. As a result, the signal voltage of the previous operation cycle is Since it is reset, the operation speed can be increased.

Monitor circuit WLML for detecting word line selection level
is a P-channel type precharge MO3FETQ9 that receives the timing signal φeq, and word lines WO to W.
It is composed of N-channel discharge MO3FETs Q7 to Q8 whose far ends are coupled to the gates of n(W255), and a CMOS inverter circuit IVL as a level detection circuit. That is, during the period when the timing signal φeq is set to low level according to the change timing of the address signal, the P-channel MO5FETQ is turned on, and the junction capacitance it (not shown) of the commonly connected drains of the MO5FETs Q7 to Q8 is charged up. be done. Thereafter, when any one word line is selected and the voltage at its far end reaches the threshold voltage of MO5FET Q7 or Q8, the voltage charged up in the junction capacitance is discharged. When this discharge operation causes the voltage of the junction capacitance to become lower than the Rosinx reflex voltage of the CMOS inverter circuit IVI, this inverter circuit! (2) A pulse signal φL that changes from low level to high level is sent from the output of 1.

An equalizing MO3FET QI4 similar to the above is provided between the subcommon complementary data lines SCD and Sτ. In addition, each subcommon complementary data line SCD, SCD is connected to an N-channel type precharge MO3FETQI5.
．． Q26 precharges to a relatively high level. Timing signals φcd and φcd are formed based on the address signal change detection timing signal φeq. As a result, the subcommon complementary data line SCD, 57
The bristles are precharged to an equal relatively high voltage prior to their write or read operations.

The subcommon complementary data lines SCD, SCD are coupled to an input terminal of a sense amplifier SA, which will be described next.

Sense amplifier SA is composed of two sets of differential amplifier circuits. In other words, N-channel type differential MO3FETQ
25. A P-channel MOS FET Q20.Q26 in a current mirror configuration is connected to the drain of Q26. An active load circuit constituted by Q21 is provided. The gate of MO5FETQ25 as an inverting input in this differential amplifier circuit is coupled to one subcommon complementary data line SCD, and the gate of MO5FETQ26 as a noninverting input is coupled to the other subcommon complementary data line SCD.

Differential MO3FET Q27 similar to the above. Q28 and load M
O5FETQ23. Q24 constitutes a differential amplifier circuit similar to the above. The input terminal of this differential amplifier circuit is MO5FETQ27. The gate of Q2B is cross-coupled with the input terminal of the differential amplifier circuit. That is, the gate of MO5FETQ27 as an inverting input of this differential amplifier circuit is coupled to the other sub-common complementary data line SCD, and the gate of MO3FETQ2B as a non-inverting input is coupled to the one sub-common complementary data line SCD. be done.

Note that the output side MO5FETs Q20 and Q23 in the load circuit configured as a current mirror are each connected with a P-channel type precharge MO3FET Q19 in parallel configuration.
．． Q22 is provided. This MO3FETQ19. Q2
2 is connected to the sense amplifier SA by supplying the sense amplifier operation timing signal φsal to its gate.
The output line is precharged during the non-operation period.

Moreover, the timing signal φs is connected between this pair of output lines.
A P-channel MOSFET Q29 receiving the voltage A1 is provided to equalize the brinage level of the output line during the precharge operation. The two sets of differential amplifier circuits are supplied with operating current by an N-channel type power switch MO3FETQ38 provided between the common source of the differential amplifier MOSFETs Q25 to Q2B and the ground potential point of the circuit. The gate of this MO5FETQ3s has a sense amplifier operation timing signal φsa.
l is supplied. This timing signal φsal is generated only when the left memory mat M-ARYL is selected.

The output signal of this sense amplifier SA is transmitted to the input of an output circuit OB having a three-state output function.

The output circuit OB uses a pair of clocked inverter circuits. That is, P-channel MO3FETQ31
One output signal from the sense amplifier SA is commonly supplied to the gates of the and N-channel MO3FETQ32, and the source of the P-channel MO3FETQ31 is
Power supply voltage Vcc is supplied through the P-channel type switch MO3FETQ30, and the N-channel MO3FET
The source of Q32 is an N-channel type switch MO3F.
The ground potential of the circuit is supplied via ETQ32.

These switch MOSFETs are connected to the sense amplifier SA.
It can be operated in sync with. That is, P channel M
O3FETQ30. The inverted timing signal φsal is supplied to the gate of Q34, and the N-channel MO5
FETQ33. The gate of Q37 is supplied with the above-mentioned timing signal φsal, and the above-mentioned similar P-channel MO
3FETQ34. G35 and N-channel MOSFETQ
36°G37 constitutes an output circuit that receives the other output signal from the sense amplifier SA. Although not particularly limited, in this embodiment, the conductance of the N-channel MO3FETs Q32 and G36 in the CMOS inverter configuration is
By setting the conductance larger than that of ETQ31 and G35, the rosin threshold voltage thereof is made to have a relatively low level.

A pair of output terminals of this output circuit OB are connected to an output line (common complementary data line ) is coupled to LO.

This output line LO has a P-channel MO3FETQ40.
and N-channel MOSFET Q41.
MOS inverter circuit and P channel MO3FETQ
A latch circuit is provided in which the input and output of a CMOS inverter circuit constituted by 42 and an N-channel MO3FETQ43 are cross-coupled. These MO3FETQ
The conductances of 40 to Q43 are set relatively small, so that they are operated according to the signal voltage of the output line LO.

N-channel type switch MO5FE of this output circuit OB
TQ This output line LO is coupled to one input of NAND gate circuits G1 and 02 forming the data output circuit DOB.

These Nant gate circuits G1. The other input of G2 is supplied with an output timing signal doc.

The output signals of the Nant gate circuits Gl and G2 are transmitted through the CMOS inverter circuits IV2 and IV3, respectively, to the N-channel output MO5FETQ in a push-pull configuration.
This will be communicated to gates 44 and G45. Although not particularly limited, in order to secure the output current on the high level side, the output MOSFET Q44 is connected to a bipolar NPN transistor Tl in parallel form, the base of which is supplied with the output signal of the CMOS inverter circuit v2. provided. The output terminal of this output circuit is coupled to an external terminal DO.

As a writing circuit, a data input circuit DIB is provided, which is connected to the external terminal DO. This data input circuit is activated by a timing signal (not shown) in the write operation mode, and
A signal having the same phase as the write signal supplied from the external terminal DO and a signal having the opposite phase are formed and transmitted to the output line LO. Note that the data input circuit DIB is placed in an output high impedance state at times other than write operations.

In this embodiment, in order to speed up the write operation,
A write amplifier is provided in pair with the sense amplifier SA. That is, the write 7 amplifier WA is connected to the output line LO.
It receives the complementary write signal of , amplifies it, and transmits the output signal to the subcommon complementary data lines SCD and SCD via transmission gates MO3FETQI7 and G18. The timing signal φwe is formed based on the write enable signal WE, is set to a high level during a write operation, and is set to a high level during a write operation, and is set to a high level when the transmission gate MO3FETQ17. Turn on G18. As a result, the subcommon complementary data line S
A write signal is supplied to CD and C3D, and writing is performed to a memory cell whose word line is in a selected state via a column switch MOS FET and a complementary data line.

Next, an outline of the read operation will be explained with reference to the timing diagram shown in FIG.

When the chip selection signal C8 is set to a low level and one of the address signals Ai changes, an address signal change detection timing signal φeq is generated in synchronization with this. This causes the complementary data line DO.

Equalization is performed for 100, etc., and the subcommon complementary data lines SCD, SCD are precharged (not shown). Furthermore, since the monitor circuit is precharged, its output timing signal φL is set to low level.

By supplying the address signal, for example, a total of eight memory cells in the left memory muff) MARYL are selected, and their read signals appear on the subcommon complementary data lines SCD and SCD, respectively. This signal is amplified by sense amplifiers 5AO-3AT, which are activated by the high level of timing signal φsal.

Output signals VO to v7 of the sense amplifiers SAO to SA7
are precharged during the low level period of the timing signal φsal, and one level is lowered to the low level side by the amplification operation. This amplified output signal has a non-negligible resistance component and parasitic capacitance in the word line, so the word line of memory array M7 closest to the X address decoder The memory array M located farthest from the X address decoder XDCR
Since the O word line reaches the selection level the latest, the corresponding output signal 0 is the latest to obtain a low level signal.

The output circuit OB is activated at the same time as the sense amplifiers SAO to SA7, and since its logic threshold voltage is set to be shifted to the low level side, the output circuit OB is set to the low level from the sense amplifiers SAO to SA7. After the side output signal is made sufficiently low, a corresponding high level output signal is formed.

At this time, the data output circuit DOB is put into an operating state by setting its operation timing signal doc to a high level at a relatively early timing.

However, since the logic threshold voltage of the output circuit OB of each of the sense amplifiers SAO to SA7 is set relatively low, their outputs are both kept at a low level until a constant amplified output signal is obtained. As a result, the Nant gate circuit Gl of the data output circuit DOB,
The output signals of G2 both become high level and the output MOS
Both FETs Q44 and Q45 are turned off. This operation prevents a meaningless output signal from being sent out in accordance with the level of the output line remaining from the previous operation cycle when the timing signal doc rises to a high level. This prevents noise and wasteful current consumption, and enables high-speed operation because the true output signal according to the information stored in the selected memory cell can be output without being affected by the meaningless signal. can be achieved. Also, the timing signal do
Since c only needs to be slightly delayed from the operating timing of the sense amplifier, the timing can be easily set.

In the output circuit OB, since the wiring capacitance of the output lines LO to L7 varies according to the wiring length as described above, a signal through the output line L7 is transmitted to the data output circuit at a timing. As a result, each signal sent to the external terminals DO to D7 has the word line selection delay time difference in the memory mat M-ARYL added to the signal delay time difference in the output line LO-L7, and is sequentially transmitted from the external terminal D7. It will be output. of the output signal like this.

The output MO of each data output circuit is
Since the timing of the operating current of the S FET is shifted, the currents flowing through the power supply voltage line VCC of the semiconductor integrated circuit and the ground line of the circuit are averaged over time. Accordingly, the noise level generated in the power supply voltage line Vcc and the ground line of the circuit can be significantly reduced even though the output signal of x8 bits is sent to the external terminal as described above.

Note that the timing signal φsal is set to a low level by a signal delayed from the word line selection detection signal φL generated by the monitor circuit.

As a result, the sense amplifier 5A can be connected at a relatively early timing.
O-SA7 and its output circuit are rendered inactive. By making the output circuit inactive, the output line L
ONL7 is placed in a high impedance state, but since the output signal level is held by the latch circuit provided in the output line, it does not have any effect on the operation of the data output circuit L)OH. be able to.

〔effect〕

+II Two memory mats arranged on the left and right sides with the X address decoder as the center are divided according to the number of output bits, and addresses are assigned to the divided memory arrays symmetrically with the X address decoder as the center. As a result, the wiring length connecting the pair of memory arrays in the two memory mats is
ζ is made to differ according to the word line length centered on the address decoder. Therefore, in a multi-focus read operation, a multi-bit output signal is sent to an external terminal with a timing difference that is calculated by adding the time difference between word line selection operations and the signal delay time difference in the wiring connecting the memory arrays. Ru. As a result, the current flowing through the power supply voltage line of the semiconductor construction circuit or the circuit grounding line is averaged over time, and even though an output signal consisting of multiple bits is sent, the current flowing through the power supply voltage line or the circuit grounding line is This has the effect of reducing the noise level generated in the line.

(2) The arrangement of the above-mentioned memory array provides timing differences in the output signal consisting of multiple bits, and there is no need for timing control such as a special signal delay circuit, so it is possible to avoid complicating the circuit. You can get the effect that you can.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment described above, the memory cell may be constituted by a P-channel MO3FB"l" and an N-channel MO5F E'l'.

In addition, when obtaining a ×8-bit read signal, the total number of sense amplifiers is 81FM (c1 memory pin) M-
The pair of memory arrays ARYL and M-ARYR may be coupled by a common complementary data line.

Further, the specific circuit configuration of peripheral circuits such as a sense amplifier and an output circuit can take various embodiments.

[Application field]

In addition to the above-mentioned static type RAM, this invention also applies to various types of RO
It can be widely used in semiconductor memories that perform read operations in units of multiple bits, such as M (IJ-1ζ/only memory).

[Brief explanation of drawings]

FIG. 1 is a front diagram showing one embodiment of a static RAM according to the present invention. FIG. 2 is a circuit diagram showing one embodiment of the memory array and input/output circuit. FIG. 3 is a timing chart for explaining an example of the above. M-ARYL, M-ARYR...Memory mat, MO~
M7...Memory array, ADBI, At)B2...Address buffer, XL)CR...X address decoder, Y
LlCR&CW-L, Yl)CI(&CW-R...Y address decoder/column switch, SAO~SA7.S
AO'~SA7'...Sense amplifier, 100~1
07... Input/output circuit, RL 1°)? L2...Load circuit, WLML, WLMR...Monitor circuit, CON '1
'...Timing control circuit, '1゛G...Timing generation circuit 11 Figure 3 DOku 7

Claims (1)

[Claims] 1. Memory mats M-ARYL and M-ARYR are divided into two with the X address decoder as the center, and each of the memory mats M-ARYL and M-ARYR is divided in the data line direction. A plurality of memory arrays configured with A semiconductor memory 2 characterized in that it includes a plurality of output circuits, each of the memory arrays is provided with a sense amplifier, and the outputs of the sense amplifiers provided in the pair of memory arrays are shared. The semiconductor memory according to claim 1, wherein the semiconductor memory is connected to an input of an output circuit. 3. The semiconductor memory according to claim 1 or 2, wherein the semiconductor memory is a static RAM including a peripheral circuit formed by a CMOS circuit.