JPH03205695A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the operation speed by constituting each of first to third differential amplifying circuits of a pair of differential input elements and an asymmetrical load means which generates a current correspondingly to the current of one of the pair of differential input elements to generate an output corresponding to the difference between this current and the current of the other input element. CONSTITUTION:For the purpose of increasing the voltage gain of a sense amplifier SA, output signals Di and the inverse of Di from first and second asymmetrical differential amplifying circuits are applied to a third asymmetrical differential amplifying circuit consisting of MISFETs Q210 to Q214, and an output signal OUT is transmitted to an input/output terminal IN of a data output buffer DOB. Though the voltage difference between signals Di and the inverse of Di from a pair of common data lines CDL and the inverse of CDL is small in a certain degree, the sense amplifier SA can generate the output signal sufficient for driving of the data output buffer DOB. Thus, the operation speed of a static RAM (random access memory) is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to improvements in its sense amplifier.

Static random access memory (RAM)
Common data line pair CDL. The sense amplifier that amplifies the CDL signal and transmits it to the data output bathophore circuit uses an asymmetric differential amplifier circuit composed of a differential MISFET and a current mirror circuit (active load) as its load. Therefore, a current equal to the difference in drain current of the differential MISFET is obtained as an output signal, so this sense amplifier has a relatively high sensitivity, so if the input level difference from the common data illcDL and CDL is large, If the output voltage is too high, a predetermined output voltage cannot be obtained.

Furthermore, this sense amplifier has a drawback in that offset voltages generated due to variations in characteristics of the elements constituting the sense amplifier are transmitted as they are to the next stage. Furthermore, this sense amplifier is an asymmetric type that receives an input signal with a level difference between a pair of input signals and forms an output signal having a potential corresponding to the input signal level difference with respect to the ground potential of the circuit. The noise margin is also reduced due to the influence of the logic threshold voltage. From the above, when using the above sense amplifier, the level difference between the common data line pair CDL and CDL can be reduced to approximately 0.
It is necessary to increase the voltage to 5 volts, which becomes a major obstacle in achieving high-speed operation.

An object of the present invention is to provide a semiconductor memory device that operates at high speed.

Another object of the present invention is to provide a semiconductor memory device equipped with a highly sensitive sense amplifier that reduces variations in device characteristics and the effects of noise.

According to the present invention, the parallel type first and Sfr2 asymmetric differential amplifier circuits that receive signals from the common data line pair CDL and CDL and form output signals having opposite phases to each other are used as sense amplifiers.

Hereinafter, this invention will be explained in detail together with examples.

[Configuration and operation of static memory system] The configuration of the static memory system will be explained with reference to FIG. First, the block diagram surrounded by dotted lines shows a static memory system, and this system is
-RAM IC ARRAY (hereinafter referred to as S-RAM) and computer central processing unit (hereinafter referred to as CPU)
(not shown). ) and an S-RAM. E is a power supply circuit that theoretically represents the function of the bank anop, and normally the power supply E
. is working, but power supply E. When the auxiliary power source EB is turned off or breaks down, the auxiliary power source EB operates to retain the memory contents of the memory tip. In addition, the power supply V. . and VSS are common to all memory ICs.

Next, input/output signals between the static memory system and the CPU will be explained. First, address signal A. -Ak
is a signal for selecting addresses of 2k memory cells in the S-RAM surrounded by solid lines.

Among them, the address signal of A o "" A i is for each memory I.
Assigned as a common address signal to JIC,
The address signals of Al+l to Al( are assigned as selection signals for the m-column IC array, and are used as the chip select signal CS common to the ICs in each column. WE is a write enable signal, which is used to control the data in the S-RAM. These are read and write command signals, and are supplied to the WE terminals of all memory ICs. MS is a memory activation signal that starts the memory operation of S-RAM. D1 to D are the signals between the CPU and S-RAM.
This is input/output data on the data path connecting to the RAM.

Next, the static memory system will be explained separately into S-RAM and the above-mentioned interface circuit.

First, S-RAM has m nk-pit integrated circuits (hereinafter referred to as nk. Note that 1k bits indicates 2lO=1024 bits) arranged in columns and B pieces in rows.
) It consists of a C array connected in a matrix of words x B bits. Data input terminal Din and data output terminal D of the memory IJIC in each row of the IC array in row B. ut are commonly connected.

Next, the interface circuit will be explained. ADR is CPU
Address signal A sent from. -Ak is received, S-
R. This is an address receiver that converts into an address signal with timing suitable for AM operation.

DCR is a decoder that sends out a chip selection control signal (hereinafter referred to as CS1 to CSm, m=2) for selecting a chip of the S-RAM.

DBD is a data path driver in which data input/output between the CPU and S-RAM is switched by a gate control signal GC. Note that the gate control signal GC is generated by a logical combination of the write enable signal WE and the memory activation signal MS.

IC array data output D. 1 to DOB receive read output signals from the data output terminals of the ICs (B pieces) in the selected column, and the data inputs DI. ~DIB sends write data to the data input terminal Din of the ICs (B pieces) in the selected column.

Next, the function of the address signal within the Statinok memory system will be explained.

Address signal A from the CPU. S-Ak is divided into two systems, namely address signal Ao=Ai is S-R
°C is used as the address signal of the memory matrix in each chip of AM, and the address signals Ai+1 to Al (are S−R
From the AM chip's point of view, this is a tip selection signal indicating whether to select the entire chip.

[16k words x 1 bit S-RAM circuit configuration] 2nd
Figure A shows an S with a storage capacity of 16k bits and an output of 1 pit.
- The internal configuration of a RAM integrated circuit (hereinafter referred to as IC) is shown below.

Each 16k pit memory cell has 128 columns (rows).
x 32 rows (columns) = 4 matrices (memory array M-A
It is composed of RY1 to M-ARY4, and each matrix is arranged in two parts on the left and right sides of the row decoder R-DCH.

Row address selection m<hood line WL1-WL128
, WRI to WR128) are the address signal A. -A5
Based on 1AI2~A 13 (2 obtained by 2 = 2
56 types of decoded output signals are row decoder R-DCR
Sent from

In this way, the memory M-CEL of each matrix consists of one of the word lines WLI to WL128, WRI to WR128 and a complementary data line pair D11, DI1 to D, which will be explained later.
132, connected to one pair of D132 (・
Ru.

Address signals As and Aa are used to select only one of the four memory matrices. Address signals A7 to A1 are used to select one column in one selected memory matrix.

The memory matrix selection signal GS is the address signal A,
Based on ,A,(・decipher into four combinations.

Column decoders C-DCRI to C-DCR4 each perform 2 =
Provides 32 different decode output signals for column selection.

When reading (・Common data line pair CDL, CDL
is the common data line dividing transistor QllQ1:・
・・・・・・；Q. ,Q. ) is divided into four for each memory array, and the common data line pair CDL, CDL is commonly coupled at the time of writing.

Sense amplifiers SAI, SA2, SA3, and SA4 are provided corresponding to the divided common/data line pairs CDL and CDL, respectively.

In this way, the common data line pair CDL, CDL is divided,
Sense up/up SAI, SA2, SA3 respectively
, SA4 is provided for common data line pair CDL.
．． The objective is to divide the parasitic capacitance of the CDL and speed up the memory cell information read operation.

Address buffer ADB receives 14 external address signals A.

-14 pairs of complementary addresses each from A 1 2? signal a
. -a1■ and decoder circuit (R-DCR, C
-DCR,GS)K is sent.

The internal control signal generation circuit COM-GE receives two external control signals CS (chip select signal) and WE (write enable signal), and generates CSI (row decoder control signal),
SAC (sense amplifier control signal), we (write control signal), DOC (data output vanofer control signal), DI
C (data input cover sofa control signal), etc.

[16k words x 1 bit S-RAM circuit operation] 2nd
The circuit operation of the S-RAMIC shown in A will be explained with reference to the timing diagram in FIG. 2B.

All operations in this IC, namely address setting operations,
Read and write operations are performed using one external control signal CS.
is performed only during the low level period. At this time, if the other external control signal WE is at high level, a read operation is performed (
・If it is low level, write operation is performed.

First, address setting operation and read operation will be explained.

The advance setting operation is always performed based on the address signal applied during this period when the external control signal CS is at a low level. Conversely, by keeping the external control signal CS at a high level, address setting operations and read operations based on uncertain address signals can be prevented.

When the external control signal CS reaches the low level t, the row decoder R-DCR receives a high-level internal control signal CSI synchronized with this signal and starts operating. The row decoder (also word driver) R-DCR receives eight types of complementary pair address signals a. -a5, al2 to al3 are decoded, one hood line is selected, and this is driven to a high level.

On the other hand, four memory arrays M-ARY1 to M-ARY4
Among them (・One of them is the memory array selection signal m1 to m
4 and one selected memory array (
For example, x complementary data line pairs (M-ARYI) in
For example, Di 1 , DI 1 ) is connected to the column decoder (
For example, C-DCRI).

In this way, one memory cell is selected (address setting)
be done.

Information on a memory cell selected by the address setting operation is sent to one of the divided common data line pairs and amplified by a sense amplifier (for example, SAI).

In this case, four sense amplifiers SAI, SA2, SA3
, SA4 is selected by the memory array selection signals m1 to m4, and only the selected sense amplifier operates while receiving the high-level internal control signal SAC.

In this way, four sense amplifiers SAI, SA2, SA
3. Power consumption can be reduced by making the three sense amplifiers in the non-operating state.The outputs of the three sense amplifiers in the non-operating state are high impedance (floating). ) state.

The output signal of the sense amplifier is amplified by the data output vanofer DOB to output data D. It is sent to the outside of the IC as ut.

The data output bath sofa DOB operates for a period of time when it receives a high level control signal DOC.

Next, the write operation will be explained.

When the external control signal WE goes low level, a high level control signal we synchronized therewith is sent to the common data line dividing transistors (Q., Q.;...;Q.
, Q4), and the common data lines CDL, CDL are commonly coupled.

On the other hand, the data buffer DIR receives the low level control signal DIC, amplifies the input data signal Din from outside the IC, and sends it to the commonly coupled common data line pair CDL, CDL.

The input data signal on the common data line pair CDL, CDL is written into the memory cell M-CEL determined by the address setting operation.

[2k words x 8 bits S-RAM circuit configuration] 3rd A
The figure shows an S-2 with a storage capacity of 16k bits and an output of 8 bits.
The internal configuration of a RAM integrated circuit (hereinafter referred to as IC) is shown.

16k binoto memory cells each have 128 columns (rows)
x 16 rows (columns) = 8 matrices (memory array M-A
RYI to M-ARY8), and each matrix is arranged in four parts on the left and right sides of the row decoder R-DCH.

Row address selection lines (word lines WLI to WL128
, WRI to WR128) are the address signal A. -A,
2'=128 decoded output signals obtained based on the following are sent out from the row decoder R-DCR.

In this way, the memory M-CEL of each matrix is composed of one of the word lines WL1 to WL128, WRI to WR128, and one complementary data line pair D11, DI1 to
D132, D132 (•) is connected to one pair.

Note that the word line intermediate buffers MBI and MB2 have an amplifying effect in order to minimize the delay time at the ends of the word lines WLI to WL128 and WRI to WR128, respectively. It is placed between (・ru.

Address signals A7-A,. is used to select one column from each of the eight matrices above.

Column decoder C-DCR receives the above address signals A7-A.
Based on 1o(*2'=16 types of decode output signals for column selection are provided.

Address buffer ADB receives 11 external address signals A.

11 pairs of complementary address signals a from S-Al0, respectively.

-ale and decoder circuit (R-DCR, C-D
CR).

The internal control signal generation circuit COM-GE receives three external control signals CS (chip select signal), WE (write enable signal), and OE (output enable signal), and generates CSI (row decoder control signal), CS12 ( sense amplifier and data control signal), W-C
(write control signal), wc-o (data output buffer control signal), etc.

[2k hood x 8 binoto S-RAM circuit operation] 3rd A
The circuit operation of the S-RAMIC shown in the figure will be explained according to the timing diagram of FIG. 3B.

All operations in this IC, namely address setting operations,
The read and write operations are performed only while the external control i-cs is at the lock level. At this time, if the other external control signal WE is at a high level, a read operation is performed (., if it is at a low level, a write operation is performed.

The external control signal OE is used to control the output timing when sending the 8-bit output signal to the outside of the IC.

First, address setting operation and read operation will be explained.

When the external control signal CS is at a low level, the address setting operation is always performed based on the signal applied during this period.Conversely, by keeping the external control signal CS at a high level, Address setting operations and read operations based on address signals can be prevented.

When the external control signal CS becomes a low level, the row decoder R-DCR receives a high level internal control signal CSI synchronized with this signal and starts operating. The row decoder (also word driver) R-DCR receives seven types of complementary pair address signals a. -a, l are decoded to select a pair of left and right word boxes, which are driven to high level.

On the other hand, the column decoder C-DCR selects one column from each of the eight memory arrays M-ARY1 to M-ARY8.

In this way, one for each memory array, or a total of 8
One memory cell is selected (address set).

Information on the memory cell selected by the address setting operation is transmitted to the common data line pair CDL . CDL
and is amplified by each sense amplifier SA.

The sense amplifier SA operates while receiving a high level control signal CS12 synchronized with the external control signal CS.

The output signal of the sense amplifier SA is sent to the data output buffer DO.
Amplified by B, output data D. utl〜Dout
It is sent to the outside of the IC as 8.

The data output buffer DOB receives a high level control signal w"c"o and operates for a period of (.times.).

Next, the write operation will be explained.

When the external control signals WE and CS both become low level, a high level control signal W-c synchronized therewith is applied to the write control transistors (Ql, Ql;...
・；Q. ,Q. ) and each common data line pair CD
L, CDL and each data buffer DIB are coupled.

On the other hand, the data input vanofer DIB provided corresponding to each memory array amplifies eight input data signals Din1 to Din8 applied from the outside of the IC for a period of t after receiving the low level control signal CS12. , a common data line pair CDL provided corresponding to each memory array.
．． Send to CDL.

Each input data signal on the common data line pair is transmitted to eight memory cells M-C determined by the address setting operation.
Each is written to EL.

[Memory cell circuit]

FIG. 4 shows the circuit of a 1-bit memory cell M-CEL in the memory arrays of FIGS. 2A and 3A. This memory cell consists of series-connected negative field effect transistors)Q. ,Q. It consists of a flip-flop that cross-couples the input and output of a pair of inverter circuits, and a pair of transmission gate MISFETs Q3, Q. , the transmission gate has a flip-flop and a complementary data line pair D, D (D,,
,D. ,...D, , 2, L used as an address means to control the transmission of information between D, 3,
・The operation is performed by the word line W (WLI, . . . WL128, WL128, W
RI, . . . WR 128).

[Peripheral circuit]

FIG. 5 shows peripheral circuitry, such as the data output buffer DOB of FIGS. 2A and 3A. In this data output vanofer DOB, the control signal C. nt is logic “1” (“V
cc ), output ■. When ut reaches a logical value according to the input n and a very low output impedance is obtained, and when Cant is "O", Vout has no relation to the input In (becomes an undefined level, that is, very low). A high L output impedance can be obtained.In this way, a vanofa having both high and low output impedances enables wired-OR of a plurality of buffer outputs.

In the final stage, a bipolar transistor Q+os is used, which has a large drive capacity so that it can drive the load at high speed. Configure the Pnosheeple circuit (・ru.

Figure 6 shows the static type RAM (-) described above.
FIG. 2 is a circuit diagram showing an example of a sense amplifier SA.

In this example, the differential MISFETQ,. 1Q 2 0
! and an active load MISFET Q203 + that constitutes a current mirror circuit provided at each drain.
A first asymmetric differential amplifier circuit P1 composed of Qto* and M I S F E T Qzos ~Qv
The asymmetric differential amplifier circuit P configured by oa,
A second asymmetric differential amplifier circuit P2 having a configuration similar to that of
Common data line pair CDL. Signal Di from CDL
*Dt, and form output signals Di', / having mutually opposite phases. That is, the M I S which is the inverting input terminal (-) of the first and second asymmetric differential amplifier circuits P, P,
The gates of FETQ2oz and Qzoa are connected to the signal Di. Di- is applied. And MISFET Q2o+ + Q which is the non-inverting input terminal (+)
2. , are connected to the gates of signals Di, Di by cross-connection.
are applied respectively. In this embodiment, a MISFETQ constitutes a common constant current source for the first and second asymmetric differential amplifier circuits p, ,P. , is provided and L
・Ru. Instead of this MISFE T Qto-, each differential MI SFET Qzo+ + Qtot and Q2
05* An MISFET as a constant current source may be provided in the common source of Qtos.

In this embodiment, in order to increase the voltage gain in the sense amplifier, first and second asymmetric differential amplifier circuits P, .
The output signal DilDi' from P, is M I S F
E T Q21. ~ Q21, the third asymmetric differential amplifier circuit P1 and P having the same configuration as the above-mentioned asymmetric differential amplifier circuit P1 and P configured by
is applied to the asymmetric differential amplifier circuit P, ′″fit,・
Ru.

The output signal OUT (Di") from the third asymmetric differential amplifier circuit P3 is transmitted to the input/output terminal IN of the data output buffer DOB shown in FIG.

Moreover, MISFETQ2. as the constant current source. ,,Q
21, in the case of a divided sense amplifier as shown in FIG. 2A, the control signal SAC and the memory array selection signal m
Inverter circuits IV, IV 2 and H M receiving i
The switch is controlled by a control circuit CONT composed of I S F E T Q215 to Qt+a.

On the other hand, as in the embodiment shown in FIG. 3A, the signal CS12 as shown in FIG. and applied to the gate of QH4.

According to this embodiment, two asymmetric differential amplifier circuits P,
, P, to form balanced signals I (H, D, I). Therefore, even if the asymmetric differential amplifier circuits P, , P, have offset voltages, if they are formed in the same monolithic IC, the offset voltages described above will occur in the same way, so they can be canceled out. can be done.

Furthermore, even if nozzles that are in the same phase as the input signals Di and Di appear, these can be canceled out.

Furthermore, in order to increase the amplification factor, a similar asymmetric differential amplifier circuit P can be provided at the next stage.

Although the offset voltage of this asymmetric differential amplifier circuit P is transmitted to the next stage, it can be substantially ignored because the signal levels of the signals Di and DI' are large (.

As a result, it is possible to reduce the effects of offset voltage and noise, and to obtain a sense amplifier with high sensitivity and high amplification factor.

By the way, even if the voltage difference between the signals Di and Di from the common data line pair cDL and cDL is as small as about 0.2 volts,
The sense amplifier SA of this embodiment can generate an output signal sufficient to drive the data output buffer DOB, and the static RAM can operate at high speed.

Note that in the embodiment circuit of FIG. 6, the third asymmetric differential amplifier circuit P is omitted, and the signals D, /, Di are
It may also be transmitted to the data output buffer DOB in the next stage (in this case, the data output buffer DOB in Figure 5
In B, the inverter circuit G,0, is omitted and the signal D
, / , D , / are directly input to terminals T, , T1.

In this case, by using the balanced signals Di and Di' as the output signals, the amplification factor can be doubled compared to the case where one asymmetric differential amplifier circuit is used as described above. Then, as described above, the offset voltage and common mode noise can be canceled out.

FIG. 7 shows a bronch diagram of another embodiment of the invention.

In this embodiment, similar asymmetric differential amplifier circuits P,
, P, form a balanced signal D i' r D I'. Similar asymmetric differential amplifier circuits P4 and P
, to form balanced output signals OUT, OUT. Each asymmetric differential amplifier circuit P, , P, and P,
, P, is the same as the circuit shown in FIG. 6, so its explanation will be omitted.

The balanced output signals OUT, OUT are supplied to the inverter circuits G, OUT in the data output buffer DOB of FIG. , is omitted, and the gate circuit G,. ．． G. One input terminal T of 2
, ,T, are input directly.

In this embodiment, since the output signal is also a balanced signal, the offset voltage of the output side asymmetric differential amplifier circuits P, P can also be canceled out. Furthermore, the amplification factor can be increased to twice that of the embodiment circuit shown in FIG.

This allows for even more offset voltage and ? It is possible to reduce the influence of noise and obtain a sense amplifier with high sensitivity and high amplification factor.

FIG. 8 is a circuit diagram showing another specific embodiment of the asymmetric differential amplifier circuit P.

This example uses a differential MI SF ETQv+s −Q
t■.

As a load, MI SFETQ2 with its gate grounded
21 and these MI SF ETQz+- ,Qt
M I S F with the common drain of ■ connected to the gate
Consists of ET Q222. In this embodiment, since the voltage between the source and gate of the load MISFET Q222 can be increased, a higher amplification factor can be obtained than when using a current mirror circuit, but the offset voltage becomes larger. However, in configurations such as the asymmetric differential amplifier circuits P, , P, and P, , P, shown in FIGS. 6 and 7, (
- In this case, the offset voltage can be canceled out, so it does not become a problem and the high amplification factor can be utilized.

Figure 9 shows the asymmetric amplifier circuits P, , P of Figures 6 and 7.
A layout diagram when formed on a 2y monolithic IC is shown.

In the same figure, the thick and solid lines indicate aluminum wiring, and the power supply voltage vcc, ground GND line, and differential MISFET Qyo+, Qzo2,
and Q! Common source connection of OS + Qzoa, differential MIS
Used for common drain connection between FET and load MI SFET.

The thin solid line indicates a conductive polysilicon layer, which is used for the gate electrode of each MISFET and its associated wiring.

The dashed line indicates the p-type or n-type diffusion region, and the MISFET
It is used for cross-connecting the source or drain of a differential MISFET and the gate of a differential MISFET.

The dashed line indicates the p-type well region formed on the n-type substrate. Therefore, this P − We
An n-channel MISFET is formed in I1.

Also, the evil mark indicates contact.

This invention is not limited to the above embodiments.

The system configuration of the static RAM can take various embodiments.

[Brief explanation of drawings]

1 to 9 all show one embodiment of the present invention, FIG. 1 is a block diagram of a static memory system, FIG. 2A is a block diagram of the internal configuration of an S-RAMIC, and FIG. 2B is a block diagram of an internal configuration of an S-RAMIC. , its timing diagram, FIG. 3A is an internal configuration diagram of S-RAMIC showing another embodiment, FIG. 3B is its timing diagram, and FIG. 4 is a 1-pin memory cell in the memory array. 5 is a circuit diagram of a data output bath sofa, FIG. 6 is a circuit diagram of a sense amplifier, FIG. 7 is a prosock diagram of a sense amplifier showing another embodiment, and FIG. 8 is a circuit diagram of a data output bath sofa. FIG. 9 is a circuit diagram of an asymmetric differential amplifier circuit showing another embodiment used in the sense amplifier described above. FIG. 9 is a layout diagram of the main parts of the sense amplifier. DIC DinDATA VALID <WRITE CYCLE> 3rd <READ CYCLE> B Figure <WRITE CYCLE> Figure 4 Figure 6 Figure 7 Figure 8 Figure ○ mark” OUT

Claims (1)

[Claims] 1. A sense amplifier that receives a signal from the data line pair and outputs an amplified output signal for the signal to a first connection point; A semiconductor memory device comprising an output buffer having a pull-driven output transistor, wherein the sense amplifier receives signals from the data line pair at its pair of inputs and outputs an output signal of one phase. a second differential amplifier circuit that receives a signal from the pair of data lines at its pair of inputs and forms a signal with a phase opposite to the output signal; The first to third differential amplifier circuits each include a pair of differential input elements and a third differential amplifier circuit that receives the output signals of mutually opposite phases of the two differential amplifier circuits at its pair of inputs. , an asymmetric load means for forming a current in response to a current in one input element of the differential input element and forming an output in accordance with a difference between the current in the other input element of the differential input element and the current in the other input element. A semiconductor memory device characterized by: 2. The differential input element is a first conductivity type differential MISFE.
T, and the asymmetric load means includes the differential MISF
Claim 1, characterized in that the current mirror load circuit is comprised of a current mirror load circuit which receives the drain current of one of the MISFETs as an input and forms an output to be combined with the output of the other differential MISFET. semiconductor storage device. 3. The output buffer includes a gate circuit that receives a signal supplied via the first connection point and an output control signal, and the signal output state is determined by the output control signal;
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to take an output high impedance state. 4. The first to third differential amplifier circuits are connected in series with a current source controlled by a control signal conditioned on a chip select signal, so that the operating current is controlled. A semiconductor memory device according to any one of claims 1 to 3.