JPS6028099A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase a reading speed by using a push-pull type output circuit. CONSTITUTION:When memory information is read out, a bias voltage is applied to a memory cell of an array M-ARY selected by address decoders X-DCR and Y-DCR via a limiter MOSFETQ13. Then a common data line CD is set at a comparatively high level by the Q13 in case a selected memory cell is turned off regardless of the selection level of a word line. While the line CD is set at a comparatively low level in case the selected memory cell is turned on by the selection level of the word line. Both high and low levels of the line CD are limited to increase the reading speed.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, for example, an FA
MO3 (Floating avalanche injection MO5FETi insulated gate field effect transistor)
The present invention relates to a technology that is effective for EPROM (Electrically Programmable Read Only Memory) devices that use semiconductor devices such as the above as storage elements (memory cells).

[Background technology]

A semiconductor element such as FAMO3 (Floating Avalanche Injection MO3FET) is used as a memory element (
EPROM device (memory cell) is disclosed in Japanese Unexamined Patent Publication No. 57-1
It is disclosed in Japanese Patent No. 92067 and is well known.

The inventors of the present application have developed a circuit as shown in FIG. 1 as an address decoder circuit for an EFROM device using the above-mentioned FAMOS transistor as a storage element.

This address decoder X-DCR is divided into three parts. That is, the address decoder X-DCR is composed of address decoder sections DCRI to DCR3.

The address decoder section DCR3 is composed of a plurality of unit circuits having an N0R-AND function. That is, the unit circuit substantially performs NO between a plurality of address signals.
An R logical operation is performed, and an AND logical operation is performed between the logical operation result and the output signal of the address decoder section DCR1 to form an output signal. As a representative of a specific circuit,
One unit circuit is shown in the figure. This unit circuit consists of a depletion type load MO3FETQ as shown in the figure.
22, enhancement type drive MO3FETs Q23 to Q26 whose respective gates are supplied with internal address signals a6 to a8 of the upper three bits and an output signal 71 of the address decoder section DCRI to be described next, the load MO3FET Q22 and the power supply voltage Vcc. and an enhancement type power switch MO5FETQ21, which is provided between the address decoder section DCR1 and the gate thereof is supplied with the output signal dcrl of the address decoder section DCR1. Although not particularly limited, this unit circuit corresponds to four word lines, and in this embodiment, 256 word lines are formed, although not particularly limited. Therefore, in this embodiment, 64 unit circuits are prepared. The above power switch MO5FETQ21 is
It is formed to have a low threshold voltage in order to increase the high level of the output signal.

The remaining 63 unit circuits not shown in the figure also have the same configuration as the above-mentioned unit circuits.

However, the supplied address signal and/or the output signal supplied from the address decoder section are different. In this way, in the integrated circuit device, the address decoder section DCR can be used without restricting the word line pitch (interval).
3 unit circuits can be arranged. That is, there is no need to reduce the degree of stacking of the plurality of storage elements in the memory array MARY.

The address decoder section DCR1 is composed of a plurality of unit circuits having an N0R-AND function. That is,
The unit circuit substantially performs a NOR logical operation between a plurality of address signals, and further performs A between the result and the control signal ce.
An ND logic operation is performed to form an output signal. Note that only one unit circuit is shown in the figure. The unit circuits of the address decoder section DCR1 are supplied with internal address signals a1 to a3 of the lower three bits and a control signal co. The address decoder section DCR,1 includes eight unit circuits so as to decode each of the eight states indicated by the 3-bit address signal. In other words, the address decoder section DCR1 forms an output signal capable of performing 1/B selection. Note that the eight unit circuits forming the address decoder section DCR1 have the same configuration. However, the types of address signals supplied are different. The control signal ce is a signal formed based on the chip enable signal CE, etc., and is set to high level when selecting a chip.
Set to low level when chip is not selected or selected.

The output signals dcrl+dcrl of the unit circuits of the address decoder section DCR1 are respectively supplied to eight unit circuits in the address decoder sections DC and R3.

With the above configuration, the output signal dcr3 of one unit circuit in the address decoder section DCR3 is set to high level only when the 6-bit address signal is set to a predetermined level state. For example, among the output signals of the 64 unit circuits in the address decoder section DCR3, only one corresponding to the state of the 6-bit address signal supplied to the address decoder sections DCR1 and DCR3 is set to high level.

The output signal dcr3 of one unit circuit in the address decoder section DCR3 is transmitted through an enhancement type transmission gate (MO3FETQ) which corresponds one-to-one to each word line.
27. Q29. It is commonly transmitted to one electrode (source or drain) of Q31 and Q33. The output signal dcr2 of the address decoder section DCR2 is applied to the gates of these MO3FETQ27 and the like.

This address decoder section DCR2 receives 2-bit address signals a4, . 4 of the unit circuit that decodes a5
Consists of individuals.

Above transmission game) MO3FETQ27. Q29°Q31 and Q33 are alternatively turned on by an output signal supplied from the address decoder section DCR2. Therefore, one output signal of the address decoder section DCR2 is transmitted to the four transmission gates I.MO3FETQ27. Q29. Q
The other electrode of each of 31 and Q33 (word line side)
is transmitted to one of the

Above enhancement type transmission game) MO3FETQ27
．． Q29. Enhancement type MO3FETs Q2B, Q30, Q32 and Q34 are provided between the respective output sides of Q31 and Q33 and the ground potential terminal (GND) of the circuit. These MO3FETQ2B, Q30. Q32
The output signal i2 of the corresponding address decoder section DCR2 is applied to each gate of Q34.

Furthermore, the transmission gate MO3FETQ27. Q29, Q
A depletion type transmission gate MO3F is connected between the other electrode of each of Q31 and Q33 and the word line selection output terminal to which the corresponding word lines W1 to W4, etc. are connected.
ETQ35 to Q38 are provided respectively. A write control signal i is commonly applied to the gates of these MO3FETs Q35 to Q3B. This write control signal 71 is a signal formed in addition to the program signal PRG, etc., and is set to a low level during a write operation, and set to a high level during a read operation. A depletion type MO3 as a high resistance load is connected between the word line selection output terminal and the write high voltage terminal Vpfl.
FETs Q40 to Q43 are provided.

In such an address decoder circuit, since a drive current is supplied from the load MO3FETQ22 to raise a selected word line to a high level, a problem arises in that the rise speed of the word line is slow. In particular, when word lines are formed long to increase storage capacity, the parasitic capacitance value increases, resulting in slow access time.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that achieves high-speed read operation.

Another object of the present invention is to provide a semiconductor memory device including an address decoder circuit suitable for increasing storage capacity.

The above and other objects and novel features of this invention include:
It will become clear from the description in this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, as an output circuit of the address decoder circuit, an input including a series drive MOS FET provided on the ground potential side that receives the output signals of the first and second address decoder circuits that receive the divided address signals, respectively. a series output MOSFET provided on the power supply voltage side that receives the output signals of the stage circuit and the first and second address decoder circuits, and an output on the ground potential side that receives the output signal of the input stage circuit; MO3FET
The drive capability is increased by using a push-pull output circuit consisting of the following.

[Embodiment 1] FIG. 2 shows a circuit diagram of an embodiment of a memory array section when the present invention is applied to an EPROM.

Each circuit element in the figure is formed on a semiconductor substrate such as silicon by a known MO3 semiconductor integrated circuit manufacturing technique.

In the EPROM device of this embodiment, a complementary address signal formed through an address buffer receiving an address signal supplied from an external terminal (not shown) is sent to an address decoder X.
-DCR, Y-DCR.

Address decoder X-DCR forms a selection signal for word line W of memory array M-ARY according to its complementary address signal.

Address decoder Y-DCR forms a selection signal for data line 1 of memory array M-ARY according to its complementary address signal.

The memory array M-ARY includes a plurality of FAMOS transistors (nonvolatile memory elements: MO3FETQI-Q6) shown as a representative, a word line Wl,
W2 and data lines D1 to Dn.

In the memory array M-ARY, FAMO3I transistors Q1 to Q3 (Q4 to Q6
) are connected to the corresponding word line W2 (Wl>), and the FAMO gates arranged in the same column are connected to the corresponding word line W2 (Wl>).
3) Transistor Ql.

Q4-Q3. The drain of Q6 is connected to the corresponding data 1jlD1 to Dn, respectively.

And the common source line C of the above FAMO3) transistors
Although not particularly limited, S is grounded via a depletion type MOS FETQlo that receives the write signal We. Further, each of the data lines D1 to Dn is connected to a common data line CD via column selection switches MO3FETQ7 to Q9.

This common data line CD is connected to an output terminal of a data cover sofa DIB for writing which receives a write signal inputted from an external terminal I10.

In addition, the level limiter circuit described below and the amplification MOS FETQ15 provided in this level limiter circuit
A sense amplifier SA that receives an output signal through the sense amplifier SA, and a data output cover sofa DOB that receives the amplified output of the sense amplifier SA are provided.

The level limiter circuit has the following circuit configuration, although it is not particularly limited. Series type depletion QMO3FETQI 1 and enhancement type MO5F
ETQ12 divides the power supply voltage Vcc to form a predetermined intermediate level according to its conductance ratio. The intermediate level formed by the above MO3FETQ11 and Ql2 is MO3FETQI3 for limiter and MO8F for amplification.
Applied to the gate of ETQ15. These MO3FE
TQ13 and MOS FET Q 15 (7)
Thor 7. For example, both are connected to the common data ljl CD. The drain of the MOSFETQ 13 is connected to the power supply voltage Vcc, and the drain of the MOSFETQ 13 is connected to the power supply voltage Vcc.
The drain of TQI 5 is the load MOS F F', TQ
It is connected to the power supply voltage Vcc via 14. In addition, the intermediate level bariasumi pressure VB formed by the circuit similar to the above MO5FETQ11 and Ql2 is the MO3FETQ
1 [applied to the gate of i. This MO3FET01
The source of No. 6 is grounded, and the drain thereof is connected to the common data line CD.

When reading information stored in a memory cell, a bias voltage is applied to the memory cell selected by the address 1 coders X-DCR and Y-DCR via the MOS FETQ13. The selected memory cell is
According to the write data, for the word line selection level,
It has either a high threshold voltage or a low threshold voltage.

If the selected memory cell is turned off regardless of the word line selection level, the common data line CD is
MO3FETQI 3 makes it relatively high level. On the other hand, if the selected memory cell is turned on by the word line selection level, the common data line CD
is set to a relatively low level. In this case, the high level of the common data line CD means that the gate voltage of MO5FETQI3 is the same as the MO3FETQI1. According to the conductance ratio of Ql 2, it is brought to a relatively low level by being relatively low.

The low level of the common data line CD is MO3FETQ13.
and MO5FETQI 5 and MO constituting the memory cell.
A relatively high level can be achieved by appropriately setting the size ratio with the SFET.

By restricting the high level and low level of the common data line CD, it is possible to speed up reading even though the common data line CD has a capacitance such as a stray capacitance that limits the speed of signal change. I can do it. That is,
When data is read out from a plurality of memory cells one after another, the time required for one level of the common data line CD to change to the other level can be shortened.

Note that the MO3FET QI 5 for amplification performs an amplification operation of the gate-grounded source input, and transmits its output to the sense amplifier SA constituted by the next-stage differential amplifier circuit. The output of this sense amplifier SA is sent from the external terminal I10 via the data buffer DOB.

The control circuit C0NT is a chip enable signal supplied to external terminals GE, O main 2 RG and vpp.

Depending on the output enable signal, program signal, and high voltage for writing, internal control signals ce and we, which will be described later, are activated.
form etc.

FIG. 3 shows a circuit diagram of a specific embodiment of the address decoder X-DCH.

In this embodiment, although not particularly limited, the address signal is divided into two parts and input to two address decoder sections, respectively. That is, one address decoder section has drive MO3FETs that receive address signals %ai and ai, respectively.
Q51. Q53 and a dibension type MO5FET Q50 as its load means. The signal is input to an inverter circuit configured with Q52. Then, other address signals ai+1 to aj are connected between the output terminals of these inverter circuits.
M-O8 FETs Q54-Q55 are provided in a bridge configuration.

The output signal obtained from one of the inverter circuits as one address decoder section is supplied to the next push-pull type output circuit in order to increase its driving capability. In other words, one-way MO3FETs arranged in series
This will be communicated to the gate of Q57. The other drive MO3FET
The gate of Q5B is supplied with an output signal dcrl generated by the other address decoder section, such as the address decoder section DCR1 shown in FIG. These driving MO
3FETQ57. A depletion type MO3FET Q56 is provided as a load of Q58, forming an input stage circuit.

The output signals of the above two address decoder sections are connected to power supply voltage side output MOS FETs Q59 and Q6 which are connected in series.
By supplying the output signal of the input stage circuit to the gate of the output MOS FETQ61 on the ground potential side, a so-called inverted push-pull output circuit is constructed. In this embodiment, although not particularly limited, the MO3FETQ59 is provided with a parallel depletion type MO5FETQ62,
Its driving ability is improved and level loss is reduced.

The output signal of this push-pull output circuit is transmitted via the word line Wn
can be conveyed to. This word line Wn is provided with the depletion type MO3FET Q65 as described above, and forms the word line high level during writing.

A push-pull output circuit PP similar to the above is also provided for the output obtained from the other inverter circuit constituting the one address decoder section, and forms a selection signal for the word line wn+l.

Next, the operation of this embodiment circuit will be explained.

Now, if address signals al to aJ are all low level, M
O3FETQ51. Q54 and Q55 are turned off. In this case, due to the high level of address signal ii,
MO3FETQ53 turns on and its output becomes low level, but the bridge type MO3FETQ
54 and Q55 are in the off state, the output signal of one inverter circuit becomes high level and MO3FETQ
57, Q59 is turned on. Furthermore, if the output signal dcrl formed by the other address decoder section is at a high level, MO3FETQ58. Q60 is turned off.

Therefore, the drive MO3FETQ57 of the input stage circuit
．． Due to the on state of Q58, its output signal becomes low level, so the output MO3FET Q61 on the ground potential side becomes off state.

And the above power supply voltage side output MO3FETQ59゜Q6
0 is in the ON state, the output (No. 8) forms a high-level selection signal. In the read operation, since the control signal 71 is at a high level, the word is transmitted through the depletion type transmission gate MO8FETQ63. Lines W and n are set to a high level selection state.

Furthermore, when the output signal dcrl formed by the other address decoder section is at a low level, the MO3FETQ58 is turned off, so the output signal of the input stage circuit becomes high level, turning on the ground potential side output MO3FETQ61. Furthermore, the low level of the output signal dc r 1 turns off the power supply voltage side output MO3FET Q60, so the output signal becomes low level (non-selected).

In this way, a pair of complementary address signals a1. Since the output of one of the pair of inverter circuits becomes low level according to the τ ball, the bridge type MOS F
If even one of the ETs is turned on, a low level non-selection signal is generated.

Also, the chip enable signal CE is set to high level,
When the chip is in a non-selected state, the control signal ce generated based on the chip enable signal CB becomes low level, and therefore the output signal dcrl becomes low level. As a result, MO5FETQ5B, Q60, etc. are turned off, so the word line is
Depending on the number 1, etc., it is brought to the ground potential. That is, in the chip non-selected state, the potential of each word line is set to the ground potential. This makes it possible to prevent undesired writing or reading from memory cells.

[Example 2] 4th Ff! J shows an embodiment of a decoder circuit to which the present invention is applied.

In the figure, DCR1° to DCR3' are address decoders DCR1 to DCR3' shown in FIG. 1, respectively.
This is an address decoder section having a configuration similar to that of DCR3. Also, Q27° ~ Q38' and Q40° ~ Q43°
, are the MO3FETs shown in FIG. 1 above, respectively.
These are MOSFETs that function similarly to Q27 to Q3B and Q40 to Q43. In this embodiment, the respective output signals of the address decoders DCR1' and DCR3'' are supplied to push-pull output circuits described below. ' For each one output signal, the address decoder section DCR2°
In fact, only one pair of output signals is shown in the figure.

The above push and nibble output circuit is of depression type M
o5FET, 0.5 s° and enhancement type MO
It is composed of 3FETs Q57'' to Q61°.

The address decoder section DCR3'' receives the address signal a.
For example, when all of 6 to a8 are a combination of low level, output signal of C/f level)405FETQ57'',
For other combinations, low level output signals are sent to MO5FETQ57' and Q60'.
Send to. When the address signals a1 to a3 are all low level and the control signal ce is high level, the address decoder unit DCR1' sends out a high level output signal to MO3FETQ58° and Q59', and outputs a high level output signal to MO3FETQ58° and Q59', and At this time, a low level output signal is sent to MO3FETQ58'' and Q59°.

Further, the address decoder section DCR2' receives the address signal a4. When a5 are both low level, a high level output signal is sent to MO3FETQ27', and a low level output signal is sent to MO3FETQ27'.
28°, and for other combinations, a high level output signal is sent to MO3FETQ28''.

When the chip is selected, the control signal ce becomes high level. In this state, address signal al-a
When all ll are set to low level, MO3FETQ59' and Q60'' are turned on and MO3FETQ61° is turned off by the respective output signals of the address decoder sections DCRI' and DCR3°. MO3FETQ27'' is turned on by the output signal of address decoder section DCR2'. Therefore, for read operation, MO3FE
A current is supplied to the word line W1 through TQ59°, Q60°, Q27' and Q35°, and the word line W1 is set to a high level (selective state h5>).

Furthermore, in the case of a write operation, MOSFETQ35° is in the off state, so the word line W] is set to MO3FETQ40.
The voltage rises to the high voltage potential VGlf). In addition, during a read operation or a write operation, the remaining word lines W2 to W4 are turned on by MO3FETs Q30', Q32'' and Q34' which are turned on by another high level output signal formed in the address decoder section DCR2°. is set to ground potential (non-selected state).

In this embodiment, only one push-pull output circuit needs to be provided for four word lines, so the number of elements in the decoder circuit can be reduced and the layout can be simplified. In addition, the address decoder section DCR1'' does not need to generate an inverted signal. Also, since the control signal ce generated based on the chip selection signal CE is taken into the decoder circuit, the chip is not selected. In other words, when the chip is not selected, the address decoder unit DCRI'
Since all the output signals of the MOSFE are low level, the MOSFE
TQ61'' etc. are turned on, and all unselected word lines are brought to the ground potential.

Therefore, it is possible to prevent undesired writing or reading.

〔effect〕

(1) By using a push-pull output circuit as an address decoder circuit, its driving capability can be increased, which has the effect of increasing the rise and fall speed of the word line selection level. .

(2) As described in (1) above, the driving ability of the word line is improved, so that it is possible to achieve the effect of achieving a large storage capacity, such as a storage capacity of about 256 bits, and high-speed operation.

(3) Bridge-type M as an address decoder circuit
OSFETQ54. When Q55 etc. are used, in the address decoder section regarding a pair of adjacent word lines,
Since the MOSFETs configuring the logic block can be shared, it is possible to reduce the number of elements.

(4) The output circuit is different from a simple 1f-number push-pull output circuit, and has a logic function, and furthermore, the output signal formed by the other address decoder section is
Since there is only the phase signal t)dcrl, it is possible to simplify the circuit configuration and reduce the number of signal lines.

(5) By the synergistic effect of (3) and (4) above, it is possible to achieve the effect of realizing a high degree of integration of the EFROM.

(6) When a chip is not selected, all word lines are set to a non-selection potential (for example, the ground potential), so that an undesired operation can be prevented.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the address decoder section is the address decoder section DCRI-D in FIG.
It is also possible to use CR3 and replace its output circuit with a push-pull output circuit as shown in FIG. 3 above. In this case, the address decoder unit DCRI does not use the inverted signal dcrl as described above. Further, the push-pull output circuit shown in FIG. 3 may be replaced with the push-pull output circuit shown in FIG.

[Application field]

The present invention is a dynamic RAM (random access memory) composed of MOSFETs.

It can be widely used in semiconductor memory devices having a word line or data line selection circuit, such as static RAM and iROM.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of an address decoder circuit previously developed by the inventor of the present application, and FIG. 2 is a block diagram showing an embodiment in which the present invention is applied to an EP ROM device. Figure 3 shows the address decoder X-D.
A circuit diagram showing a specific embodiment of the CH. FIG. 4 is a circuit diagram showing another embodiment of the address decoder X-DCH. X-DCR, Y-DCR...Address decoder, M-
A RY... Noso Rear Array, SA... Sense Amplifier, D
IB...Data buffer sofa, DOB...Data output buffer, DCR1 to DCR3...Address decoder section Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. Ca

Claims (1)

[Claims] 1. The first . a second address decoder section; and the first address decoder section. An input stage circuit including a series drive MO3FET provided on the ground potential side receiving the output signal of the second address decoder section, and the first. A series output MO3 provided on the power supply voltage side receiving the output signals of the second address decoder section.
1. A semiconductor memory device comprising an address decoder circuit configured with a push-pull output circuit consisting of an FET and an output MO3FET on the ground potential side that receives an output signal of the input stage circuit. 2. The semiconductor memory device according to claim 1, wherein the address decoder circuit forms a word line selection signal. 3. A depletion type MO3FET to which an internal write control signal is applied is provided between the output terminal of the push-pull output circuit and the word line, and a load means is provided between the word line and the high voltage terminal for writing. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory element is a FAMO3) transistor.