JPS59198595A - Eprom device - Google Patents

Abstract

PURPOSE:To reduce a leak current at a non-selecting word line without losing a write speed by applying a write high voltage to the load means of a word line only at write operation by means of a switch MOSFET and boosting a gate voltage with a bootstrap circuit utilizing a write control signal. CONSTITUTION:At write operation, a high voltage is applied to a high voltage terminal Vpp, the write control signal we is brought into a low level, MOSFETs Q45, Q47 are turned off and the gate voltage of an MOSFETQ50 goes to a high level such as Vpp-2Vth through MOSFETQ48, 49. On the other hand, since an MOSFETQ59 is turned on while a delay signal we' is changed to a low level, a bootsrrap capacitor CB is charged up to a high level according to the gate voltage of the MOSFETQ50. Since the gate voltage of the MOSFETQ50 is brought into a high voltage being over the high voltage Vpp through the bootstrap operation, a high voltage Vpp' almost equal to the high voltage Vpp is applied to a depletion MOSFETQ40 or the like being a load.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to an EPROM (Electrically Programmable Read Only Memory) device composed of MOSFETs (Insulated Gate Field Effect Transistors), such as FAMQS ( EPR that uses semiconductor elements such as floating avalanche injection MO3FETs as memory elements (memory cells)
The present invention relates to technology effective for OM devices.

[Background technology]

EPROM devices that use semiconductor elements such as FAMQS (floating avalanche injection MOS FET) as storage elements (memory cells) are known.

In a conventional EPROM device, a depletion type MO3 is connected between the write high voltage terminal (VpI) and the word line.
A high resistance load made up of FETs is provided to apply a high voltage vpp to a selected word line. However, in the read operation, 5V is applied to the high voltage terminal Vpp.
Since such a voltage is supplied, a leakage current of about 5 μA to 6 μA flows between the high resistance load and the X address decoder in unselected word lines. In particular, in an EPROM device with a large storage capacity such as 256 bits, the leakage current is 10% in total.
This results in a large current value exceeding mA.

Therefore, it is conceivable to supply the high voltage vpp to the high resistance load means only during the write operation via the switch MO3FET. However, in this case, switch MO3
Since the write voltage of the selected word line is reduced by the threshold voltage of the FET, a problem arises in that the write speed becomes slow.

[Purpose of the invention]

An object of the present invention is to provide an EPROM that reduces leakage current in unselected word lines without impairing write speed.
The goal is to provide equipment.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the switch MO3FET, which is turned on by the write control signal, supplies the write high voltage vpp to the word line load means only during the write operation, and the gate voltage is controlled by the bootstrap circuit using the write control signal. It boosts the pressure.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a memory array section when the present invention is applied to an EPROM.

Each circuit element shown in the figure is formed on a semiconductor substrate such as silicon by a known MO8 semiconductor integrated circuit manufacturing technique.

In the EPROM device shown in the figure, an external address signal is supplied from an external terminal (not shown) to an address buffer (not shown). The address buffer forms a complementary pair of address signals (an address signal corresponding to an external address signal and an address signal whose phase is inverted with respect to the address signal) and sends it to the address decoders X-DCR and Y-DCR.
supply to.

Address decoder X-DCR decodes word line W in memory array M-ARY according to its complementary pair address signal.
form a selection signal.

Address decoder Y-DCR forms a selection signal for the data line of memory array M-ARY according to its complementary pair address signal.

The memory array M-ARY is composed of a plurality of FAMO transistors, a word line, and a data line.

The figure shows multiple FAMO3) transistors (non-volatile memory elements...MO3FETQI to Q6) as representatives.
and word line Wl.

W2 and data lines D1-Dn are shown.

In the above memory array M-ARY, FAMO3) transistors Q1 to Q3 (Q4 to Q6) arranged in the same row.
The control gates of the respective word lines W
FAM connected to l (W2) and placed in the same column
OS transistor Ql.

Q4-Q3. The drains of Q6 are connected to corresponding data lines D1 to Dn, respectively.

The sources of each of the FAMO3I- transistors are coupled to a common source line C8.

Although not particularly limited, in this embodiment, a depletion type MO3FETQIO receiving the write signal ye
The common source line CS is grounded via the common source line CS. Further, each of the data lines D1 to Dn is connected to a common data line CD via column selection switches MO3FETQ7 to Q9.

This common data line CD is connected to an output terminal of a data cover sofa DIB for writing which receives a write signal inputted from an external terminal I10.

Also, a level limiter circuit to be described next, a sense amplifier SA that receives an output signal through the amplification MO3FET Q15 provided in this level limiter circuit, and a data output buffer DO that receives the amplified output of this sense amplifier SA.
B is provided.

The level limiter circuit has the following circuit configuration, although it is not particularly limited. Depression type MO3FETQ11 and enhancement type MO3F in series
ETQI 2 is determined by dividing the power supply voltage Vcc according to its conductance ratio.

form an intermediate level. Above MO3FETQ11,Q
The intermediate level formed by l2 is MO3FE for limiter.
It is applied to TQI 3 and the gate of MO3FETQ15 for amplification. These MO3FETQ13 and MO3FE
The sources of TQI 5 are both connected to the common data line CD. The drain of the MO3FETQ13 is connected to the power supply voltage Vcc, and the drain of the MO3FETQ13 is connected to the power supply voltage Vcc.
The drain of MO3FET QI 5 is connected to the power supply voltage Vcc through the load MO3FET QI 4. In addition, the above MO3FET
An intermediate level bias voltage VB formed by a circuit similar to Q11 and Ql2 is applied to the gate of MO3FET QI6. The source of this MO3FET QI 6 is grounded, and its drain is connected to the common data line CD.

When reading information stored in a memory cell, a bias voltage is applied to the memory cell selected by the address decoders X-DCR and Y-DCR via the MO3FETQ13.

The selected memory cell has a threshold voltage higher or lower than the word line selection level, depending on the written information.

When the selected memory cell is turned off regardless of the word line selection level, the common data line CD (7
) potential is brought to a relatively high level by MO3FETQI3. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to a relatively low level. In this case, the high level of the common data line CD is MO3FETQI3
The gate voltage of MO3FETQI 1. According to the conductance ratio of Ql 2, it is brought to a relatively low level by being relatively low.

The low level of the common data line CD is MO3FETQ13.
and MO3FETQI 5 and MO constituting the memory cell.
A relatively high level can be achieved by appropriately setting the size ratio with the SFET.

By restricting the high level and low level of the common data line CD in this way, it is possible to speed up reading even though the common data line CD has a capacitance such as a stray capacitance that limits the speed of signal change. I can do it. That is,
In the case where data is read out from a plurality of memory cells one after another, the time required for one level of the common data line CD to change to the other level can be shortened.

Note that the MO3FET QI 5 for amplification performs an amplification operation of the gate-grounded source input, and transmits its output to the sense amplifier SA constituted by the next-stage differential amplifier circuit. The output of this sense amplifier SA is sent out from the external terminal I10 via the data output buffer DOB.

The control circuit C0NT is a chip enable signal supplied to external terminals CE, OE, PRG, and Vpp.

Depending on the output enable signal, program signal, and high voltage for writing, internal control signals ce and we, which will be described later, are activated.
form etc.

FIG. 2 shows a circuit diagram of a specific embodiment of the address decoder X-DCH.

The address decoder X-DCR of this embodiment is composed of three divided address decoder sections DCR1 to DCR3.

The address decoder section DCR3 is composed of a plurality of unit circuits having an N0R-AND function, although this is not particularly limited. That is, the unit circuit substantially receives a plurality of address signals (in the example shown in the figure, the address signal a
N between 6 and a8).

An R (NOR) logical operation is performed, and the result of this logical operation is ANDed (in the example shown in the figure, the output signal 11crl) of the address decoder unit DCR1
and) performs a logical operation to form an output signal. In the figure, one unit circuit is shown as a representative. This unit circuit consists of a depletion type load MO as shown in the figure.
3FET Q22, and enhancement type drive MO3FETs Q23 to Q26 whose respective gates are supplied with internal address signals a6 to a8 of the upper three bits and an output signal dcrl of the address decoder section DCRI, which will be described next.
is provided between the load MO3FET Q22 and the power supply voltage Vcc, and the address decoder section D is connected to its gate.
It is composed of an enhancement type power switch MO3FETQ21 to which the CRI output signal clcrl is supplied. Although not particularly limited, this unit circuit may include 4
Corresponds to the word line of the book. Although not particularly limited, 256 word lines are formed in this embodiment.

Therefore, in this embodiment, 64 unit circuits are prepared. Although not particularly limited, the power switch MO3FETQ21 is formed to have a low threshold voltage in order to increase the high level of the output signal.

It should be noted that the 63 unit circuits that are not inferior to those shown in the figure also have the same configuration as the above-mentioned unit circuits.

However, the supplied address signal and/or the output signal supplied from the address decoder unit DCRI are different.

By dividing the address decoder as in this embodiment, the unit circuits of the address decoder portion DCR3 can be arranged in the integrated circuit device without limiting the word line pitch (interval). That is, memory array MARY
This eliminates the need to reduce the degree of integration of a plurality of memory elements in the device.゛Address decoder section DCR
1 is an address decoder unit DCR, although it is not particularly limited.
3, it is composed of a plurality of unit circuits having the N0R-AND function. That is, the unit circuit substantially performs a NOR logical operation between a plurality of address signals (for example, address signals al-a3), and further uses the result and the control signal ce.
An AND logical operation is performed between the two to form an output signal. Note that only one unit circuit is shown in the figure.

The unit circuits of the address decoder section DCRI are supplied with internal address signals a1 to a3 of the lower three bits and a control signal ce. Although not particularly limited, in this embodiment, the address decoder section DCR1 includes eight unit circuits, and the remaining seven unit circuits other than the above unit circuits also have a similar configuration to the above unit circuits. has been done. However, the supplied address signal is different as in the case of the address decoder section DCR3 described above.

This address decoder unit DCRI receives complementary address signals a1 to a3 . Since it is supplied with signals al to i3 and includes eight unit circuits, it decodes the complementary address signal of the lower three bits. That is, the address decoder unit DCRI forms an output signal capable of performing 178 selections.

The output signals dcrl and dc of the unit circuits in the address decoder section DC:R1 are respectively supplied to eight unit circuits in the address decoder section DCR3.

Since each decoded output signal dcrl is output from each unit circuit of the address decoder section DCRI, the number of drive MO3FETs in the unit circuit of the address decoder section DCR3 can be reduced.

With the above configuration, the output signal dcr3 of one unit circuit in the address decoder section DCR3 is set to high level only when the 6-bit address signal, that is, the address signal of the above 3 bits and the lower 3 bits, is set to a predetermined level state. Ru. That is, for example, the address decoder section DC
Among the output signals of the 64 unit circuits in R3, only one corresponding to the state of the 6-bit address signal supplied to address decoders DCR1 and DCR3 is set to high level.

The output signal dcr3 of one unit circuit in the address decoder section DCR3 is transmitted through an enhancement type transmission gate (MO3FETQ) corresponding to each word line.
27. Q29. It is commonly transmitted to one electrode (source or drain) of Q31 and Q33. The output signal dcr2 of the address decoder section DCR2 is applied to the gates of these MO3FETQ27 and the like.

This address decoder section DCR2 receives 2-bit address signals a4, . 4 of the unit circuit that decodes a5
Consists of individuals. Note that among the four types of output signals obtained by decoding in the figure, one output signal dcr2.
Only dcr2 is shown.

The above transmission gate MO3FETQ27. Q29°Q31 and Q33 are alternatively turned on by an output signal supplied from the address decoder section DCR2. Therefore, one output signal of the address decoder section DCR2 is transmitted to the four transmission gates MO3FETQ27. Q29. Q3
1 and Q33 are transmitted to one of the other electrodes (word line side).

The above enhancement type transmission gate MO3FETQ27
．． Q29. Enhancement type MO3FETs Q2B, Q30, Q32 and Q34 are provided between the respective output sides of Q31 and Q33 and the ground potential terminal (GND) of the circuit. These MO3FETQ2B, Q30. Q32
The output signal dcr2 of the corresponding address decoder section DCR2 is applied to each gate of Q34.

Furthermore, the transmission gate MO3FETQ27. Q29, Q
A depletion type transmission gate MO3F is connected between the other electrode of each of 31 and Q33 and the word line selection output terminal to which the corresponding word lines W1 to W4, etc. are connected.
ETQ35 to Q38 are provided respectively. The control signal (write control signal) we is commonly applied to the gates of these MO3FETs Q35 to Q3B.

The word lines W1 to W4 shown as representatives above include
Although not particularly limited, depletion type MO3FETs Q40 to Q43 are provided as high resistance loads.

Although not particularly limited, the depletion type MO3FETs Q35 to Q3B have a stacked gate structure so that they have a drain breakdown voltage larger than the high voltage supplied to the write high voltage terminal VPp.

In this embodiment, in order to reduce leakage current in unselected word lines, a depletion type MO is used as the load.
Write control signal Wτ is applied to 3FETQ40 to Q43.
A high voltage for writing vpp' formed by a timing generation circuit TG receiving the high voltage for writing and vpp is supplied. That is, only during the write operation, a high level voltage Vl)p' equal to the high voltage vpp is applied to the depletion type MO3FET Q40 etc. as the load.
will be supplied.

FIG. 3 shows a circuit diagram of an embodiment of the timing generation circuit Ii'8TG.

Depletion type MO3FETQ4 as load means
4 and an enhancement type MO8FE as a driving means
TQ45 constitutes an inverter circuit. Above MO3
A write control signal i is applied to the gate of FETQ45. The inverted signal formed by the inverter circuit and the write control signal iτ are a push-pull type MO8.
FETQ46. These signals are applied to the gates of Q47, forming a so-called invert push-pull circuit.

The output signal of the above push-pull circuit is the output MO3FET
Applied to the gate of Q50. Also, this MO3FET
Diode-type enhancement type MO3FETs Q4B and Q are connected between the gate of Q50 and the high voltage terminal ■pp.
49 is provided as a load. Above M OS F E
The drain of TQ50 is connected to a high level voltage V to the depletion type MO3FETQ40 etc. as the load.
It is connected to the high voltage terminal Vpp to supply pp'. A bootstrap capacitor CB is provided between the gate and source of the MO3FETQ50. A delay signal i of the write control signal 71 is connected between the source of the M.03FET Q50 and the ground potential point of the circuit.
' is provided. The delayed signal w e ' is formed by four cascade-type inverter circuits similar to those described above, each consisting of MOS FETs Q51 to Q58.

That is, the delayed signal chain 1' is formed by transmitting the write control signal iτ through the delay circuit constituted by the inverter circuit. In addition,
Although not particularly limited, in order to reduce the level loss due to the threshold voltage, the MO3FETQ46 and the MO3FETQ46
3FETs Q4B-Q50 are formed to have low threshold voltages.

In a write operation, a high voltage for writing, such as 21V, is supplied to the high voltage terminal vpp. Then, the write control signal we is set to low level. This write control signal; by the low level of 1, MO3FET
Q45. Since Q47 is turned off, the MO
3FETQ4B.

The gate voltage of MO3FETQ50 is Vp through Q49.
It becomes a high level like p-zvth. At this time, MO3
When the gate voltage of the MO3FET Q50 exceeds the power supply voltage Vcc, the FET Q46 is turned off because its gate and source have the same potential at the Vcc level. Note that vth represents the threshold voltage of the MOSFET.

On the other hand, the delay signal we” formed through the delay circuit
MO3FETQ59 until it changes to low level.
is in the on state, the bootstrap capacitor CB is charged up to a high level according to the gate voltage of the MO3FETQ50. Then, due to the low level of the delay signal we', the MOS
Since FET0゜59 is in the off state, MO3FE is
The gate voltage of TQ50 increases. Due to this bootstrap operation, the gate voltage of the MO3FETQ50 can be raised to a high voltage higher than the high voltage VPI), so that the depletion type MOSFE as the load can be
A high voltage vpp' that is approximately equal to the high voltage VPP can be supplied to the TQ40 and the like.

Also, by the high level word line selection signal formed by the address decoder X-DCR of FIG.
The above one depletion type transmission gate MO5FET
Since Q35 etc. are turned off, the level of the word line W1 etc. is equal to the high voltage vp passed through MO3FET Q40.
to a high level according to p'. On the other hand, regarding the unselected word lines, the debension type transmission gate MO3FETQ36 etc. continue to be in the on state due to the low level non-selection signal formed by the above-mentioned X-DCH, so the unselected word lines are set to low level. Become. In order to set the unselected word line to low level in this way, the impedance of MO3FETQ40 etc. that supplies the high voltage to the word line is changed to MO31? which outputs low level. E.T.
Q28. The impedance is set sufficiently large compared to the impedance of Q35, etc.

In addition, in the read operation, the write control signal w
e is at a high level. For this reason, MO3FET
Q45. By the GL47 being in the oscillating state, the MO
This turns 3FETQ50 off. Therefore, from the high voltage terminal vpp to the power supply voltage Vcc, 5V
Even if the MO3FET Q50 is in the off state, the voltage from the terminal VPP is increased by the depletion type MO3FET Q40 to Q serving as the load.
43 etc. will not be supplied.

〔effect〕

(1) In a write operation, the timing generation circuit can supply a high voltage equal to the write high voltage VPp to a selected word line, thereby increasing the speed of the write operation. This has the effect of being able to.

(2) In the read operation, voltage is not supplied to the MOS FETQ4.0 etc. as a load on the word line, so the M on the unselected word line.

The effect of reducing the leakage current flowing through the 5FETQ40 etc. can be obtained. For example, 256
In an EFROM device having a storage capacity of 1,000 bits, the number of word lines is 1024, and even though the leakage current per line is as small as about 5 to 6 μA, the total exceeds 10 mA. In this embodiment, since this leakage current can be reduced, power consumption can be significantly reduced.

(3) Since the timing generation circuit for increasing the speed of the write operation and reducing the power consumption of the read operation uses a bootstrap circuit, it has the advantage that it can be realized by an extremely simple circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, regarding a timing generation circuit for reducing leakage current, the word line load means described above is divided into multiple sets, a plurality of timing generation circuits similar to the above are prepared, and only one of them is activated according to an address signal. The operation may also reduce leakage current during writing. Furthermore, the specific circuit configuration can be modified in various ways.

[Application field]

This invention can be widely used in EPROM devices.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific embodiment of the address decoder X-'DcR, and FIG. FIG. 2 is a circuit diagram showing an example. X-DCR, Y-DCR--7 dress decoder, M-A
RY...Memory array (, SA...Sense amplifier, D
rB...Data output cover sofa, DOB...Data output cover sofa, TG...Timing generation circuit Fig. 1] Fig. 2 No knob Fig. 3 We'

Claims (1)

[Claims] 1. A memory array in which non-volatile semiconductor storage elements having a control gate and a floating gate and storing information by taking charge into the floating gate are arranged in a matrix shape. a high resistance load means having one end connected to the word line to which the control gate is connected; a switch MO3FETQ50 which receives a write control signal and supplies a write high voltage Vflp to the other end of the high resistance load means; 10s to this switch
It is characterized by including a bootstrap capacitor provided between the gate and source of the FETQ50, and an MO3FETQ59 provided between the source of the switch MO3FETQ50 and the ground potential of the switch FI3 to receive a delay signal of the write control signal. EPROM device. 2. The high resistance load means is a depression type Nio
2. The EPROM device according to claim 1, wherein the EPROM device is constituted by an s FET. 3. The EPROM device according to claim 1 or 2, wherein the switch MO3FETQ50 is a low threshold voltage MOS FET.