JP2002043918A - Power on reset circuit and semiconductor integrated circuit device provided with it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power on reset circuit that can surely initialize circuits needing initialization after application of power such as a latch circuit and a flip-flop used for an integrated circuit. SOLUTION: A power-on reset signal PON outputted from an initialization end signal detection section 3 is brought into a high level as soon as a power-on pulse generating section 2 generates a one-shot pulse simultaneously at application of power so as to bring all initialization end signals from initialization completion discrimination sections 4-1 to 4--n to an active level, which have initialization simulation circuits that are designed to be hardly initialized more than a latch circuit and a flip-flop in the integrated circuit. After the initialization end signal detection section 3 detects the reception of all the active levels, the initialization end signal detection section 3 sets the power-on reset signal PON to a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power-on reset circuit and a semiconductor integrated circuit device having the same.
In particular, the present invention relates to a power-on reset circuit that can reliably execute initialization of a circuit requiring initialization such as a latch circuit and a flip-flop in a semiconductor integrated circuit device when power is turned on, and a semiconductor integrated circuit device including the same.

[0002]

2. Description of the Related Art A power-on reset circuit detects a power-on and automatically resets a circuit to be initialized such as a latch circuit or a flip-flop (hereinafter abbreviated as F / F) in a large-scale integrated circuit (LSI). It is used to generate signals and initialize the entire LSI.

A power-on reset circuit 70 of the first prior art shown in FIG. 9A uses an inverter circuit 73 to detect a potential change at a connection point NE between a resistor 71 and a capacitor 72 provided between a VCC power supply terminal and ground. To output a one-shot power-on pulse POP. FIG.
(B) shows changes in the potential of the connection point NE and the power-on pulse POP after the VCC power is turned on. However, in the first conventional example, when the capacitance 72 is set to a large capacitance value, the occupied area increases, and the chip size of the LSI increases. For this reason, in this conventional example, the high-level period of the power-on pulse POP used as a power-on reset signal as it is cannot be sufficiently long, and some of the initialization target circuits in the LSI are not reset without being initialized. In some cases, poor formation occurred.

FIG. 10 shows a known technique that can secure a desired time for an active output period of a power-on reset signal in order to prevent occurrence of initialization failure.

FIG. 10 (a) shows a Japanese Patent Application Laid-Open No. 61-19891.
FIG. 9A shows a second conventional example described in Japanese Patent Publication No.
The power-on pulse POP output from the power-on pulse generation circuit 70 is set and reset by a flip-flop (S
By inputting to the set side of the R-F / F 81, the power-on reset signal PON which is the Q-side output of the SR-F / F 81 is synchronized with the change of the power-on pulse POP from the low level to the high level. Changes from a low level to a high level.

When a reset signal RST is input from the outside,
Since the power-on reset signal PON can be changed from high level to low level by resetting the RF / F81, the power-on reset signal PON can be changed.
Active period can be set externally, and LS
The power-on reset signal PON having a sufficient active period can be supplied to all the latch circuits that need to be reset after the power is turned on in I and the initialization target circuits such as the F / F.

FIG. 10B is a diagram showing the configuration of Japanese Patent Application Laid-Open No. 5-291915.
In the third conventional example described in Japanese Patent Application Laid-Open Publication No. H10-209, an SR-F /
The difference from the second conventional example is that a reset signal of F81 is generated. The SR-F / F 81 is set in synchronization with the change of the power-on pulse POP to the high level, and the timer 82 starts counting time. After a preset time has elapsed, the SR-F / F 81 is reset by the reset signal from the timer 82.
Since the -F / F 81 is reset, the power-on reset signal PON can be supplied as active for a time period set in the timer 82 after the power is turned on.

[0008]

As described above, a power-on reset signal having a sufficient active period must be supplied to a circuit to be initialized which needs to be reset after power is turned on. However, on the other hand, it is desirable that the LSI can start the operation promptly after the power is turned on, and setting a power-on reset time that greatly exceeds the necessary limit undesirably increases a wasteful waiting time.

In the second conventional example, since a reset signal of the SR-F / F is inputted from outside the LSI, the reset signal is generated at an appropriate timing in consideration of a change in the F / F characteristic in the LSI due to manufacturing variations. Difficult to supply,
In consideration of safety, the power-on reset time must be excessively long.

In a third conventional example, an LSI having the same timer
, There is room for setting the time measured by the timer in consideration of manufacturing variations as compared with the second conventional example.
However, a power-on reset signal is obtained in which useless waiting time is reduced as much as possible in consideration of changes due to manufacturing variations between the characteristics of the clock oscillator and the characteristics of the F / F, which determine the clock period, which is the unit time of the timer. It is not easy to make settings so that the clock oscillator changes the amount of change in the clock cycle due to manufacturing variations depending on, for example, one of a crystal oscillation circuit, a ring oscillator, and a CR oscillation circuit. The design has to be changed depending on the type of the clock oscillator, which complicates the design.

An object of the present invention is to provide a power-on reset circuit that reliably realizes initialization of an LSI within an appropriate time without depending on a change in circuit characteristics due to manufacturing variations in an LSI manufacturing process, and a semiconductor having the same. An object of the present invention is to provide an integrated circuit device.

[0012]

According to a first aspect of the present invention, there is provided a power-on reset circuit for detecting a power-on and generating and outputting a one-shot power-on pulse; The change of the pulse to the active level is detected, the power-on reset signal for initializing the initialization target circuit is set to the active level, and it is detected that all of the plurality of initialization completion signals have changed to the active level. A power-on reset signal generation unit having an initialization completion signal detection unit for setting a power-on reset signal to an inactive level; and an initialization time internally simulating an initialization operation of the initialization target circuit and the initialization time. It has a larger initialization simulation circuit, and when a power-on reset signal is input, the logic state of the initialization simulation circuit is inverted to complete initialization Detects that please caution and a plurality of initialization completion judgment unit which outputs the initialization completion signal.

In a semiconductor integrated circuit device having a power-on reset circuit according to a second aspect of the present invention, a power-on reset signal for detecting power-on and initializing a circuit to be initialized is set to an active level, and a plurality of initializations are performed. A power-on reset signal generation unit that detects that all of the completion signals have changed to the active level and sets the power-on reset signal to an inactive level; and an initialization simulation that respectively simulates an initialization operation of a circuit to be initialized. A plurality of initialization completion determination units having a circuit, receiving the power-on reset signal, detecting that the logic state of the initialization simulation circuit has been inverted to the initialization completed state, and outputting the initialization completion signal; Wherein one of the plurality of initialization completion determination units has a wiring path from the power-on reset signal generation unit to the circuit to be initialized. The power-on reset signal provided from the far end of the long signal line of the power-on reset signal, and the other one of the plurality of initialization completion determination units is connected to the power-on reset signal to which the largest number of circuits to be initialized are connected. The signal is input from the far end of the signal line.

A power-on reset circuit according to a third aspect of the present invention comprises:
A power-on pulse generator for generating a one-shot power-on pulse by detecting power-on and outputting the power-on pulse; and power-on for initializing a circuit to be initialized by detecting a change of the power-on pulse to an active level. A power-on reset signal having an active-level reset signal, detecting that all of the plurality of initialization-complete signals have changed to the active level, and setting the power-on reset signal to an inactive level. A generation unit, internally including an initialization simulation circuit that simulates an initialization operation of the initialization target circuit and has an initialization time larger than the initialization target circuit, receives a power-on reset signal, and outputs a logic of the initialization simulation circuit. A plurality of initialization completion judgments each detecting that the state has been inverted to the initialization completion state and outputting the initialization completion signal. And parts, and a test output selector for outputting at least one of an initialization completion signal among the plurality of the initialization complete signal in the test mode to the external terminal.

In a semiconductor integrated circuit device having a power-on reset circuit according to a fourth aspect of the present invention, a power-on reset signal for detecting power-on and initializing a circuit to be initialized is set to an active level, and a plurality of initializations are performed. A power-on reset signal generation unit that detects that all of the completion signals have changed to the active level and sets the power-on reset signal to an inactive level; and an initialization simulation that respectively simulates an initialization operation of a circuit to be initialized. A plurality of initialization completion determination units having a circuit, receiving the power-on reset signal, detecting that the logic state of the initialization simulation circuit has been inverted to the initialization completed state, and outputting the initialization completion signal; A test output selector for outputting at least one initialization completion signal of the plurality of initialization completion signals to an external terminal in a test mode. One of the plurality of initialization completion determination units receives an input from a far end of a signal line of the power-on reset signal, which has a longest wiring path from the power-on reset signal generation unit to a circuit to be initialized. The other one of the plurality of initialization completion determination units is provided by inputting from the far end of the signal line of the power-on reset signal to which the largest number of initialization target circuits are connected. .

[0016]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a power-on reset circuit according to a first embodiment of the present invention.

The power-on reset circuit 10 detects a power-on and generates and outputs a one-shot power-on pulse POP, and detects a change of the power-on pulse POP to an active level. The power-on reset signal PON for initializing the flip-flop is set to the active level, and it is detected that all of the plurality of initialization completion signals RJ1, RJ2,.
A power-on reset signal generator 1 having an initialization completion signal detector 3 that sets ON to an inactive level is provided. In addition, an initialization simulation circuit simulating the initialization operation of the initialization target circuit and having an initialization time longer than the initialization target circuit is provided therein, and a power-on reset signal PON is inputted thereto. Detecting that the state has been inverted to the initialization completed state, the initialization completion signal RJ1,
The power-on reset circuit 10 includes a plurality of initialization completion determination units 4-1, 4-2,..., 4-n that output RJ2,.

The power-on reset circuit 10 supplies a power-on reset signal PO to a circuit to be initialized such as a latch circuit or F / F disposed in the LSI at the same time when power is turned on.
N is set to the active level to start initialization, and each of the initialization completion determination units 4-1 4-2,.
The time required for initialization of the initialization simulation circuit that simulates the initialization operation of the initialization target circuit built in −n is made longer than the initialization target circuit such as a latch circuit or F / F arranged in the LSI. And all the initialization completion determination units 4-1 and 4-
When it is determined in 2,..., 4-n that the initialization simulation circuit has changed to the initialization completed state, it is considered that all the initialization target circuits in the LSI have been initialized, and the initialization completion signal determination unit 3 The power-on reset signal PON is returned to the non-active level.

FIG. 2 is an operation timing chart of each part of the power-on reset circuit 10. The power-on pulse POP rises to the VCC level following the potential rise after the VCC power is turned on. If the circuit of the first conventional example shown in FIG. 9 is used as the power-on pulse generator, the capacitance value and the resistance value After the elapse of a predetermined time TPOP determined by the following equation, the power-on pulse POP drops to the ground level. On the other hand, the power-on reset signal PON is
After the power-on pulse POP changes to a low level, the active level is maintained even after the power-on pulse POP changes to a low level.
-1, 4-2,... 4-n, an initialization completion signal RJ1,
The power-on reset signal PON is changed to a low level, which is an inactive level, only after the initialization completion signal determination unit 3 detects that all of RJ2,... RJn have changed to a high level, which is an active level. Therefore, a period TPON from the power-on of the power-on reset signal PON to the return to inactive is a period T1 from the power-on of the initialization completion signal RJ1 to the activation, and becomes active from the power-on of the initialization completion signal RJ2. In this case, it is ensured that the period T2 is equal to or longer than the largest period in the period Tn from when the power of the initialization completion signal RJn is turned on until the signal becomes active.

The initialization completion judging section is provided by an LSI including a portion where it is estimated that the signal delay amount of the power-on reset signal PON from the power-on reset signal generating section becomes the largest.
The active level period TPON of the power-on reset signal PON corresponds to not only a change in transistor characteristics due to manufacturing variations, but also a change in signal delay due to variations in the width and thickness of metal wiring. Automatically changes, the initialization execution of the initialization target circuit such as the latch circuit and the F / F can be reliably guaranteed when the power is turned on, and the power-on reset is performed as in the second and third conventional examples. It is not necessary to set the active level period in the signal PON excessively.

FIG. 3A is a circuit diagram of an embodiment of the initialization completion judging section, and FIG. 3B is an operation timing chart thereof. The initialization completion determination unit 4a outputs a NAND to the connection point NA.
An initialization simulation circuit including a latch circuit configured by connecting the output terminal of the circuit 12 and the input terminal of the inverter circuit 13 and connecting the one input terminal of the NAND circuit 12 and the output terminal of the inverter circuit 13 to the connection point NB. Have
The power-on reset signal PON is inverted by the inverter circuit 11 and input to the other input terminal of the NAND circuit 13. A capacitor 14 is connected between the connection point NA and the ground, a capacitor 15 is connected between the connection point NB and the power supply VCC, and a buffer circuit having the connection point NA connected to the input terminal and having the same input and output. 16 output end signal R
Ja is output.

As shown in FIG. 3B, after the power supply VCC is turned on, the connection completion point NA stops at a low level due to capacitive coupling, and the connection point NB rises following the VCC, as shown in FIG. The connection point NA is at a low level and the connection point N
B is once stabilized at a high level, and the initialization completion signal R
Ja is at a low level. A power-on reset signal PO is supplied to the initialization completion determination section 4a in this state.
By maintaining N as an active level, NA
Since the level of the connection point NA connected to the output terminal of the ND circuit 12 rises toward the potential level of the VCC power supply, the NAND circuit 12 which is the initialization simulation circuit and the inverter circuit 1
The logic state of the latch circuit consisting of
Is at a high level and the connection point NB is at a low level and is initialized, so that after an elapse of the initialization time Ta after the power is turned on, the initialization completion signal RJa becomes the active level of the high level and notifies the completion of the initialization. Initialization completion determination unit 4a
In this case, the capacitance 14 and the capacitance 15 are added to increase the NA compared with the parasitic capacitance of the corresponding portion in the initialization target circuit such as the F / F and the latch circuit in the LSI.
The initialization time of the initialization simulation circuit including the ND circuit 12 and the inverter circuit 13 can be reliably made longer than the initialization time of the initialization target circuit.

FIG. 4A is a circuit diagram of another embodiment of the initialization completion judging section, and FIG. 4B is an operation timing chart thereof. The initialization completion determining unit 4b includes an inverter circuit 21 for inputting a power-on reset signal PON, a P-channel having a source connected to the VCC power supply, a gate connected to the output terminal of the inverter circuit 21, and a drain connected to the connection point NC. A MOS transistor 22; a resistor 23 having one end connected to the connection point NC and the other end grounded; an inverter circuit 24 having an input end connected to the connection point NC and an output end connected to the connection point ND; The inverter circuit 25 includes an inverter circuit 25 connected to the connection point ND and an output terminal connected to the connection point NC, and an inverter circuit 26 connected to the input terminal ND and outputting an initialization completion signal RJb.

A latch circuit is constituted by the inverter 24 and the inverter 25 and used as an initialization simulation circuit. CMO
By setting the current extraction capability of the N-channel MOS transistor of the S inverter circuit 25 to be several times or more larger than the current supply capability of the P-channel MOS transistor, the connection point NC immediately after turning on the power is maintained at a low level.

As shown in FIG. 4B, after the power supply VCC is turned on, the output of the inverter 21 rises following the rise in the potential of the power supply VCC. Maintain the off state.
Therefore, the connection point NC stays at the low level, and the connection point N
Since D rises following VCC, the initialization completion signal R
Jb is at a low level. The power-on reset signal PO is supplied to the initialization completion determination section 4b in this state.
By maintaining N as an active level, the output terminal of the inverter circuit 21 changes to a low level.
Since the P-channel MOS transistor 22 changes to the ON state, the connection point NC changes to the high level, and the connection point ND changes to the low level and is initialized, the initialization is completed after the lapse of the initialization time Tb after the power is turned on. The signal RJb goes to the high level of the active level to notify the completion of the initialization. In the initialization completion determination unit 4b, the current extraction capability of the N-channel MOS transistor of the CMOS inverter circuit 25 is set to L
By setting the F / F inside the SI and the N-channel MOS transistor of the corresponding inverter circuit in the initialization target circuit such as the latch circuit, the initialization time of the initialization simulation circuit is initialized. Can be greater than time.

FIGS. 5A and 5B are circuit diagrams of an embodiment of the initialization completion signal detecting section. The initialization completion signal detector 3a in FIG. 5A receives a power-on pulse POP from a set input terminal and outputs a power-on reset signal from a Q-side output terminal to a set-reset flip-flop (SR-F).
/ F) 31 and a plurality of initialization completion signals RJ1, RJ2,
.. Having a multi-input AND circuit 32 which inputs RJn and whose output terminal is connected to the reset input terminal of the SR-F / F 31. In the initialization completion signal detecting section 3a, a plurality of initialization completion signals RJ1 and RJ1 and RJ1 and RJ2 are replaced with a reset signal input from the outside of the SR-F / F in the second conventional example of FIG.
Detecting that all of J2,... RJn have become active levels, the AND circuit 32 generates a signal that becomes active, thereby resetting the SR-F / F31.

Power-on pulse P by turning on VCC power
When OP changes from low level to high level, SR-
Power-on reset signal P which is the Q-side output of F / F 31
ON changes from the low level to the high level, and the power-on reset signal PON maintains the high level even when the power-on pulse POP returns to the low level. When all of the plurality of initialization completion signals RJ1, RJ2,... RJn change to high level, the output of the multi-input AND circuit 32 goes high to reset the SR-F / F 31, and the power-on reset signal PON becomes inactive. It changes to the low level which is the level.

An initialization completion signal detecting section 3b shown in FIG. 5B, which is another embodiment of the initial completion signal detecting section 3, has an OR circuit 33 in which a power-on pulse POP is input to a first input terminal.
And a plurality of initialization completion signals RJ1, RJ2,... RJn, and a multi-input NAND circuit 34 having an output terminal connected to the second input terminal of the OR circuit 33. When the power-on pulse POP goes high, the power-on reset signal PON also goes high, which is the active level. However, a plurality of initialization completion signals RJ1, RJ2,.
The output of the NAND circuit 34 maintains the high level while at least one of them is at the low level which is the inactive level. Therefore, even if the power-on pulse POP goes low during this period, the power-on reset signal PON remains high. Maintain levels. A plurality of initialization completion signals RJ1, R
When all of J2,... RJn become active level, the output of the NAND circuit 34 becomes low level, and the power-on reset signal PON output from the OR circuit 33 changes to low level of inactive level. Therefore, the initialization completion signal detection unit 3b can realize the same operation as the initialization completion detection unit 3a with a simple circuit configuration.

FIG. 6 is a schematic layout diagram of an LSI chip on which the power-on reset circuit of the first embodiment is mounted. In the LSI chip 41, a power-on reset signal PON for detecting a VCC power-on and initializing a circuit to be initialized such as a latch circuit and F / F in the LSI is set to an active level, and a plurality of initialization completion signals are provided. The power-on reset signal generator 1 detects that all of them (not shown for simplicity) have changed to the active level and sets the power-on reset signal PON to the inactive level.
And a power-on reset signal PON, a plurality of initialization completion determinations for detecting that the logic state of the initialization simulation circuit included therein has been inverted to an initialization completed state, and outputting an initialization completion signal. And a latch circuit and F /
The PON signal line 44- of the power-on reset signal PON to which the initialization target circuit such as F is most connected and the load is large.
x is provided with an initialization completion determination unit 4-x, and an initialization completion determination unit 4 is provided for the PON signal line 44-y having the longest wiring path from the power-on reset signal generation unit 1 to the circuit to be initialized. -Y is provided.

As described above, the power-on reset signal in which the reset time of the initialization target circuit is delayed due to the signal delay due to the parasitic resistance and the parasitic capacitance of the wiring and the signal delay due to the number of the initialization target circuits connected to the wiring and serving as a load. By always providing the initialization completion determination unit for the PON wiring,
The power-on reset signal PON is also applied to the initialization target circuit whose initialization is executed with the longest delay in the entire LSI chip.
, An active level with a sufficient pulse width is secured.

In FIG. 6, reference numeral 42 denotes a VCC power supply terminal, reference numeral 43 denotes a VCC power supply line, reference numeral 44-z denotes another PON signal line, and reference numeral 4-z denotes an initialization completion provided for the PON signal line. It is a determination unit.

As described above, according to the first embodiment of the present invention, the initial state of the LSI can be surely set within an appropriate time without depending on a change in circuit characteristics due to manufacturing variations in the manufacturing process of the LSI. And a semiconductor integrated circuit device having the same.

FIG. 7 is a circuit diagram of a power-on reset circuit 10a according to a second embodiment of the present invention. The power-on reset circuit 10a selects the output of the initialization completion determination unit by setting the test signal TEST to an active level in addition to the components of the power-on reset circuit 10 of FIG. A selector 51 is provided for outputting to the selector 52.

When the LSI is in the normal mode, the test signal TEST is inactive and the selector 51
The data output DOUT from the inside of the LSI is selected and output to the data output / test output shared terminal 52. When a failure related to the initialization of the LSI occurs, the test mode is set to activate the test signal TEST, and the initialization completion signal RJn of the initialization completion determination section 4-n is output to the data output / test output shared terminal 52, for example. Then, the output level of the initialization completion signal RJn is observed. In the present embodiment,
If the output level is high, the power-on reset signal generator 1 and the initialization completion determiner 4-n can determine that they have operated normally, and the cause of the failure related to the initialization of the LSI is the F / F or the like. It is possible to easily and quickly determine whether the initialization target circuit is defective due to a failure of the initialization target circuit, or whether it is a defective initialization completion determination unit.

By using a plurality of data output / test output shared terminals and externally observing the initialization completion signals RJ1, RJ2,. Can be determined with higher accuracy whether the error is caused by a failure of the power-on reset circuit or a failure of the circuit to be initialized.

Alternatively, in the test mode, the multi-input shown in FIG. 5A for detecting whether the initialization completion signal in the initialization completion signal detection section has become active level together with the initialization completion signal from the initialization completion determination section. The output signal of the AND circuit 32 or the output signal of the multi-input NAND circuit 34 of FIG. 5B may be taken out to an external terminal via a selector. For example, if it can be observed that one of the initialization completion signals is at a high level and the output of the multi-input NAND circuit of FIG. 5B is at a low level, it indicates that the power-on reset circuit 1 has normally operated. It can be determined that the cause of the initialization failure is not in the power-on reset circuit 1.

FIG. 8 is a schematic layout diagram of an LSI chip 41a on which the power-on reset circuit of the second embodiment is mounted. The LSI chip 41a activates a power-on reset signal PON for initializing a circuit to be initialized such as a latch circuit inside the LSI and an F / F, by detecting the VCC power supply, as in the LSI chip 41 of FIG. Level, and detects that all of the plurality of initialization completion signals have changed to the active level.
A power-on reset signal generation unit 1 that sets ON to an inactive level and a power-on reset signal PON are input, and it is detected that the logic state of the initialization simulation circuit included therein has been inverted to the initialization completed state. A plurality of initialization completion determining units 4-x and 4-y for outputting an initialization completion signal, and a data output 61 from an arithmetic unit in the LSI chip and outputs of the plurality of initialization completion determining units Of at least one initialization completion signal 62 among the initialization completion signals, the data output / test output shared terminal 52
And a selector 51 for outputting to Similarly to the LSI chip of FIG. 6, one of the plurality of initialization completion judging units is a signal line of a power-on reset signal to which the largest number of initialization target circuits are connected. And a signal line for the power-on reset signal having the longest wiring path from the power-on reset signal generation unit to the circuit to be initialized. Input from the far end.

By using a plurality of data output / test output shared terminals, the initialization completion signals RJ1, RJ2,... RJn of the plurality of initialization completion determination units can be taken out in the test mode. The cause of the initialization failure can be determined with higher accuracy.

[0039]

As described above, according to the first embodiment of the present invention, an excessive power-on reset time is not required without depending on a change in circuit characteristics due to manufacturing variations in an LSI manufacturing process. A power-on reset circuit that reliably realizes initialization of an LSI within an appropriate time and a semiconductor integrated circuit device including the same can be obtained. Further, according to the second embodiment, in addition to the same effects as those of the first embodiment, when an initialization failure occurs, the cause is a failure of the power-on reset circuit or an LSI.
It is possible to easily and quickly determine whether or not a failure has occurred in a circuit to be initialized such as a latch circuit or an F / F circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power-on reset circuit according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of each unit of the power-on reset circuit.

FIG. 3A is a circuit diagram of an embodiment of an initialization completion determination unit, and FIG. 3B is an operation timing diagram thereof.

FIG. 4A is a circuit diagram of another embodiment of the initialization completion determining unit, and FIG. 4B is an operation timing diagram thereof.

FIG. 5A is a circuit diagram of an embodiment of an initialization completion signal detection unit, and FIG. 5B is a circuit diagram of another embodiment of an initialization completion signal detection unit.

FIG. 6 is a schematic layout diagram of an LSI chip including a power-on reset circuit according to the first embodiment;

FIG. 7 is a circuit diagram of a power-on reset circuit according to a second embodiment of the present invention.

FIG. 8 is a schematic layout diagram of an LSI chip including a power-on reset circuit according to a second embodiment;

FIG. 9A is a circuit diagram of a first conventional example,
(B) is an operation timing chart thereof.

FIG. 10A is a circuit diagram of a second conventional example,
(B) is a circuit diagram of a third conventional example.

[Explanation of symbols]

Reference Signs List 1 power-on reset signal generation unit 2 power-on pulse generation unit 3, 3a, 3b initialization completion signal detection unit 4-1, 4-2, 4-n, 4-x, 4-y, 4-z, 4
a, 4b Initialization completion determination section 10 Power-on reset circuit 11, 13, 21, 24, 25, 26 Inverter circuit 12 NAND circuit 14, 15 Capacitance 16 Buffer circuit 22 P-channel MOS transistor 23 Resistance 31 Set reset flip-flop 32 Many Input AND circuit 33 OR circuit 34 Multi-input NAND circuit 41, 41a LSI chip

Claims (8)

[Claims] 1. A power-on pulse generator for generating and outputting a one-shot power-on pulse upon detecting power-on, and detecting a change of the power-on pulse to an active level to initialize a circuit to be initialized. A power-on reset signal for the active level, detects that all of the plurality of initialization completion signals have changed to the active level, and sets the power-on reset signal to an inactive level. A power-on reset signal generation unit having an initialization simulation circuit that simulates an initialization operation of the initialization target circuit and has an initialization time longer than the initialization target circuit. A plurality of circuits each of which detects that the logic state of the simulated circuit has been inverted to the initialization completed state and outputs the initialization completion signal. Power-on reset circuit, characterized in that it comprises an initialization completion judgment unit. A first inverter circuit to which a power-on reset signal is inputted; an output of the first inverter circuit being inputted to a first input terminal, and an output terminal being a first inverter circuit; A two-input NAND circuit connected to a connection point, a second input terminal connected to the first connection point and an output terminal connected to the second connection point, and a second input terminal connected to the second input terminal of the two-input NAND circuit; An inverter circuit, a first capacitor provided between the first connection point and a ground terminal, a second capacitor provided between the second connection point and a power supply terminal, 2. The power-on reset circuit according to claim 1, further comprising a buffer circuit having an input terminal connected to said first connection point and outputting an initialization completion signal from an output terminal. A first inverter circuit for inputting a power-on reset signal; a source connected to a power supply terminal, a gate connected to an output terminal of the first inverter circuit, and a drain connected to the first inverter circuit. A P-channel MOS transistor connected to a first connection point; a resistance element having one end connected to the first connection point and the other end connected to a ground terminal; an input terminal connected to the first connection point and an output A second inverter circuit having an end connected to the second connection point, an input end connected to the second connection point, and an output end connected to the first connection point;
2. The power-on reset circuit according to claim 1, further comprising: a third inverter circuit connected to the second connection point; and a fourth inverter circuit having an input terminal connected to the second connection point and outputting an initialization completion signal. . 4. A set-reset flip-flop for inputting a power-on pulse to a set input terminal and outputting a power-on reset signal from an output terminal, and receiving a plurality of initialization completion signals. 2. The power-on reset circuit according to claim 1, further comprising a multi-input AND circuit having an output terminal connected to a reset input terminal of the set / reset flip-flop. 5. A two-input OR circuit for inputting a power-on pulse to a first input terminal and outputting a power-on reset signal from an output terminal, the initialization completion signal detection unit comprising: a plurality of initialization completion signals; Input and output terminal
2. The power-on reset circuit according to claim 1, further comprising a multi-input NAND circuit connected to a second input terminal of the R circuit. 6. A power-on reset signal for initializing a circuit to be initialized by detecting power-on is set to an active level, and it is detected that all of a plurality of initialization completion signals have changed to an active level. A power-on reset signal generation unit for setting a power-on reset signal to an inactive level; and an initialization simulation circuit for simulating an initialization operation of a circuit to be initialized, each of which has the power-on reset signal input and performs the initialization. A plurality of initialization completion judging sections for detecting that the logic state of the simulation circuit has been inverted to be in the initialization completion state and outputting the initialization completion signal, wherein one of the plurality of initialization completion judging sections is provided. The wiring path from the power-on reset signal generation unit to the initialization target circuit is provided by inputting the longest power-on reset signal from the far end of the signal line. The other one of the plurality of initialization completion determination units is provided by inputting from the far end of the signal line of the power-on reset signal to which the largest number of initialization target circuits are connected. A semiconductor integrated circuit device having a power-on reset circuit. 7. A power-on pulse generator for generating and outputting a one-shot power-on pulse upon detecting power-on, and detecting a change of the power-on pulse to an active level to initialize a circuit to be initialized. A power-on reset signal for the active level, detects that all of the plurality of initialization completion signals have changed to the active level, and sets the power-on reset signal to an inactive level. A power-on reset signal generation unit having an initialization simulation circuit that simulates an initialization operation of the initialization target circuit and has an initialization time longer than the initialization target circuit. A plurality of circuits each of which detects that the logic state of the simulated circuit has been inverted to the initialization completed state and outputs the initialization completion signal. An initialization completion determining unit, a power-on reset circuit characterized by comprising a test output selector for outputting at least one of an initialization completion signal to the external terminals of the plurality of the initialization completion signal in the test mode. 8. A power-on reset signal for initializing a circuit to be initialized by detecting power-on is set to an active level, and it is detected that all of a plurality of initialization completion signals have changed to an active level. A power-on reset signal generation unit for setting a power-on reset signal to an inactive level; and an initialization simulation circuit for simulating an initialization operation of a circuit to be initialized, each of which has the power-on reset signal input and performs the initialization. A plurality of initialization completion determination units for detecting that the logic state of the simulation circuit has been inverted to the initialization completion state and outputting the initialization completion signal; and at least one of the plurality of initialization completion signals in a test mode. A test output selector for outputting a number of initialization completion signals to an external terminal, wherein one of the plurality of initialization completion determination units has the power A wiring path from an on-reset signal generation unit to an initialization target circuit is provided by being input from a far end of a signal line of the longest power-on reset signal, and another one of the plurality of initialization completion determination units is provided. A semiconductor integrated circuit device having a power-on reset circuit, which is provided by being input from a far end of a signal line of the power-on reset signal which is most connected to the initialization target circuit.