TWI760673B - Electronic device - Google Patents

Abstract

An electronic device including a plurality of peripheral components, a flash memory and a test mode circuit is provided. The flash memory provides a plurality of test reference data. The test mode circuit responds to a test entry signal and provides a plurality of test data based on the test reference data to the peripheral components for testing the peripheral components.

Description

electronic device

The present invention relates to an electronic device, and more particularly, to an electronic device entering a test mode.

In the past, the test mode of an electronic device is to input specific data through an input and output interface (eg, a general-purpose input output (GPIO)) and determine whether the input data is an entry key (Entry Key) to determine whether to enter the test mode. However, in order to prevent customers from mistakenly entering the test mode when using the I/O interface and thus affecting the behavior of the chip, the access key is designed in a form of high complexity, large number of bits, and not easy to enter randomly. However, such an operation mode also increases the difficulty for the measurement personnel to enter the test mode. In addition, the operator must maintain the voltage state of the reset pin in the reset state after entering the test mode, so that the processor (such as the central processing unit (CPU)) is not involved, and the test mode can be used for measurement. Therefore, how to make the test mode easier to enter without being mistakenly entered by the user has become a key point in designing an electronic device.

The present invention provides an electronic device, which can improve the testing capability of the electronic device and shorten the testing time and cost.

The electronic device of the present invention includes a plurality of peripheral components, a flash memory and a test mode circuit. Flash memory provides multiple test references. The test mode circuit provides a plurality of test data based on the test reference data to the peripheral devices respectively in response to the test entry signal, so as to test the peripheral devices.

Based on the above, in the electronic state of the embodiment of the present invention, the data provided through the flash memory is used as the test reference data for the test mode circuit to be tested, and it is not necessary to input the test related data from the electronic device. Therefore, when entering the test mode You can omit the input pins and use most (or all) of the pins for output data (or test results). In this way, the testing capability of the electronic device can be improved, and the testing time and cost can be shortened.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

FIG. 1 is a system schematic diagram of an electronic device according to an embodiment of the present invention. Referring to the drawings, in this embodiment, the electronic device 100 includes a power supply circuit 110, a flash memory 120, a processor 130, a test mode circuit 140, and peripheral components 150, 160, wherein the peripheral components 150, 160 at least include a voltage-controlled oscillator regulators, voltage regulators and reference voltage circuits. The flash memory 120 is coupled to the power circuit 110 , the processor 130 , the test mode circuit 140 and the peripheral components 150 and 160 .

In this embodiment, the electronic device 100 is activated in response to the power-on signal Pon, wherein the power-on signal Pon may be generated by an input interface (eg, keys, touch keys, switches, etc.) of the electronic device 100 . Further, the power circuit 110 provides at least the system voltage Vdd to the flash memory 120 in response to the power-on signal Pon, and the flash memory 120 starts the initialization process in response to receiving the system voltage Vdd.

During the initialization period, the power circuit 110 controls the reset pin of the processor 130 to be in a reset state. For example, the power circuit 110 can provide the reset signal HRESETn with a logic low level or logic level “0” to the processor 130 reset pin.

In the initialization process, the flash memory 120 sequentially provides a plurality of initialization parameters DPc, DP1, DP2, and DPT to the processor 130, the peripheral devices 150, 160, and the test mode circuit 140, so as to set the processor 130 and the peripheral devices in sequence 150 , 160 and the operating mode and operating state of the test mode circuit 140 .

After the initialization process, that is, after the initialization period, the electronic device 100 determines whether to operate in the test mode or the user mode in response to whether the test entry signal S_Test is received (or generated), wherein the test entry signal S_Test can be operated through an input interface (eg pin) from the external input of the electronic device 100 or generated by the electronic device 100 itself.

Moreover, after the initialization process, the flash memory 120 can provide a plurality of data Data to the processor 130 and the test mode circuit 140 in sequence. When the electronic device 100 receives (or generates) the test entry signal S_Test, the test mode circuit 140 is enabled in response to the test entry signal S_Test, and the power circuit 110 enables the reset pin of the processor 130 in response to the test entry signal S_Test Maintaining in the reset state, that is, the reset signal HRESETn is maintained at a logic low level or a logic level "0", so that the processor 130 is kept in an inoperable state.

At this time, the data of the flash memory 120 will be provided to the processor 130 and the test mode circuit 140 as the test reference data DTS, but the processor 130 will not respond to the test reference data DTS, and the test mode circuit 140 will respond to the test entry The signal S_Test provides a plurality of test data D_Test1 and D_Test2 based on the test reference data DTS (eg, input control signals of the analog circuit) to the peripheral elements 150 and 160 respectively, so as to test the peripheral elements 150 and 160 .

When the electronic device 100 does not receive (or does not generate) the test entry signal S_Test, the test mode circuit 140 will be disabled in response to not receiving the test entry signal S_Test, and the power circuit 110 will enable the power supply circuit 110 in response to not receiving the test entry signal S_Test. The reset pin of the processor 130 is released from the reset state, that is, the reset signal HRESETn changes from a logic low level or logic level "0" to a logic high level or logic level "0", so that the processing The device 130 enters an operational state.

Next, the electronic device 100 will return to the power-on process to restore the power supply of all components (eg, the processor 130 , peripheral components 150 , 160 ). After the boot process is completed, the user mode is entered, and the processor 130 can access the data Data from the flash memory 120 to execute the application program written into the flash memory 120 by the user.

According to the above, in the embodiment of the present invention, the data provided by the flash memory 120 is used as the test reference data DTS referenced by the test mode circuit 140 for testing, and there is no need to input test-related data from the electronic device 100, so the test is performed before entering the test. In mode, the input pins can be omitted and most (or all) of the pins can be used for output data (or test results). In this way, the testing capability of the electronic device 100 can be improved, and the testing time and cost can be shortened.

In the embodiment of the present invention, the test data D_Test1 and D_Test2 may be the first part data of the corresponding test reference data DTS, respectively. In addition, the data of the second part of the test reference data DTS can be used to instruct each of the test data D_Test1 and D_Test2 to be transmitted to the corresponding peripheral elements 150 and 160 , that is, the data of the second part of the test reference data DTS represents the data of the electronic device 100 . Test items, in which the second part of the data is different from the first part of the data.

In the embodiment of the present invention, the test storage area Mtest storing the test reference data DTS in the flash memory 120 is shared with the user, that is, the test storage area Mtest is not an area dedicated to the system, but the user can see and area used. Therefore, before the test of the peripheral devices 150 and 160 is completed, the test storage area Mtest can store the test related data (ie, the test reference data DTS), and after the test of the peripheral devices 150 and 160 is completed, the test storage area Mtest is erased. In order to avoid affecting the user's free space.

In the embodiment of the present invention, a control circuit (not shown) can be configured in the electronic device 100 to control the timing of outputting the initialization parameters DPc, DP1, DP2, DPT, and the test reference data DTS from the flash memory 120, that is, to control The circuit (not shown) can sequentially provide the address corresponding to the initialization parameters DPc, DP1, DP2, DPT, and the test reference data DTS to the control flash memory 120 . In other words, the control circuit (not shown) can provide the address corresponding to the initialization parameters DPc, DP1, DP2, DPT, and the test reference data DTS in response to the system voltage Vdd. In the embodiment of the present invention, the control circuit (not shown) may be configured in the flash memory 120 . In the embodiment of the present invention, the control circuit (not shown) may be enabled in response to the system voltage Vdd, and may be disabled in response to the test entry signal S_Test.

FIG. 2 is a system schematic diagram of an electronic device according to another embodiment of the present invention. Please refer to FIG. 1 and FIG. 2 , wherein the electronic device 200 mainly shows the difference from the electronic device 100 . In other words, the electronic device 200 further includes a latch circuit 210 and a multiplexer 230 . The latch circuit 210 is coupled between the flash memory 120 , the test mode circuit 140 and the processor 130 to provide one of the test reference data DTS to the test mode circuit 140 for processing in response to receiving the latch signal S_LAT The controller 130 transmits the plurality of test reference data DTS to the test mode circuit 140 and the processor 130 one by one in response to the latch signal S_LAT.

The multiplexer 230 has a first input terminal for receiving the external signal S_Ext, a second input terminal for receiving the internal clock signal Clk_I, a control terminal for receiving the test entry signal S_Test, and an output terminal for providing the latch signal S_LAT, wherein the internal clock signal Clk_I can be generated by a clock generator or oscillator inside the electronic device 100 , and the external signal S_Ext is input from the outside through the pins of the electronic device 200 .

In the embodiment of the present invention, when the control terminal of the multiplexer 230 receives the test entry signal S_Test, the multiplexer 230 can provide the external signal S_Ext as the latch signal S_LAT, and at this time, the tester can control the electronic device through the external signal S_Ext 200 is the speed (or rhythm) of the test; when the control terminal of the multiplexer 230 does not receive the test entry signal S_Test, the multiplexer 230 can provide the internal clock signal Clk_I as the latch signal S_LAT.

The test mode circuit 140 is further coupled to the flash memory 120, and the test mode circuit 140 returns the third part data D_PAT3 of the test reference data DTS to the flash memory 120 to indicate the test reference data to be read next The address of the DTS, where the third part of the data D_PAT3 is different from the first part of the data and the second part of the test reference data DTS. Therefore, when the electronic device 200 enters the test mode, the electronic device 200 will automatically perform the test operation.

To sum up, in the electronic state of the embodiment of the present invention, the data provided by the flash memory is used as the test reference data for the test mode circuit to be tested, and there is no need to input the test related data from the electronic device, so when entering the In test mode, the input pins can be omitted and most (or all) of the pins can be used for output data (or test results). In this way, the testing capability of the electronic device can be improved, and the testing time and cost can be shortened.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100, 200: Electronic devices 110: Power circuit 120: flash memory 130: Processor 140, 220: Test mode circuit 150, 160: Peripheral components 210: Latch circuit 230: Multiplexer Clk_I: Internal clock signal D_PAT3: The third part of the information D_Test1, D_Test2: Test data Data: data DPc, DP1, DP2, DPT: initialization parameters DTS: Test References HRESETn: reset signal Mtest: Test storage area Pon: power on signal S_Ext: External signal S_LAT: Latch signal S_Test: Test entry signal Vdd: system voltage

FIG. 1 is a system schematic diagram of an electronic device according to an embodiment of the present invention. FIG. 2 is a system schematic diagram of an electronic device according to another embodiment of the present invention.

100: Electronics

110: Power circuit

120: flash memory

130: Processor

140: Test Mode Circuit

150, 160: Peripheral components

D_Test1, D_Test2: Test data

Data: data

DPc, DP1, DP2, DPT: initialization parameters

DTS: Test References

HRESETn: reset signal

Mtest: Test storage area

Pon: power on signal

S_Test: Test entry signal

Vdd: system voltage

Claims (8)

An electronic device includes: a plurality of peripheral components; a flash memory for providing a plurality of test reference materials; a processor with a reset pin; a test mode circuit, which responds to a test entry signal based on the tests A plurality of test data of the reference data are respectively provided to the peripheral components, so as to test the peripheral components independently of the processor; and the power circuit keeps the reset pin in a heavy state in response to the test entry signal set state, wherein the power circuit provides a system voltage to the flash memory in response to a power enable signal, and the flash memory initiates an initialization procedure in response to receiving the system voltage, in which the flash memory The body sequentially provides a plurality of initialization parameters to the processor, the peripheral elements and the test mode circuit. The electronic device of claim 1, wherein the flash memory provides the test reference data after the initialization process. The electronic device according to claim 1, wherein each of the test data is a first part of the corresponding test reference data. The electronic device as described in claim 3, wherein a second part of data of each of the test reference data instructs each of the test data to be transmitted to a corresponding peripheral element, wherein the second part of data is different from the The first part of the information. The electronic device of claim 4, wherein a third part of each of the test reference data is returned to the flash memory to indicate the address of the next read test reference data. The electronic device as described in claim 1, further comprising: a latch circuit, coupled between the flash memory, the test mode circuit and the processor, for responding to receiving a latch signal to One of the test references is provided to the test mode circuit and the processor. The electronic device as described in claim 6, further comprising: a multiplexer having a first input terminal for receiving an external signal, a second input terminal for receiving an internal clock signal, and receiving the test input terminal. A control terminal of the signal and an output terminal for providing the latch signal. The electronic device as described in claim 7, wherein when the control terminal receives the test entry signal, the multiplexer provides the external signal as the latch signal, and when the control terminal does not receive the test entry signal , the multiplexer provides the internal clock signal as the latch signal.

Images