TW202125523A - Electronic device - Google Patents

Abstract

An electronic device including a plurality of peripheral components, a flash memory and a test mode circuit is provided. The flash memory provides a plurality of test reference data. The test mode circuit responds to a test entry signal and provides a plurality of test data based on the test reference data to the peripheral components for testing the peripheral components.

Description

Electronic device

The present invention relates to an electronic device, and more particularly to an electronic device that enters a test mode.

In the past, the test mode of an electronic device used input and output interfaces (such as general-purpose input and output (GPIO)) to input specific data and determine whether the input data is an entry key to determine whether to enter the test mode. However, in order to prevent customers from erroneously entering the test mode when using the input and output interfaces and thus affecting the behavior of the chip, the access key is designed to be highly complex, with a large number of bits, and not easy to enter randomly. However, such an operation mode also increases the difficulty for the measurement personnel to enter the test mode. In addition, after the operator enters the test mode, the voltage state of the reset pin must be maintained in the reset state, so that the processor (such as the central processing unit (CPU)) is not involved, and the test mode can be used for measurement. Therefore, how to make the test mode easier to enter without being mistaken by the user has become an important point in the design of electronic devices.

The present invention provides an electronic device, which can improve the testing ability of the electronic device, and can shorten the test time and cost.

The electronic device of the present invention includes a plurality of peripheral components, flash memory and a test mode circuit. Flash memory provides multiple test reference materials. The test mode circuit responds to the test entry signal and provides a plurality of test data based on the test reference data to the peripheral components to perform the test of the peripheral components.

Based on the above, in the electronic state of the embodiment of the present invention, the data provided through the flash memory is used as the test reference data for the test mode circuit test, without inputting test-related data from the electronic device, so when entering the test mode In this case, you can omit the input pins and use most (or all) of the pins for output data (or test results). In this way, the testing capability of the electronic device can be improved, and the testing time and cost can be shortened.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram of a system of an electronic device according to an embodiment of the invention. Please refer to the figure. In this embodiment, the electronic device 100 includes a power supply circuit 110, a flash memory 120, a processor 130, a test mode circuit 140, and peripheral components 150 and 160. The peripheral components 150 and 160 include at least a voltage-controlled oscillator. Voltage regulator, voltage regulator and reference voltage circuit. The flash memory 120 is coupled to the power circuit 110, the processor 130, the test mode circuit 140 and peripheral elements 150 and 160. The power circuit 110 is coupled to the processor 130, and the test mode circuit 140 is coupled to the peripheral elements 150 and 160.

In this embodiment, the electronic device 100 is activated in response to the power activation signal Pon, where the power activation signal Pon can be generated by an input interface (such as buttons, touch keys, switches, etc.) of the electronic device 100. Furthermore, the power circuit 110 responds to the power activation signal Pon to provide at least the system voltage Vdd to the flash memory 120, and the flash memory 120 responds to receiving the system voltage Vdd to start the initialization process.

During the initialization period, the power circuit 110 controls the reset pin of the processor 130 to be in a reset state. For example, the power circuit 110 can provide a reset signal HRESETn with a logic low level or a logic level of "0" to the processor 130 The reset pin.

In the initialization process, the flash memory 120 sequentially provides a plurality of initialization parameters DPc, DP1, DP2, DPT to the processor 130, peripheral components 150, 160 and the test mode circuit 140 to sequentially set the processor 130 and peripheral components Operating modes and operating states of 150, 160 and test mode circuit 140.

After the initialization process, that is, after the initialization period, the electronic device 100 responds to whether it receives (or generates) the test entry signal S_Test and determines whether to operate in the test mode or the user mode. The test entry signal S_Test can be transmitted through an input interface (for example, Pin) is input from the outside of the electronic device 100 or generated by the electronic device 100 itself.

Moreover, after the initialization process, the flash memory 120 can sequentially provide a plurality of data to the processor 130 and the test mode circuit 140. When the electronic device 100 receives (or generates) the test entry signal S_Test, the test mode circuit 140 is activated in response to the test entry signal S_Test, and the power circuit 110 responds to the test entry signal S_Test to reset the pin of the processor 130 Maintained in the reset state, that is, the reset signal HRESETn is maintained at the logic low level or the logic level “0”, so that the processor 130 is maintained in an inoperable state.

At this time, the data of the flash memory 120 will be provided to the processor 130 and the test mode circuit 140 as the test reference data DTS, but the processor 130 will not respond to the test reference data DTS, and the test mode circuit 140 will respond to the test entry The signal S_Test provides a plurality of test data D_Test1 and D_Test2 (such as input control signals of an analog circuit) based on the test reference data DTS to the peripheral components 150 and 160, respectively, to perform the testing of the peripheral components 150 and 160.

When the electronic device 100 does not receive (or does not generate) the test entry signal S_Test, the test mode circuit 140 is disabled in response to not receiving the test entry signal S_Test, and the power circuit 110 will respond to not receiving the test entry signal S_Test. The reset pin of the processor 130 is released from the reset state, that is, the reset signal HRESETn will change from the logic low level or the logic level "0" to the logic high level or the logic level "0", so that the processing The device 130 enters an operable state.

Then, the electronic device 100 will return to the boot process to restore the power supply of all components (such as the processor 130 and the peripheral components 150 and 160). After the boot process is completed, the user mode is entered. At this time, the processor 130 can access data from the flash memory 120 to execute the application program written into the flash memory 120 by the user.

According to the above, in the embodiment of the present invention, the data provided by the flash memory 120 is used as the test reference data DTS referenced by the test mode circuit 140 for testing, and there is no need to input test-related data from the electronic device 100. Therefore, when entering the test In the mode, the input pins can be omitted and most (or all) of the pins are used for output data (or test results). In this way, the testing capability of the electronic device 100 can be improved, and the testing time and cost can be shortened.

In the embodiment of the present invention, the test data D_Test1 and D_Test2 may be the first part of the corresponding test reference data DTS, respectively. In addition, the second part of the test reference data DTS can be used to instruct each of the test data D_Test1 and D_Test2 to be sent to the corresponding peripheral components 150, 160, that is, the second part of the test reference data DTS indicates the electronic device 100 Test items, the second part of the data is different from the first part of the data.

In the embodiment of the present invention, the test storage area Mtest for storing the test reference data DTS in the flash memory 120 is shared with the user, that is, the test storage area Mtest is not an area dedicated to the system, but the user can see and The area used. Therefore, before the testing of the peripheral components 150 and 160 is completed, the test storage area Mtest can store test-related data (that is, the test reference data DTS), and after the testing of the peripheral components 150 and 160 is completed, the test storage area Mtest is erased, In order to avoid affecting the user's available space.

In the embodiment of the present invention, a control circuit (not shown) may be configured in the electronic device 100 to control the flash memory 120 to output the initialization parameters DPc, DP1, DP2, DPT, and the timing of the test reference data DTS, that is, control The circuit (not shown) can sequentially provide the initialization parameters DPc, DP1, DP2, DPT, and the addresses corresponding to the test reference data DTS to the control flash memory 120. In other words, the control circuit (not shown) can respond to the system voltage Vdd to provide the addresses corresponding to the initialization parameters DPc, DP1, DP2, DPT, and the test reference data DTS. In the embodiment of the present invention, the control circuit (not shown) can be configured in the flash memory 120. In the embodiment of the present invention, the control circuit (not shown) can be activated in response to the system voltage Vdd, and can be disabled in response to the test entry signal S_Test.

FIG. 2 is a schematic diagram of a system of an electronic device according to another embodiment of the present invention. Please refer to FIGS. 1 and 2, where the electronic device 200 mainly shows the differences from the electronic device 100. In other words, the electronic device 200 further includes a latch circuit 210 and a multiplexer 230. The latch circuit 210 is coupled between the flash memory 120, the test mode circuit 140, and the processor 130 to provide one of the test reference data DTS to the test mode circuit 140 and process it in response to receiving the latch signal S_LAT The device 130, in response to the latch signal S_LAT, transmits a plurality of test reference data DTS to the test mode circuit 140 and the processor 130 one by one.

The multiplexer 230 has a first input terminal that receives an external signal S_Ext, a second input terminal that receives an internal clock signal Clk_I, a control terminal that receives a test entry signal S_Test, and an output terminal that provides a latch signal S_LAT, wherein the internal clock signal The Clk_I can be generated by a clock generator or an oscillator inside the electronic device 100, and the external signal S_Ext is input from the outside through the pins of the electronic device 200.

In the embodiment of the present invention, when the control terminal of the multiplexer 230 receives the test entry signal S_Test, the multiplexer 230 can provide the external signal S_Ext as the latch signal S_LAT, and the tester can control the electronic device through the external signal S_Ext. The speed (or rhythm) at which the 200 performs the test; when the control terminal of the multiplexer 230 does not receive the test entry signal S_Test, the multiplexer 230 may provide the internal clock signal Clk_I as the latch signal S_LAT.

The test mode circuit 140 is further coupled to the flash memory 120, and the test mode circuit 140 returns the third part data D_PAT3 of the test reference data DTS to the flash memory 120 to instruct the next test reference data to be read The address of the DTS, the third part of the data D_PAT3 is different from the first part and the second part of the test reference data DTS. In this way, when the electronic device 200 enters the test mode, the electronic device 200 will automatically perform a test action.

To sum up, in the electronic state of the embodiment of the present invention, the data provided through the flash memory is used as the test reference data for the test mode circuit test, and the test-related data does not need to be input from the electronic device. Therefore, when entering In the test mode, the input pins can be omitted and most (or all) of the pins can be used to output data (or test results). In this way, the testing capability of the electronic device can be improved, and the testing time and cost can be shortened.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100, 200: electronic device 110: Power supply circuit 120: flash memory 130: processor 140, 220: Test mode circuit 150, 160: Peripheral components 210: Latch Circuit 230: Multiplexer Clk_I: internal clock signal D_PAT3: The third part of the data D_Test1, D_Test2: test data Data: data DPc, DP1, DP2, DPT: initialization parameters DTS: Test Reference Materials HRESETn: reset signal Mtest: test storage area Pon: Power start signal S_Ext: external signal S_LAT: Latch signal S_Test: Test entry signal Vdd: system voltage

FIG. 1 is a schematic diagram of a system of an electronic device according to an embodiment of the invention. FIG. 2 is a schematic diagram of a system of an electronic device according to another embodiment of the present invention.

100: electronic device

110: Power supply circuit

120: flash memory

130: processor

140: Test mode circuit

150, 160: Peripheral components

D_Test1, D_Test2: test data

Data: data

DPc, DP1, DP2, DPT: initialization parameters

DTS: Test Reference Materials

HRESETn: reset signal

Mtest: test storage area

Pon: Power start signal

S_Test: Test entry signal

Vdd: system voltage

Claims (10)

An electronic device, including: Multiple peripheral components; A flash memory, providing multiple test reference materials; and A test mode circuit responds to a test entry signal and provides a plurality of test data based on the test reference data to the peripheral components to perform the test of the peripheral components. The electronic device as described in item 1 of the scope of patent application further includes: A processor with a reset pin; and A power circuit responds to the test entry signal to maintain the reset pin in a reset state. The electronic device according to claim 2, wherein the power circuit responds to a power activation signal to provide a system voltage to the flash memory, and the flash memory responds to receiving the system voltage to start an initialization process In the initialization procedure, the flash memory sequentially provides a plurality of initialization parameters to the processor, the peripheral components, and the test mode circuit. The electronic device described in item 3 of the scope of patent application, wherein the flash memory provides the test reference materials after the initialization process. For the electronic device described in item 3 of the scope of patent application, each of the test data is a first part of the corresponding test reference data. For the electronic device described in item 5 of the scope of patent application, a second part of each of the test reference data instructs each of the test data to be sent to the corresponding peripheral component, wherein the second part of the data is different from the The first part of the information. For the electronic device described in item 6 of the scope of patent application, a third part of each of the test reference data is returned to the flash memory to indicate the address of the test reference data to be read next. The electronic device described in item 2 of the scope of patent application includes: A latch circuit is coupled between the flash memory, the test mode circuit and the processor to provide one of the test reference data to the test mode circuit in response to receiving a latch signal And the processor. The electronic device as described in item 8 of the scope of patent application further includes: A multiplexer has a first input terminal for receiving an external signal, a second input terminal for receiving an internal clock signal, a control terminal for receiving the test entry signal, and an output terminal for providing the latch signal. For example, the electronic device described in item 9 of the scope of patent application, wherein when the control terminal receives the test entry signal, the multiplexer provides the external signal as the latch signal, and when the control terminal does not receive the test entry signal , The multiplexer provides the internal clock signal as the latch signal.

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