JP2023104478A - Reset circuit and semiconductor device - Google Patents

Abstract

To improve reliability and safety of a reset circuit.SOLUTION: A reset circuit 10 includes: a first detection unit 11 configured to generate a first detection signal UVLO1 by comparing a monitoring target voltage VREG (e.g., internal electrical power source voltage) with a first threshold voltage VH; a second detection unit 12 configured to generate a second detection signal UVLO2 by comparing the monitoring target voltage VREG with a second threshold voltage VL equal to or less than the first threshold voltage VH; a logical gate 13 configured to generate a reset signal RST on the basis of the first detection signal UVLO1 and the second detection signal UVLO2; and a third detection unit 14 configured to detect whether a logic level of the first detection signal UVLO1 is switched after a logic level of the second detection signal UVLO2 is switched, to generate a failure detection signal LAT.SELECTED DRAWING: Figure 4

Description

The invention disclosed in this specification relates to a reset circuit and a semiconductor device.

In recent years, many semiconductor devices include a reset circuit (also called a POR [power ON reset] circuit).

As an example of conventional technology related to the above, Patent Document 1 can be cited.

JP 2012-105190 A

However, conventional reset circuits have room for improvement in terms of their functional safety.

An object of the invention disclosed in the present specification is to provide a reset circuit and a semiconductor device with high reliability and safety in view of the above problems found by the inventors of the present application.

For example, the reset circuit disclosed herein includes: a first detector configured to compare a monitored voltage and a first threshold voltage to generate a first detection signal; and a second threshold voltage equal to or lower than the first threshold voltage to generate a second detection signal; and a reset based on the first detection signal and the second detection signal. and a logic gate configured to generate a fault detection signal by detecting whether the logic level of the first detection signal switches after the logic level of the second detection signal switches. and a configured third detector.

Other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description and accompanying drawings that follow.

According to the invention disclosed in this specification, it is possible to provide a reset circuit and a semiconductor device with high reliability and safety.

FIG. 1 is a diagram showing a comparative example of a semiconductor device having a reset circuit. FIG. 2 is a diagram illustrating normal operation of the reset circuit according to the comparative example. FIG. 3 is a diagram illustrating an abnormal operation of a reset circuit according to a comparative example; FIG. 4 is a diagram showing an embodiment of a semiconductor device with a reset circuit. FIG. 5 is a diagram illustrating normal operation of the reset circuit according to the embodiment. FIG. 6 is a diagram illustrating abnormal operation of the reset circuit according to the embodiment;

<Comparative example>
FIG. 1 is a diagram showing a comparative example of a semiconductor device including a reset circuit (=general configuration compared with embodiments described later). A semiconductor device 1 of this comparative example includes a reset circuit 10 and a logic circuit 20 .

The reset circuit 10 monitors whether the internal power supply voltage VREG (=monitored voltage) is in a low voltage abnormal state and outputs a reset signal RST to the logic circuit 20 . Referring to this drawing, the reset circuit 10 includes a first detection section 11 , a second detection section 12 and a logic gate 13 .

The first detection unit 11 compares an internal power supply voltage VREG input to a non-inverting input terminal (+) and a threshold voltage VTH input to an inverting input terminal (-) to generate a first detection signal UVLO1. It is a hysteresis comparator. The first detection signal UVLO1 becomes low level (=reset state logic level) when the internal power supply voltage VREG is lower than the threshold voltage VTH, and becomes high level (=reset state) when the internal power supply voltage VREG is higher than the threshold voltage VTH. release state logic level).

The second detection unit 12 compares the internal power supply voltage VREG input to the non-inverting input terminal (+) and the threshold voltage VTH input to the inverting input terminal (-) to generate a second detection signal UVLO2. It is a hysteresis comparator. The second detection signal UVLO2 becomes low level (=reset state logic level) when the internal power supply voltage VREG is lower than the threshold voltage VTH, and becomes high level (=reset state) when the internal power supply voltage VREG is higher than the threshold voltage VTH. release state logic level).

Thus, in the reset circuit 10 of this comparative example, not only the first detection section 11 but also the second detection section 12 as a safety mechanism (so-called SM [safety mechanism]) are provided in parallel.

The logic gate 13 generates a logical AND signal of the first detection signal UVLO1 and the second detection signal UVLO2, and outputs this as the reset signal RST. The reset signal RST becomes low level (=reset state logic level) when at least one of the first detection signal UVLO1 and the second detection signal UVLO2 is at low level (=reset state logic level), and becomes the first detection signal. When both the UVLO1 and the second detection signal UVLO2 are at high level (=logic level of reset release state), they become high level (=logic level of reset release state).

Logic circuit 20 operates by being supplied with internal power supply voltage VREG. The operating state of the logic circuit 20 is initialized according to the reset signal RST output from the reset circuit 10 . For example, when the internal power supply voltage VREG is lower than the threshold voltage VTH, the reset signal RST becomes low level, so that the logic circuit 20 is in a reset state (=stopped state). On the other hand, when the internal power supply voltage VREG is higher than the threshold voltage VTH, the reset signal RST becomes high level, so the logic circuit 20 enters the reset release state (=normal operation state).

Further, the logic circuit 20 outputs an error flag ERR indicating whether or not the semiconductor device 1 is out of order after the reset is canceled by the reset signal RST. For example, the error flag ERR becomes high level when a failure of the semiconductor device 1 is not detected, and becomes low level when a failure of the semiconductor device 1 is detected.

Note that the logic circuit 20 may output the error flag ERR actively (voluntarily), or may output the error flag ERR in response to a request from the host (such as MCU [micro controller unit]). .

FIG. 2 is a diagram showing a normal operation of the reset circuit 10 according to this comparative example (=a state in which neither the first detection unit 11 nor the second detection unit 12 is malfunctioning). VREG, first detection signal UVLO1, second detection signal UVLO2, reset signal RST, and error flag ERR are depicted.

When the semiconductor device 1 starts up and the internal power supply voltage VREG becomes higher than the threshold voltage VTH, both the first detection signal UVLO1 and the second detection signal UVLO2 rise from low level to high level. As a result, the reset signal RST rises to a high level, so that the logic circuit 20 enters the reset release state (=normal operation state). Therefore, the logic circuit 20 is ready to output the error flag ERR.

In this figure, since no failure has occurred in the semiconductor device 1, the error flag ERR is maintained at a high level (=logical level when no failure is detected).

FIG. 3 is a diagram showing an abnormal operation of the reset circuit 10 according to this comparative example (=a state in which the first detection unit 11 fails and the first detection signal UVLO1 is fixed at a high level). The internal power supply voltage VREG, the first detection signal UVLO1, the second detection signal UVLO2, the reset signal RST, the operating state of the logic circuit 20, and the error flag ERR are depicted.

When the semiconductor device 1 starts up and the internal power supply voltage VREG becomes higher than the threshold voltage VTH, the second detection signal UVLO2 rises from low level to high level. On the other hand, the first detection signal UVLO1 is always fixed at high level regardless of the internal power supply voltage VREG due to the failure of the first detection section 11 . As a result, the second detection signal UVLO2 is passed through as the reset signal RST. That is, when the second detection signal UVLO2 rises to high level, the reset signal RST also rises to high level, so that the logic circuit 20 enters the reset release state (=normal operation state). Therefore, the logic circuit 20 is ready to output the error flag ERR.

In this figure, although the semiconductor device 1 (especially the first detection section 11 of the reset circuit 10) has a failure, the logic circuit 20 has no means of detecting this, so the error flag ERR is at a high level (=failure logic level when not detected).

In the following, in view of the above considerations, a novel embodiment is proposed that can detect a failure of the first detector 11 .

<Embodiment>
FIG. 4 shows a novel embodiment of a semiconductor device with a reset circuit. The reset circuit 10 mounted on the semiconductor device 1 of this embodiment is based on the first embodiment (FIG. 1) and includes a third detector 14 and a threshold voltage generator 15 . Therefore, the same reference numerals as those in FIG. 1 are used for the components already mentioned to omit redundant description, and the characteristic portions of the present embodiment will be mainly described below.

The third detection unit 14 detects whether or not the logic level of the first detection signal UVLO1 switches from low level to high level after the logic level of the second detection signal UVLO2 switches from low level to high level. A detection signal LAT is generated. Referring to this figure, the third detector 14 includes a D flip-flop 14a and a delay stage 14b.

A high level signal is input to the data input terminal (D) of the D flip-flop 14a. The clock input terminal (>) of the D flip-flop 14a receives the first detection signal UVLO1 delayed by the delay stage 14b. A second detection signal UVLO2 is input to the reset input terminal (R) of the D flip-flop 14a. A failure detection signal LAT is output from the output terminal (Q) of the D flip-flop 14a.

The D flip-flop 14a connected as described above latches the first detection signal UVLO1 after the reset is released by the second detection signal UVLO2, and outputs the failure detection signal LAT.

Referring to this figure, when the second detection signal UVLO2 is at low level, the D flip-flop 14a is reset (=stopped) and the failure detection signal LAT is maintained at low level.

On the other hand, when the second detection signal UVLO2 is at high level, the D flip-flop 14a is in the reset release state (=normal operation state), and the first detection signal UVLO1 is latched out as the failure detection signal LAT. Specifically, the failure detection signal LAT rises from low level to high level triggered by the rise of the first detection signal UVLO1 (more precisely, the delayed signal of the first detection signal UVLO1) from low level to high level. , its logic level is latched.

The delay stage 14b delays the first detection signal UVLO1 input to the D flip-flop 14a. By providing such a delay stage 14b, even if pulse edges occur simultaneously (or substantially simultaneously) in both the first detection signal UVLO1 and the second detection signal UVLO2, the latch operation of the D flip-flop 14a will not be hindered. It becomes difficult to come. That is, the D flip-flop 14a can latch the first detection signal UVLO1 after the reset state is released by the second detection signal UVLO2.

It should be noted that the pulse edge timings of the first detection signal UVLO1 and the second detection signal UVLO2 can be shifted by providing a difference between the first threshold voltage VH and the second threshold voltage VL, which will be described later. Therefore, in this case, it is possible to omit the delay stage 14b. On the other hand, when the first threshold voltage VH and the second threshold voltage VL have the same value (or almost the same value), the pulse edge timings of the first detection signal UVLO1 and the second detection signal UVLO2 are close. Therefore, it is effective to provide the delay stage 14b in this case.

A threshold voltage generation unit 15 generates a first threshold voltage VH and a second threshold voltage VL (where VH≧VL) from a predetermined reference voltage VREF, and first detects each of the first threshold voltage VH and the second threshold voltage VL. Output to the unit 11 and the second detection unit 12 .

Referring to this figure, the threshold voltage generator 15 includes a plurality of resistors 15a, 15b, and 15c connected in series between the application terminal of the reference voltage VREF and the application terminal of the reference voltage (for example, the ground terminal). and outputs a first threshold voltage VH and a second threshold voltage VL from connection nodes between the resistors.

Along with the addition of the threshold voltage generation section 15 described above, the input signals of the first detection section 11 and the second detection section 12 are also changed.

Specifically, the first detection unit 11 compares the internal power supply voltage VREG input to the non-inverting input terminal (+) with the first threshold voltage VH input to the inverting input terminal (-). A first detection signal UVLO1 is generated. Therefore, the first detection signal UVLO1 becomes low level (=reset state logic level) when the internal power supply voltage VREG is lower than the first threshold voltage VH, and when the internal power supply voltage VREG is higher than the first threshold voltage VH. becomes high level (=logic level of reset release state).

Further, the second detection unit 12 compares the internal power supply voltage VREG input to the non-inverting input terminal (+) with the second threshold voltage VL input to the inverting input terminal (-) to generate a second detection signal. Generate UVLO2. Therefore, the second detection signal UVLO2 becomes low level (=reset state logic level) when the internal power supply voltage VREG is lower than the second threshold voltage VL, and when the internal power supply voltage VREG is higher than the second threshold voltage VL. becomes high level (=logic level of reset release state).

FIG. 5 is a diagram showing normal operation of the reset circuit 10 according to the present embodiment (=a state in which neither the first detection unit 11 nor the second detection unit 12 is malfunctioning). VREG, first detection signal UVLO1, second detection signal UVLO2, reset signal RST, failure detection signal LAT, and error flag ERR are depicted.

When the semiconductor device 1 starts up and the internal power supply voltage VREG becomes higher than the second threshold voltage VL, the second detection signal UVLO2 rises from low level to high level. When the internal power supply voltage VREG further rises and becomes higher than the first threshold voltage VH, the first detection signal UVLO1 rises from low level to high level. As a result, the reset signal RST rises to a high level, so that the logic circuit 20 enters the reset release state (=normal operation state). Therefore, the logic circuit 20 is ready to output the error flag ERR.

Focusing on the operation of the third detector 14, when the second detection signal UVLO2 rises from the low level to the high level, the D flip-flop 14a enters the reset release state (=normal operation state). Triggered by the rise of the 1 detection signal UVLO1 (more precisely, the delayed signal of the first detection signal UVLO1) from the low level to the high level, the failure detection signal LAT is latched to the high level.

Note that in this figure, for convenience of explanation, the delay given to the first detection signal UVLO1 by the delay stage 14b is ignored, and at the same time (or almost at the same time) the first detection signal UVLO1 rises from the low level to the high level. , the failure detection signal LAT is latched to a high level.

The logic circuit 20 checks the failure detection signal LAT after the reset is released by the reset signal RST, and outputs an error flag ERR indicating whether or not the semiconductor device 1 has failed. In this figure, since the failure detection signal LAT has correctly risen to a high level and no other failure has occurred in the semiconductor device 1, the error flag ERR is maintained at a high level (=logical level when no failure is detected). there is

FIG. 6 is a diagram showing an abnormal operation of the reset circuit according to the embodiment (=a state in which the first detection unit 11 fails and the first detection signal UVLO1 is fixed at a high level). A voltage VREG, a first detection signal UVLO1, a second detection signal UVLO2, a reset signal RST, a fault detection signal LAT, and an error flag ERR are depicted.

When the semiconductor device 1 starts up and the internal power supply voltage VREG becomes higher than the second threshold voltage VL, the second detection signal UVLO2 rises from low level to high level. On the other hand, the first detection signal UVLO1 is always fixed at high level regardless of the internal power supply voltage VREG due to the failure of the first detection section 11 . As a result, the second detection signal UVLO2 is passed through as the reset signal RST. That is, when the second detection signal UVLO2 rises to high level, the reset signal RST also rises to high level, so that the logic circuit 20 enters the reset release state (=normal operation state). Therefore, the logic circuit 20 is ready to output the error flag ERR.

Focusing on the operation of the third detector 14, when the second detection signal UVLO2 rises from the low level to the high level, the D flip-flop 14a enters the reset release state (=normal operation state), and the first detection is performed. The signal UVLO1 is now ready to be latched out. However, as described above, the first detection signal UVLO1 is always fixed at high level. Therefore, the failure detection signal LAT is maintained at a low level without being latched to a high level.

The logic circuit 20 checks the failure detection signal LAT after the reset is released by the reset signal RST, and outputs an error flag ERR indicating whether or not the semiconductor device 1 has failed. In this figure, since the failure detection signal LAT is maintained at a low level, the logic circuit 20 sets the error flag ERR to inform the reset circuit 10 (especially the first detection section 11) that some failure has occurred. switch to low level (=logical level at the time of fault detection).

As described above, the logic circuit 20 may actively (spontaneously) output the error flag ERR, or output the error flag ERR in response to a request from the host (MCU, etc.). may

As described above, the reset circuit 10 of the present embodiment can notify the logic circuit 20 of its own failure. Therefore, it is possible to improve the reliability and safety of the reset circuit 10 (and the semiconductor device 1 in which it is mounted).

<Summary>
The following provides a general description of the various embodiments described above.

For example, the reset circuit disclosed herein includes: a first detector configured to compare a monitored voltage and a first threshold voltage to generate a first detection signal; and a second threshold voltage equal to or lower than the first threshold voltage to generate a second detection signal; and a reset based on the first detection signal and the second detection signal. and a logic gate configured to generate a fault detection signal by detecting whether the logic level of the first detection signal switches after the logic level of the second detection signal switches. and a configured third detection unit (first configuration).

In the reset circuit having the first configuration, the third detection section is a flip-flop configured to latch the first detection signal and output the failure detection signal after the reset is canceled by the second detection signal. A configuration (second configuration) including a loop may be employed.

Further, in the reset circuit according to the second configuration, the third detection section further includes a delay stage configured to delay the first detection signal input to the flip-flop (third configuration).

Further, the reset circuit according to any one of the first to third configurations further includes a threshold voltage generator configured to generate the first threshold voltage and the second threshold voltage from a predetermined reference voltage ( 4th configuration).

In the reset circuit according to the fourth configuration, the threshold voltage generator includes a plurality of resistors connected in series between the reference voltage application terminal and the reference voltage application terminal, and the connection between the resistors A configuration (fifth configuration) in which the first threshold voltage and the second threshold voltage are output from a node may be employed.

In the reset circuit having any one of the first to fifth configurations, the first detection section and the second detection section may each be a hysteresis comparator (sixth configuration).

Further, for example, the semiconductor device disclosed in this specification includes a reset circuit having any one of the first to sixth configurations, and a logic circuit configured to operate by being supplied with the voltage to be monitored. and a configuration (seventh configuration).

In the semiconductor device according to the seventh configuration, the logic circuit may have a configuration (eighth configuration) in which an operating state is initialized according to the reset signal output from the reset circuit.

In the semiconductor device according to the seventh or eighth configuration, the logic circuit monitors the failure detection signal after the reset is canceled by the reset signal, and an error flag indicates whether or not the reset circuit has failed. may be configured to output (ninth configuration).

In the semiconductor device according to the ninth configuration, the logic circuit may output the error flag in response to a request from the host (tenth configuration).

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is defined by the claims, It should be understood that all changes that come within the meaning and range of equivalency of the claims are included.

1 semiconductor device 10 reset circuit 11 first detector 12 second detector 13 logic gate 14 third detector 14a D flip-flop 14b delay stage 15 threshold voltage generator 15a, 15b, 15c resistor 20 logic circuit

Claims (10)

a first detector configured to compare the monitored voltage and the first threshold voltage to generate a first detection signal;
a second detection unit configured to generate a second detection signal by comparing the monitored voltage with a second threshold voltage equal to or lower than the first threshold voltage;
a logic gate configured to generate a reset signal based on the first detection signal and the second detection signal;
a third detection unit configured to detect whether or not the logic level of the first detection signal switches after the logic level of the second detection signal switches to generate a failure detection signal;
a reset circuit. 2. The reset circuit according to claim 1, wherein said third detection unit includes a flip-flop configured to latch said first detection signal and output said failure detection signal after reset is released by said second detection signal. . 3. The reset circuit according to claim 2, wherein said third detector further includes a delay stage configured to delay said first detection signal input to said flip-flop. 4. The reset circuit according to any one of claims 1 to 3, further comprising a threshold voltage generator configured to generate said first threshold voltage and said second threshold voltage from a predetermined reference voltage. The threshold voltage generator includes a plurality of resistors connected in series between the reference voltage application terminal and the reference voltage application terminal, and the first threshold voltage and the second threshold voltage are generated from a connection node between the resistances. 5. The reset circuit of claim 4, which outputs a voltage. 6. The reset circuit according to claim 1, wherein each of said first detection section and said second detection section is a hysteresis comparator. a reset circuit according to any one of claims 1 to 6;
a logic circuit configured to operate by being supplied with the monitored voltage;
A semiconductor device comprising: 8. The semiconductor device according to claim 7, wherein said logic circuit has an operating state initialized according to said reset signal output from said reset circuit. 9. The semiconductor device according to claim 7, wherein said logic circuit outputs an error flag indicating whether or not said semiconductor device is faulty after reset is released by said reset signal. 10. The semiconductor device according to claim 9, wherein said logic circuit outputs said error flag in response to a request from a host.

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