JP7463952B2 - Overcurrent detection circuit and switching power supply circuit - Google Patents

Description

The present invention relates to an overcurrent detection circuit and a switching power supply circuit.

For example, when detecting an overcurrent in a switching power supply circuit that generates power by driving a switching element, the current waveform that flows during switching operation is not constant, but increases and decreases with the switching cycle, so the current detection output becomes pulsed. For this reason, a detection counter using a flip-flop circuit is provided as a configuration for maintaining the monitored current state, and when the overcurrent detection signal is counted a certain number of times in succession, an overcurrent state is determined.

This makes it possible to reliably determine overcurrent and activate the protection functions of switching elements and circuits while preventing false detection due to single current changes caused by noise, etc., during intermittent current detection that accompanies switching operations.

However, in the above-mentioned overcurrent detection judgment technology, if the overcurrent detection signal cannot be properly received due to the influence of noise or the like, resulting in a low current level, an erroneous detection state will occur in which the overcurrent detection signal is not continuously detected. As a result, it may be determined that the overcurrent is not detected, and the detection counter may count down or be reset.

For this reason, even if an overcurrent is actually flowing, such a false detection state continues, resulting in a problem of delaying the protective action of the switching element.
Moreover, this problem occurs not only in switching power supply circuits but also in series power supply circuits in which overcurrent detection is performed periodically.

JP 2012-10577 A Japanese Patent Application Laid-Open No. 11-24762

The present invention has been made in consideration of the above circumstances, and its purpose is to provide an overcurrent detection circuit and a switching power supply circuit using such an overcurrent detection circuit, which periodically detects overcurrent, increases or decreases a count value depending on the presence or absence of a detection signal, and determines that an overcurrent state is present when a predetermined count value is reached, so that an overcurrent state can be quickly determined even when an undetected state occurs due to a missed overcurrent detection signal,

The overcurrent detection circuit according to claims 1 and 2 is an overcurrent detection circuit for detecting an overcurrent flowing through a semiconductor element and performing a protective operation, comprising an overcurrent detection unit (22) for detecting the current flowing through the semiconductor element at a predetermined cycle and outputting an overcurrent detection signal when the current exceeds an overcurrent detection level, and a determination unit (21) for incrementing a count value depending on whether there is an overcurrent detection signal from the overcurrent detection unit and decrementing the count value depending on whether there is no overcurrent detection signal, and determining an overcurrent state when the count value reaches a determination count value, wherein the determination unit sets the number of increments per unit time to be greater than the number of decrements per unit time . In the overcurrent detection circuit according to claim 1, the determination unit increments the count value and performs the next overcurrent detection at the predetermined cycle when there is an overcurrent detection signal from the overcurrent detection unit, and decrements the count value and performs the next overcurrent detection at a cycle longer than the predetermined cycle when there is no overcurrent detection signal. In the overcurrent detection circuit according to claim 2, the judgment unit counts up a count value when the overcurrent detection signal from the overcurrent detection unit is generated once or multiple times in succession, and counts down the count value when the overcurrent detection signal is generated multiple times in succession that is greater than the counting time.

By adopting the above configuration, the overcurrent detection unit outputs an overcurrent detection signal when the current flowing through the semiconductor element exceeds the overcurrent detection level, and the determination unit increments the count value when the overcurrent detection signal is output, decrements the count value when the overcurrent detection signal is not output, and determines an overcurrent state when the count value reaches a determination count value. At this time, the determination unit sets the rate of incrementing the count value per time to be greater than the rate of decrementing the count value per time, so that even in cases where a false detection occurs in an overcurrent state and a state in which the overcurrent detection signal is output alternates with a state in which it is not output, the count value can be increased and an overcurrent state can be determined quickly.

Electrical configuration diagram showing the first embodiment 1 is a timing chart showing a first embodiment; Electrical configuration diagram showing the second embodiment Timing chart showing the second embodiment Electrical configuration diagram showing a third embodiment

First Embodiment
A first embodiment in which the present invention is applied to a switching power supply circuit will be described below with reference to FIGS.

In FIG. 1, which shows the electrical configuration, a power stage 100 constituting a step-down switching power supply circuit is driven and controlled by a switching drive circuit 10. The switching drive circuit 10 includes an overcurrent detection circuit 20.

The power stage 100 comprises a MOS transistor 1 as a switching semiconductor element, a resistor 2 for current detection, a diode 3, a coil 4, and a capacitor 5. Here, for example, a P-channel type MOS transistor is used as the MOS transistor 1. The source of the MOS transistor 1 is connected to the power supply terminal of the DC power supply Vcc via the resistor 2, and the drain is connected to ground GND via the diode 3 in the reverse direction, and is also connected to ground GND via the coil 4 and the capacitor 5. The common connection point of the capacitor 5 and the coil 4 is connected to the output terminal of the output voltage Vout.

The switching drive circuit 10 includes the above-mentioned overcurrent detection circuit 20, as well as a switching control circuit 11, a drive circuit 12, and a protection circuit 13. The switching control circuit 11 is given a clock signal CLK, and the output voltage Vout is input via a monitor terminal VOM. The switching control circuit 11 outputs a drive signal to the drive circuit 12 at the cycle of the clock signal CLK so that the output voltage Vout becomes a set voltage level.

The drive circuit 12 outputs a gate drive signal to the gate of the MOS transistor 1 via the terminal VG in response to the drive signal provided by the switching control circuit 11. This causes the MOS transistor 1 to be controlled to be turned on and off at the cycle of the clock signal CLK. When a signal indicating that the drive circuit is in an overcurrent state is input from the overcurrent detection circuit 20, the protection circuit 13 controls the drive output of the drive circuit 12 to perform a protection operation for the MOS transistor 1.

The overcurrent detection circuit 20 includes an overcurrent judgment unit 21 as a judgment unit and a comparator 22 as an overcurrent detection unit. The source voltage Vs of the MOS transistor 1 is input to the inverting input terminal of the comparator 22. The reference voltage Vref is also applied to the non-inverting input terminal of the comparator 22. The reference voltage Vref is set to the voltage when the current Id of the MOS transistor 1 becomes the overcurrent detection level Ioc.

When the current Id flowing through the MOS transistor 1 exceeds the overcurrent detection level Ioc, the source voltage Vs of the MOS transistor 1 falls below the reference voltage Vref, so the comparator 22 outputs a high-level detection signal. The overcurrent determination unit 21 includes a counter and a control unit that controls the count value.

The overcurrent determination unit 21 synchronizes the detection signal input from the comparator 22 with the clock signal CLK, instructs the counter to count the count value set by the control unit, and executes counting to increase or decrease, and determines an overcurrent state as described below. When the overcurrent determination unit 21 determines an overcurrent state, it outputs an overcurrent determination signal to the protection circuit 13.

The protection circuit 13 is designed to take into consideration the tolerance of the semiconductor elements and system requirements as a protection operation, and to control the switching control circuit 11 and the MOS transistor 1 so that they do not break down or malfunction.

Examples of the protective operations performed by the protection circuit 13 include the following operations (a) to (e). The configuration may include any one of these protective operations, or may include other protective operations.

(a) The output voltage Vout is completely stopped.
(b) After the output voltage Vout is stopped, it is restarted after a certain time has elapsed.
(c) Repeating the stopping operation and switching operation of the output voltage Vout.
(d) After repeating the above-mentioned operation (b) or (c) a certain number of times, the operation is completely stopped. (e) The control state is switched to one in which the maximum output current is limited, and output is performed.

Next, the operation of the above configuration will be described with reference to FIG.
2 is a time chart for explaining the determination operation in the overcurrent determination unit 21 of the overcurrent detection circuit 20. In this embodiment, three patterns, 1 to 3, are shown as patterns of the determination operation. For comparison, FIG. 2 also shows comparative patterns 1 and 2, which are patterns of the determination operation equivalent to the conventional method.

First, we will explain the normal operating state where no overcurrent flows. When a drive command is given to the switching drive circuit 10 of the power stage 100, the switching control circuit 11 outputs a drive signal to the drive circuit 12 at the cycle of the clock signal CLK. At this time, the switching control circuit 11 monitors the output voltage Vout of the power stage 100 and performs feedback control so that this voltage becomes a predetermined voltage.

In this state, the overcurrent detection circuit 20 takes in the source voltage Vs of the MOS transistor 1 and determines whether the current Id of the MOS transistor 1 has reached the overcurrent detection level. The current Id of the MOS transistor 1 causes a voltage drop across the current detection resistor 2, so when the source voltage Vs falls below the reference voltage Vref, it can be detected that an overcurrent is flowing.

In FIG. 2, the overcurrent state is detected with the overcurrent detection level Ioc set to the current Id of MOS transistor 1 as the reference. When MOS transistor 1 is turned on at timings t0, t1, ... in accordance with the cycle of the clock CLK, the current Id increases, but in a normal state it does not reach the overcurrent detection level Ioc before the next cycle begins.

However, if some change in circumstances causes the current Id of MOS transistor 1 to increase to an overcurrent level, it will exceed the overcurrent detection level Ioc before the next period begins, and the comparator 22 will output a high-level overcurrent detection signal to the overcurrent determination unit 21.

Next, in the overcurrent determination unit 21, in a normal state where no overcurrent is detected, the instruction to the counter is a decrement count, and the counter value of the counter is maintained at "0."

<First pattern>
In the first pattern, when an overcurrent detection signal is output, the count value is incremented, and in the next period, the count value is incremented or decremented again depending on whether an overcurrent detection signal is output or not. When an overcurrent detection signal is not output, the count value is decremented, and in the next period, the count value is maintained regardless of whether an overcurrent detection signal is output or not.

As described above, when an overcurrent starts to flow through MOS transistor 1, in a period after time t0, when current Id exceeds overcurrent detection level Ioc, an overcurrent detection signal is output. At this time, in the first pattern, the overcurrent determination unit 21 counts up and down the count value as follows.

First, when the overcurrent detection signal is output four times in succession from time t0 to time t3, the overcurrent determination unit 21 increments the count value by "1" at each detection timing. This causes the count value to increase sequentially to "1," "2," "3," and "4."

After that, if the current value is small due to an erroneous signal caused by noise or the like in the cycle at time t4 and the overcurrent detection signal is not output, the overcurrent determination unit 21 decrements the count value by "1" to make it "3." In this way, after the count value is decremented without the overcurrent detection signal being output, the overcurrent determination unit 21 does not perform a determination in the next cycle at time t5 regardless of the presence or absence of an overcurrent detection signal, and maintains the counter value at "3."

After that, in the cycle of time t6, if an overcurrent detection signal is output as shown in the figure, the overcurrent determination unit 21 counts up the counter value to set the count value to "4". Note that, in the cycle of time t6, if an overcurrent detection signal is not output, the overcurrent determination unit 21 counts down the counter value to set the count value to "2".

After this, when the current Id becomes unaffected by noise and the overcurrent detection signal is output continuously again from the cycle at time t6 onwards, the overcurrent determination unit 21 increments the count value by "1" each cycle to "4", "5", and "6". As a result, the count value at time t9 becomes "6", which is the overcurrent determination value, so the overcurrent determination unit 21 outputs a determination signal to the protection circuit 13 to perform a protection operation.

As described above, in the first pattern, the overcurrent determination unit 21 performs an increment count when an overcurrent detection signal is detected, and when an overcurrent detection signal is not detected, the determination period after the decrement count is doubled, so that the number of increment counts per unit time increases.

As a result, delays in determining the overcurrent state, which may occur when an overcurrent detection signal is output and when there is no overcurrent detection signal due to erroneous detection caused by noise or the like, can be prevented, and the overcurrent state can be determined reliably and quickly. As a result, the time between determining the overcurrent state and protective action can be prevented from becoming long, and damage to the MOS transistor 1 and each circuit can be reduced.

<Second pattern>
In the second pattern, when an overcurrent detection signal is output, the count value is incremented, and when the overcurrent detection signal is not output twice in succession, the count value is decremented.

Similarly to the above, assume that there is an overcurrent detection signal generation pattern as shown in FIG. 2. When the overcurrent detection signal is output four times in succession from time t0 to t3, the overcurrent determination unit 21 increments the count value by "1" at each detection timing. This causes the count value to increase sequentially to "1," "2," "3," and "4."

After that, if the current value is small due to an erroneous signal caused by noise or the like in the cycle between times t4 and t5 and the overcurrent detection signal is not output continuously, the overcurrent determination unit 21 will keep the count value at "4" at time t5, and will decrement the count value to "1" at time t6, making the count value "3."

After that, if an overcurrent detection signal is output in the cycle of time t7, the overcurrent determination unit 21 increments the counter value to set the count value to "4". If an overcurrent detection signal is not output in the cycle of time t7, the overcurrent determination unit 21 keeps the counter value at "3".

After this, when the current Id becomes unaffected by noise and the overcurrent detection signal is output continuously again from the cycle at time t7 onwards, the overcurrent determination unit 21 increments the count value by "1" each cycle to "4", "5", and "6". As a result, the count value becomes "6", which is the overcurrent determination value, so the overcurrent determination unit 21 outputs a determination signal to the protection circuit 13 to perform a protection operation.

As described above, in the second pattern, the overcurrent determination unit 21 increments the count value when an overcurrent detection signal is output, and decrements the count value when the overcurrent detection signal is not output twice in succession, resulting in a state in which the number of increments per time is set large. As a result, it is possible to obtain the same effect as in the first pattern.

<Third pattern>
In the third pattern, when an overcurrent detection signal is output, the count value is incremented by "2," and when an overcurrent detection signal is not output, the count value is decremented by "1." In this pattern, the overcurrent determination value is set to a count value of "12."

Similarly to the above, assume that there is an overcurrent detection signal generation pattern as shown in FIG. 2. When the overcurrent detection signal is output four times in succession from time t0 to t3, the overcurrent determination unit 21 increments the count value by "2" at each detection timing. This causes the count value to increase sequentially to "2," "4," "6," and "8."

After that, if the current value is small due to an erroneous signal caused by noise or the like during the cycle of times t4 and t5, and the overcurrent detection signal is not output continuously, the overcurrent determination unit 21 will decrement the count value by "1" at time t5 to make it "7", and then decrement the count value by "1" again at the next time t6 to make it "6".

After that, if an overcurrent detection signal is output in the cycle of time t6, the overcurrent determination unit 21 increments the counter value by "2" and sets the count value to "8" at the timing of time t7. If an overcurrent detection signal is not output, the overcurrent determination unit 21 decrements the counter value to "5" at the timing of time t7.

After this, when the current Id becomes unaffected by noise and the overcurrent detection signal is output continuously again from the cycle at time t7 onwards, the overcurrent determination unit 21 increments the count value by "2" each cycle to "10" and "12". As a result, the count value becomes "12", the overcurrent determination value, at the timing of time t9, so the overcurrent determination unit 21 outputs a determination signal to the protection circuit 13 to perform a protection operation.

As described above, in the third pattern, when the overcurrent detection signal is output by the overcurrent determination unit 21, the count value is incremented by "2", and when the overcurrent detection signal is not output, the count value is decremented by "1", resulting in a state in which the number of increments per time is set large. As a result, it is possible to obtain the same effect as in the first pattern.

In addition, compared to the three patterns in this embodiment described above, in the two comparison patterns 1 and 2 of the conventional method shown in Figure 2, it can be seen that there are cases where the determination of the overcurrent state is delayed for the same output pattern of the overcurrent detection signal.

In other words, in comparison pattern 1, the counter counts by adding up during the period when the overcurrent detection signal is output from the comparator in the overcurrent detection circuit, and resetting the count value to "0" during the period when the overcurrent detection signal is not output. In this method, when the output pattern of the overcurrent detection signal shown in Figure 2 occurs, the overcurrent state is determined to be present at time t13, which is significantly later than the time t10 determined in patterns 1 to 3.

In addition, in comparison pattern 2, the counter counts by incrementing the count value during periods when the overcurrent detection signal is output from the comparator in the overcurrent detection circuit, and decrementing the count value during periods when the overcurrent detection signal is not output. In this method, when the output pattern of the overcurrent detection signal shown in Figure 2 occurs, the overcurrent state is determined to be at time t11, which is later than the time t10 determined in patterns 1 to 3.

According to the first embodiment, in the overcurrent detection circuit 20, the rate of the increment count of the counter by the overcurrent determination unit 21 is set to a value greater than the rate of the decrement count, so that the overcurrent state can be quickly determined even in cases where a false detection occurs in an overcurrent state, causing alternating states in which the overcurrent detection signal is output and not output.

The above-mentioned counter's increment and decrement ratios can be set in three different ways, the first to third patterns below, allowing for a variety of setting directions.

That is, in the first pattern, the count period during subtractive counting is set longer than the count period during incremental counting, in the second pattern, the number of times the overcurrent detection signal goes undetected during subtractive counting is set greater than the number of times the overcurrent detection signal is output during incremental counting, and in the third pattern, the count value during incremental counting is set greater than the count value during subtractive counting.

In the above embodiment, in the first pattern, when there is an overcurrent detection signal from the overcurrent detection unit, the count value is incremented and the next overcurrent detection is performed at a predetermined cycle, and when there is no overcurrent detection signal, the count value is decremented and the next overcurrent detection is performed at a cycle longer than the predetermined cycle.

In addition, in the second pattern, the count value may be incremented when the overcurrent detection signal from the overcurrent detection unit is generated once or multiple times in succession, and the count value may be decremented when the overcurrent detection signal is generated multiple times in succession that is greater than the increment count.

In the third pattern, when an overcurrent detection signal is detected by the overcurrent detection unit, m count values are counted up, and when an overcurrent detection signal is not detected, n count values less than m (n < m) are counted down.
In addition, in the above embodiment, the overcurrent determination value is set to "6" or "12", but these are merely examples, and any appropriate overcurrent determination value can be set.

Second Embodiment
3 and 4 show the second embodiment, and the following describes the differences from the first embodiment. In this embodiment, multiple overcurrent detection levels are set, and the number of counts added is set differently depending on the level. This allows the counter value to be increased more quickly when a large current is detected, and enables the overcurrent state to be determined more quickly when the large current state continues.

Figure 3 shows the electrical configuration, and the overcurrent detection circuit 20a of the switching drive circuit 10a includes an overcurrent determination unit 21a, a first comparator 23a, and a second comparator 23b. The two comparators 23a and 23b function as a first overcurrent detection unit and a second overcurrent detection unit, and the source voltage Vs of the MOS transistor 1 is input to the inverting input terminal of both comparators.

The first comparator 23a, like the comparator 22 of the first embodiment, receives a first reference voltage Vref1, which is at the same level as the reference voltage Vref, at its non-inverting input terminal. The second comparator 23b receives a second reference voltage Vref2, which is set to be higher than the first reference voltage Vref1, at its non-inverting input terminal.

The first comparator 22 detects an overcurrent state in which a current Id of the first overcurrent detection level Ioc1, the same as in the first embodiment, flows based on the first reference voltage Vref1, and the second comparator 23 detects an overcurrent state in which a current Id of the second overcurrent detection level Ioc2, which is greater than the first overcurrent detection level Ioc1, flows based on the second reference voltage Vref2.

The overcurrent determination unit 21a adds an additional count value of "1" when the first overcurrent detection signal is input from the first comparator 23a, and adds an additional count value of "2" when the second overcurrent detection signal is input from the second comparator 23b. If neither the first nor second overcurrent detection signal is output from the two comparators 23a, 23b, the subtraction count value of "1" is subtracted.

Next, the operation of the above configuration will be described with reference to FIG.
4 is a time chart for explaining the determination operation in the overcurrent determination unit 21a of the overcurrent detection circuit 20a. The detection pattern is shown as the fourth pattern. For comparison, FIG. 4 also shows the comparative pattern 2 corresponding to the conventional technique.

This shows a case where the same current Id as in the first embodiment flows, and in this embodiment, the first or second overcurrent detection signal is output at two detection levels. The first overcurrent detection level Ioc1 is the same level as in the first embodiment, so a similar overcurrent detection signal is output as the first overcurrent detection signal. The second overcurrent detection level Ioc2 is a level greater than the first overcurrent detection level Ioc1, and is detected here at times t3 and in each of the cycles t6-t9, and is output as the second overcurrent detection signal. In the cycles of times t4 and t5, an overcurrent state occurs due to erroneous detection, but neither the first nor the second overcurrent detection signal is output.

As shown in FIG. 4, the first overcurrent detection signal is output four times in succession over the period from time t0 to t3, and overcurrent detection signal 2 is also output during the period from time t3. Then, the overcurrent determination unit 21a increments the count value by "1" at the detection timing of three periods from time t0 to t2, and increments the count value by "2" at the detection timing of time t4. This causes the count value to increase to "1", "2", "3", and "5".

After that, if the current value becomes small due to an erroneous signal caused by noise or the like during the cycles of time t4 and t5, and neither the first nor the second overcurrent detection signal is output continuously, the overcurrent determination unit 21a will sequentially decrement the count value by "1" at each of times t5 and t6, decreasing it to "4" and then "3."

In reality, the current Id of MOS transistor 1 exceeds the second overcurrent detection level Ioc2, so when the first and second overcurrent detection signals are output without erroneous detection in the following cycles at times t6 and t7, the overcurrent determination unit 21a increments the count value by "2" at times t7 and t8, respectively. As a result, the count value increases to "5" and then "7".

As a result, at time t8, the count value exceeds the overcurrent judgment value of "6", so the overcurrent judgment unit 21a outputs a judgment signal to the protection circuit 13 to perform a protection operation.

In the second embodiment, as a fourth pattern, the overcurrent determination unit 21a increments the count value by "1" when the first overcurrent detection signal is output, increments the count value by "2" when the second overcurrent detection signal is output, and decrements the count value by "1" when neither the first nor second overcurrent detection signal is output.

This results in a state in which the number of counts added per time is set large. As a result, it is possible to obtain the same effect as in the case of the first pattern. Furthermore, when a large overcurrent that exceeds the second overcurrent detection level Ioc2 flows, the count value is increased by "2", making it possible to quickly determine the overcurrent state.

In the above embodiment, the count value added in response to the output of the first and second overcurrent detection signals is not limited to "1" or "2", and can be set to an appropriate count value as long as the condition for increasing the count value in response to the output of the second overcurrent detection signal is satisfied.

Third Embodiment
5 shows the third embodiment, and the following describes the differences from the first embodiment. In this embodiment, a configuration example is combined with the switching driver circuit 10b that can prevent overboost due to an open circuit abnormality of the monitor terminal VOM when the switching driver circuit 10b is started.

As shown in FIG. 5, in addition to the configuration of the first embodiment, this embodiment includes an overvoltage detection circuit 14 that monitors the output voltage Vout and detects overvoltage, a startup control circuit 15 that switches control at startup, and a light load control circuit 16 that increases the current only under light load to improve power supply characteristics. It also includes a MOS transistor 17 that is turned on and off by the light load control circuit 16.

The output terminal of the power stage 100 is connected to the bleed terminal BREED of the switching drive circuit 10b via a resistor 6 in order to discharge the charge in the capacitor 5. The output terminal of the power stage 100 is connected to the overvoltage detection circuit 14 via a monitor terminal VOM, and the output voltage Vout is also monitored from the bleed terminal BREED.

The light-load control circuit 16 receives the source voltage Vs from the overcurrent detection terminal OC and detects a light-load state in which the current Id of the MOS transistor 1 drops below a predetermined level. When the light-load control circuit 16 determines that a light-load state exists, it turns on the MOS transistor 17 to discharge the charge in the capacitor 5, thereby preventing the potential of the output terminal Vout from rising.

The startup control circuit 15 prevents overvoltage from being applied to the load by causing the feedback control to go into full-on operation when the power supply is started up if the monitor terminal VOM is in an open state. During startup, the light load control circuit 16 is turned off, and the voltage of the bleed terminal BREED is monitored to detect an open circuit abnormality in the monitor terminal VOM based on the potential difference between the monitor terminal VOM and the bleed terminal BREED.

According to the third embodiment, in addition to determining an overcurrent state, it is also possible to detect an overvoltage state and perform control at startup, so that the drive control of the power stage 100 by the switching drive circuit 10b can perform protective operations with higher functionality.

Other Embodiments
The present invention is not limited to the above-described embodiment, but can be applied to various embodiments without departing from the spirit of the present invention, and can be modified or expanded as follows, for example.

In each of the above embodiments, a P-channel MOSFET is used as the MOS transistor 1, but an N-channel MOSFET can also be used. In this case, the source and drain are reversed, so that the drain voltage Vd is input to the comparator 22 instead of the source voltage Vs, but basically the same detection principle can be implemented.

In the above embodiments, the overcurrent detection circuits 20 and 20a are applied to the switching power supply circuits 10, 10a and 10b, but they can also be used to detect overcurrent in semiconductor elements of a series power supply. In this case, they can be applied to an overcurrent detection circuit configured to periodically perform overcurrent detection operations.

In each of the above embodiments, a configuration using a MOS transistor 1 as a semiconductor element has been shown, but it can also be applied to a power stage using an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor.

Although the present disclosure has been described with reference to the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

In the drawing, 1 is a MOS transistor (semiconductor element), 10, 10a, and 10b are switching drive circuits, 11 is a switching control circuit, 12 is a drive circuit, 13 is a protection circuit, 14 is an overvoltage detection circuit, 20 and 20a are overcurrent detection circuits, 21 and 21a are overcurrent judgment units (judgment units), 22 is a comparator (overcurrent detection unit), 23a is a first comparator (first overcurrent detection unit), 23b is a second comparator (second overcurrent detection unit), and 100 is a power stage.

Claims (4)

An overcurrent detection circuit that detects an overcurrent flowing through a semiconductor element and performs a protective operation,
an overcurrent detection unit (22, 23a, 23b) that detects a current flowing through the semiconductor element at a predetermined period and outputs an overcurrent detection signal when the current exceeds an overcurrent detection level;
a determination unit (21, 21a) that increments a count value when there is an overcurrent detection signal from the overcurrent detection unit, decrements the count value when there is no overcurrent detection signal, and determines an overcurrent state when the count value reaches a determination count value;
the determination unit sets a count number of an increment count per unit time to be greater than a count number of a decrement count per unit time ,
The overcurrent detection circuit has a count value that is incremented when an overcurrent detection signal is received from the overcurrent detection unit, and performs the next overcurrent detection at the specified period, and a count value that is decremented when the overcurrent detection signal is not received, and performs the next overcurrent detection at a period longer than the specified period . An overcurrent detection circuit that detects an overcurrent flowing through a semiconductor element and performs a protective operation,
an overcurrent detection unit (22, 23a, 23b) that detects a current flowing through the semiconductor element at a predetermined period and outputs an overcurrent detection signal when the current exceeds an overcurrent detection level;
a determination unit (21, 21a) that increments a count value when there is an overcurrent detection signal from the overcurrent detection unit, decrements the count value when there is no overcurrent detection signal, and determines an overcurrent state when the count value reaches a determination count value;
the determination unit sets a count number of an increment count per unit time to be greater than a count number of a decrement count per unit time ,
The judgment unit is an overcurrent detection circuit that counts up a count value when the overcurrent detection signal from the overcurrent detection unit is generated once or multiple times in succession, and counts down the count value when the overcurrent detection signal is generated multiple times in succession that is greater than the time for the additional count . A switching power supply circuit configured to output a predetermined voltage by switching driving the semiconductor element,
The overcurrent detection circuit (20, 20a, 20b) according to claim 1 or 2 ,
a protection circuit (13) for protecting the semiconductor element when an overcurrent state of the semiconductor element is determined by the overcurrent detection circuit. 4. The switching power supply circuit according to claim 3 , further comprising an overvoltage detection circuit (14) for detecting a voltage applied to the semiconductor element and causing the protection circuit to perform a protection operation when an overvoltage is applied to the semiconductor element.

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