JP2583948B2 - Boost circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory device,
The present invention relates to a booster circuit for boosting and outputting an S level signal to a predetermined potential.

(Prior Art) Conventionally, as this kind of booster circuit, for example, there is one as shown in FIG. Hereinafter, the configuration will be described.

FIG. 2 is a circuit diagram showing one configuration example of a booster circuit in a conventional semiconductor memory device.

This booster circuit is, for example, an amplifier circuit 30 that sets a signal level of a data bus in a dynamic RAM to a MOS level.
Connected to the output side of the
It comprises a bootstrap circuit 10 for boosting the MOS level signal S30 and an output circuit 40.

The bootstrap circuit 10 includes inverters 11 and 12, N-channel MOS transistors (hereinafter, referred to as MNOS) 13, 14, 16,
19, 20, 21; NMOSs 17, 18, which are transfer gates; P-channel MOS transistors (hereinafter, referred to as PMOS) 15;
Inverters 11 and 12 are connected in series to an input node N1 that includes an OS capacitor 22 and is connected to the output side of the amplifier circuit 30. The gates of the NMOSs 14 and 21 are connected to a node N2 between the inverters 11 and 12, and the output node N13 of the inverter 12 is further connected.
Is connected to the gates of the NMOS 13 and the PMOS 15 and the NMOS 17. The NMOSs 13 and 14 are connected in series between the power supply potential Vcc and the ground potential GND, and a node N4 between the NMOSs 13 and 14 is connected to the gate of the NMOS 16. The NMOSs 15 and 16 are connected in series between the power supply potential Vcc and the ground potential GND, and a node N5 between the NMOSs 15 and 16 is connected.
The gate of the NMOS 17 is connected to the gate of the NMOS 17 via the NMOS 18 and the node N6. The output node N7 for the boost signal S10 of the NMOS 17 is connected to the gate of the NMOS 22, the MOS capacitor 22, and to the ground potential GND via the NMOS 21. The NMOSs 19 and 20 are connected in series between the power supply potential Vcc and the ground potential GND, and a node N8 between the NMOSs 19 and 20 is connected to the node N7 via the MOS capacitor 22.

The output circuit 40 connected to the node N7 is a circuit that drives the boost signal S10 output from the bootstrap circuit 10 and sends it out in the form of an output signal Dout.
NMOS 41 and 42 are connected in series between Vcc and ground potential GND. The gate of the NMOS 41 is connected to a node N7, and the gate of the NMOS 42 is connected to a low-potential (hereinafter, referred to as “L”) control signal CS. An output signal Dout is taken out between the two NMOSs 41 and 42.

 Next, the operation will be described.

When the node N1 changes from “L” to “H”, the node N2 is inverted to “L” by the inverter 11 and the node N3 is
It is inverted at 12 to become “H”, and the “H” is transmitted to the node N7 via the NMOS17. At this time, the power supply potential Vcc level is applied to the node N7 by the bootstrap operation (self-boosting operation) of the NMOS 17, and the NMOS 19, 41 is switched according to the Vcc level.
Is turned on, and the MOS capacitor 22 is charged. When the NMOS 19 turns on, a through current flows to the node N8, but the nodes N2 and N
By 3, the NMOS 13 is turned on, the NMOS 14 is turned off, the node N4 becomes “H”, the NMOS 16 is turned on, the nodes N5 and N6 become “L”, and the NMOSs 17 and 20 are turned off. Then, the potential of the node N8 rises, and the node N7 receives the coupling of the MOS capacitor 22.
Is equal to or higher than (Vcc + the threshold value of the transistor). NMO
The timing of turning off S17 and S20 is based on the NMOS 13, 14, 16, 18
And the PMOS 15 is set so that the potential of the node N7 is turned off after the potential of the node N7 rises to the power supply potential Vcc level. Node N7
Rises to a potential equal to or higher than (Vcc + transistor threshold), the power supply potential Vcc level through the NMOS 41, for example, 1.32V
Of the output signal Dout.

(Problems to be Solved by the Invention) However, in the booster circuit having the above configuration, a pulse wave (noise) that changes in a very short time such as “H”, “L”, and “H” generated due to an address queue (distortion) or the like. , There is a risk of malfunction.

That is, FIG. 3 is an operation waveform diagram at the time of a malfunction in FIG. 2. When the node N1 changes from "H" to "L", the potential of the node N7 is discharged through the NMOS 21, and the nodes N4, N5, N6,. N8 also tries to return to the initial state. However, when the node N1 returns to “H” again in a short time, the node N3 becomes “H” before the node N6.
Therefore, the bootstrap operation by the NMOS 17 as the transfer gate cannot be performed sufficiently, and the potential of the node N7 does not rise to the power supply potential Vcc. Therefore, a sufficient boosted potential cannot be obtained, and the output signal Dout of the output circuit 40 drops in level,
That is, there is a problem that a malfunction occurs.

An object of the present invention is to provide a booster circuit that solves the problem of the prior art that a predetermined boosted potential cannot be obtained by a pulse wave and a malfunction occurs.

(Means for Solving the Problems) According to the present invention, in order to solve the above-mentioned problems, in a booster circuit, an output circuit (for example, 40), a bootstrap circuit (for example, 10A), and a correction circuit (for example, pulse) Width correction circuit 50).

The output circuit includes an output terminal, a first control electrode connected to a first node (for example, N7) to which a boost signal (for example, S100) is supplied, a first electrode connected to the output terminal, A first transistor (for example, an NMOS 41) having a second electrode to which a power supply potential is applied, and an output signal having a potential level based on the power supply potential from the output terminal in response to the boost signal (for example, Do
ut).

The bootstrap circuit includes a second node (for example, N3) to which a first input signal having a first or second logic level is supplied, and a second node (for example, N6) connected to a third node (for example, N6). A second transistor (e.g., NMOS 17) having a control electrode, a third electrode connected to the first node, and a fourth electrode connected to the second node
And capacitance means connected to the first node (for example,
MOS capacitor 22), and boosts the potential of the third node in response to the first input signal having the first logic level, thereby performing the bootstrap operation of the second transistor and the capacitance of the capacitor means. A circuit for applying the boost signal having a potential level higher than the power supply potential level to the first node by a coupling operation.

Further, the correction circuit outputs the first input signal to the second node in response to a second input signal having a third or fourth logic level (for example, S30). After outputting the first input signal of the second logic level in response to the second input signal of the third logic level, the logic level of the second input signal is changed to the third logic level. From the first logic level to the fourth logic level, the period from when the first input signal of the first logic level is applied to the second node to when the potential of the third node is boosted elapses After the first logic level of the first
Is a circuit that outputs an input signal.

(Operation) According to the present invention, since the booster circuit is configured as described above, when the second input signal is supplied, the first input signal is output from the correction circuit in response to the second input signal. Is output. The bootstrap circuit performs a boosting operation in response to the first input signal, and the bootstrap circuit
A boost signal having a potential level higher than the power supply potential level is output and sent to the output circuit. The output circuit outputs an output signal of a potential level based on the power supply potential from an output terminal in response to the boost signal.

Here, when the second input signal has a pulse waveform, the correction circuit operates so as to extend the pulse width of the pulse waveform by a predetermined width. This allows the bootstrap circuit to return to the initial state and perform an accurate bootstrap operation. When the pulse width of the pulse wave is extremely short, it is absorbed by the correction circuit, and the first input signal from which the pulse wave has been removed is supplied to the bootstrap circuit. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a booster circuit in a semiconductor memory device showing one embodiment of the present invention. In FIG. 1, the same elements as those in FIG. I have.

This booster circuit, for example,
The pulse width correction circuit 5 is connected to the output side of the amplifier circuit 30 for setting the signal level of the data bus in the RAM to the MOS level.
0, a bootstrap circuit 10A, and an output circuit 40.

The bootstrap circuit 10A is composed of the same circuit as the bootstrap circuit 10 in FIG.

The pulse width correction circuit 50 connected to the input side of the bootstrap circuit 10A is connected to the input side node N10.
A circuit that expands or absorbs the OS level signal S30.
An input NAND gate (hereinafter, referred to as a NAND gate) 51, a flip-flop (hereinafter, referred to as an FF circuit) 52 including cross-connected NAND gates 52a, 52b, and inverters 53, 54
It has. The input side node N10 is connected to the NAND gates 51 and 52b.
The output node N11 of the NAND gate 51 is connected to one input side of the NAND gate 52a,
The output node N12 of the NAND gate 52a is connected to the NAND gate 52b.
The output node N13 of the NAND gate 52b is connected to the other input side of the NAND gate 52a, and the bootstrap circuit is connected via the inverter 53.
It is connected to the input node N1 of 10A. Further, the output side of the inverter 53 is connected to the other input side of the NAND gate 51 via the inverter 54.

Next, the operation of FIG. 1 will be described with reference to FIG. 4 to FIG.

FIG. 4 is an operation waveform diagram of the pulse width correction circuit 50 in FIG. 1, and FIG. 5 is a bootstrap circuit 10 in FIG.
6A is an operation waveform diagram of the output circuit 40. FIG.

As shown in FIG. 4, when the node N10 changes from "H" to "L", the node N13 changes from "L" to "H" through the NAND gate 52b, and in response thereto, via the NAND gate 52a. When the node N12 changes from “H” to “L” and the inverter 5
The node N1 changes from “H” to “L” via 3. Node N
14 changes from “L” to “H” by the inverter 54 in response to the change at the node N1, but even if the node N10 returns to “H” before the node N14 changes, it is suppressed by the NAND gate N11. Node N11 does not change. NAND gate 52b is also a node
Since N12 is “L”, the change of the node N10 is not transmitted to the node N13. Thereafter, the node N11 changes from “H” to “L” in response to the change of the node N14, and the node N12 changes from “L” to “H”.
Changes to Then, the node N13 changes from “H” to “L”,
The node N1 returns from “L” to “H”.

Thus, the inverter 54, the NAND gates 51, 52b, 52a,
Since the pulse width on the node N1 becomes longer due to the delay of the inverter 53, the minimum time required for charging the node N6 in the bootstrap circuit 10A is secured as shown in FIG. An accurate boost operation is performed, and a predetermined level (for example, 1.32
V) can be obtained.

FIG. 6 is an operation waveform diagram of the pulse width correction circuit 50 when a very short pulse MOS level signal S30 is input to the input node N10 of the pulse width correction circuit 50. The broken line in FIG. 6 is a waveform during operation.

When a very short pulse wave (noise) is input to the node N10, the node N13 tries to invert, but does not completely invert because the recovery of the node N10 is fast. If the potential of the node N13 does not exceed the rotation threshold of the inverter 53 and the NAND gate 52a, the pulse wave is absorbed by the pulse width correction circuit 50. When the potential of the node N13 exceeds the circuit threshold, the pulse wave is transmitted to the nodes N1 and N12, but the two nodes N1 and N12 perform the same operation because the circuit threshold is set to the same value, and If N1 is not inverted, the node N12 is not inverted, so that the circuit does not operate, and this noise does not cause the bootstrap circuit 10A to malfunction. Also node N10
Is inverted, the node N12 is also inverted, and the circuit operates.
That is, the circuit operation is controlled by monitoring the node N1 by the node N12.

As described above, in the present embodiment, the bootstrap circuit
A pulse width correction circuit 50 is provided on the input side of 10A to ensure the width of the pulse wave as long as it does not malfunction or absorb it, so even if a very short pulse wave is input, the bootstrap circuit 10A malfunctions An accurate boosting operation is performed without the need. Therefore, it is effective for use in an output buffer circuit or the like of a dynamic RAM. Furthermore, since the number of elements is small, the configuration is simple, and the effect on the operation speed is small,
It can be used for high-speed MOS logic devices, etc. Also, NAND gates 51 and 52 in the pulse width correction circuit 50
If the a, 52b and the inverters 53, 54 are composed of complementary MOS transistors (hereinafter referred to as CMOS), power consumption can be reduced.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications.

(A) The bootstrap circuit 10A can have another circuit configuration using another transistor or the like.

(B) The pulse width correction circuit 50A may have another circuit configuration using another gate circuit such as an AND gate or an OR gate.

(Effects of the Invention) As described in detail above, according to the present invention, a correction circuit is provided on the input side of the bootstrap circuit for securing or absorbing the width of the pulse wave so as not to cause a malfunction. Even if an extremely short pulse wave is input, the bootstrap circuit can perform an accurate boosting operation without causing a malfunction. Therefore, a highly reliable booster circuit that is resistant to noise can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a booster circuit showing an embodiment of the present invention.
FIG. 3 is a circuit diagram of a conventional booster circuit, FIG. 3 is an operation waveform diagram at the time of malfunction in FIG. 2, FIG. 4 is an operation waveform diagram of the pulse width correction circuit in FIG. 1, and FIG. FIG. 6 is an operation waveform diagram of the bootstrap circuit and the output circuit, and FIG. 6 is an operation waveform diagram of the pulse width correction circuit of FIG. 1 when a short pulse is input. 10A: Bootstrap circuit, 30: Amplifier circuit, 40
…… Output circuit, 50 …… Pulse width correction circuit, 51 …… NAND gate, 52 …… FF circuit, 53,54 …… Inverter, S30 …… MO
S level signal, S100 ... Boost signal.

Claims (1)

(57) [Claims] An output terminal, a first control electrode connected to a first node supplied with a boost signal, a first electrode connected to the output terminal, and a second electrode supplied with a power supply potential.
An output circuit comprising: a first transistor having a first electrode and a second transistor; and an output circuit for outputting an output signal having a potential level based on the power supply potential from the output terminal in response to the boost signal. A second input terminal supplied with a first input signal, a second control electrode connected to a third node, a third electrode connected to the first node, and the second node. A second transistor having a fourth electrode connected thereto; and capacitance means connected to the first node, wherein the third transistor is responsive to a first input signal having the first logic level. Boosted by the bootstrap operation of the second transistor and the coupling operation of the capacitance means, the boost having a potential level higher than the power supply potential level at the first node. A bootstrap circuit that supplies a first input signal to the second node in response to a second input signal having a third or fourth logic level; After outputting the first input signal of the second logic level in response to the second input signal of the third logic level, the logic level of the second input signal is changed from the third logic level to the third logic level. When transitioning to the fourth logic level, after a period from when the first input signal of the first logic level is supplied to the second node to when the potential of the third node is boosted, And a correction circuit for outputting a first input signal of the first logic level.