JP2016046620A - Power-on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of stably operating without depending on the length of a time from cut-off of power till reclosing of power and requiring a control signal from the outside.SOLUTION: A first reference voltage and a second reference voltage set lower than the first reference voltage are generated. The first reference voltage is set so that a rise time during power-up becomes slower in comparison with the second reference voltage. Comparison means outputs an L level signal in situation where the first reference voltage is lower than the second reference voltage, and outputs an H level signal in the reverse case. The H level signal output by the comparison means is outputted by delay means as a delay signal rising in a delayed manner, and buffer means outputs a reset signal corresponding to the delayed signal. Discharge means operates by receiving the second reference voltage during power-up to discharge charges of a capacitor included in the delay means, and the discharge means releases a discharge circuit if the comparison means outputs the H level signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power-on reset circuit, and more particularly to a power-on reset circuit that operates stably when power is turned on again.

  In order to automatically start the computer normally when the computer is turned on, it is necessary to initialize the internal circuit of the computer hardware when the computer is turned on. In this initialization operation, the program counter is reset to 0, the timer is reset to a predetermined state, the internal computer state, the instruction execution result state, etc. are reset to a predetermined state, etc. Operation is performed.

  In order to execute this reset, it is necessary to set the reset signal to L (low) level in a state where power is stably supplied. This state is realized by a power-on reset circuit that connects a reset signal, which rises with a predetermined timing after the power supply reaches the specified voltage, to the reset input of the computer.

  Examples of related art power-on reset circuits are disclosed in Patent Documents 1 and 2.

  The power-on reset circuit disclosed in Patent Document 1 is a circuit that can reliably generate a reset pulse even when the power supply voltage rises steeply or slowly.

  The power-on reset circuit disclosed in Patent Document 2 is a circuit that does not generate an unnecessary power-on reset signal as long as it is within an allowable range even if the power supply voltage fluctuates.

  A configuration example and operation of a related art power-on reset circuit will be described with reference to FIGS.

  FIG. 5 is a circuit diagram showing a configuration example of a related art power-on reset circuit.

  The power-on reset circuit shown in FIG. 5 includes an NMOS 31 as a first transistor, an NMOS 32 as a second transistor, a resistor 33, an inverter 34, a capacitor 35, a resistor 36, a capacitor 37, and a buffer 38. . “NMOS” is an abbreviation for “n-type Metal Oxide Semiconductor”.

  The resistor 33 is connected in series to the NMOS 31 and the NMOS 32, and the input of the inverter 34 is connected to a connection node N 11 between the resistor 33 and the NMOS 32. The capacitor 35 is connected to a connection node N12 between the NMOS 31 and the NMOS 32. The resistor 36 is connected to the output of the inverter 34 at the connection node N13, and the other end of the resistor 36 is connected to the buffer 38 at the connection node N14. The capacitor 37 is connected to a connection node N14 between the resistor 36 and the buffer 38.

  In a state before the power supply voltage (VDD: Voltage Drains) is applied, the two NMOSs 31 and 32 are in an off state.

  FIG. 6 is a chart for explaining the operation of the power-on reset circuit having the configuration of FIG.

  The upper chart in FIG. 6 shows how VDD, the threshold voltage (Vti) of the inverter 34, and the voltage at the connection node N11 and the connection node N12 change with the passage of time since the power is turned on. Vth is a threshold voltage applied to the gate of each transistor for turning on the NMOSs 31 and 32.

  Further, the lower chart diagram of FIG. 6 shows the change of the voltage at the connection node N13 and the connection node N14 and the state of the reset signal OUT corresponding to the upper chart diagram as time elapses after the power is turned on.

  As shown in the upper chart of FIG. 6, when VDD is applied by turning on the power, the voltage applied to the gates of the NMOSs 31 and 32 gradually increases, and the threshold value Vti of the inverter 34 also increases in proportion. The voltage at the connection node N11 also increases as VDD increases. The voltage of the connection node N12 also increases with VDD due to the capacitor 35.

  Immediately after the power is turned on, the inverter 34 outputs an L level signal (see N13 in the lower chart of FIG. 6).

  When the voltage applied to the gates of the NMOSs 31 and 32 exceeds the threshold value Vth at time T0 and each transistor is turned on, the NMOS 31 first causes a charging current to flow from the capacitor 35, and the voltage at the connection node N12 is decreased. Subsequently, the NMOS 32 causes a current to flow through the resistor 33 and the connection node N11. That is, by delaying the current flowing through the resistor 33 by the capacitor 35, the voltage at the connection node N11 drops after a little time has elapsed since VDD exceeded the threshold value Vth.

  When the voltage at the connection node N11 reaches the inverter threshold value Vti at time T1, the inverter 34 outputs an H (high) level signal (see N13 in the lower chart of FIG. 6).

  Further, when the reset signal is output after VDD has completely risen, this is realized by providing a delay circuit after the inverter 34. This delay circuit is constituted by a filter circuit having a resistor 36 and a capacitor 37 in series. The delay circuit outputs the signal of the connection node N13 to the buffer 38 as the voltage of the connection node N14 having a delay change due to the time constant (τ = RC) by the resistor 36 and the capacitor 37. Here, R is the resistance value of the resistor 36, and C is the capacitance value of the capacitor 37. Assuming that the threshold value of the buffer 38 is the same as the threshold value Vti of the inverter 34, the reset signal OUT is output in which the L level is delayed until time T2 when the voltage of the connection node N14 rising after delay reaches the threshold value Vti.

  Receiving the L level reset signal OUT after VDD rises, the computer performs an initialization operation. Then, upon receiving the H level reset signal OUT, the release operation is performed.

  FIG. 7 is a chart for explaining the operation of the related-art power-on reset circuit when power is turned on again.

  The upper chart of FIG. 7 shows how VDD changes with the lapse of time after turning on the power. After turning on the power, the VDD gradually reaches the specified voltage, and after the power is stabilized, the power is turned off. After that, the power is turned on again.

  The operation from when the power is turned on until VDD becomes stable is as described with reference to FIG.

  The middle chart in FIG. 7 shows how the threshold voltage (Vti) of the inverter 34 changes in voltage at the connection node N13 and the connection node N14 following the change in VDD.

  As shown in the middle chart of FIG. 7, the signal at the connection node N13 is output to the connection node N14 as a voltage having a delay change due to the time constant by the resistor 36 and the capacitor 37 and supplied to the buffer 38.

  The lower chart of FIG. 7 shows how the reset signal OUT changes corresponding to the central chart when the power is turned on, the power is stabilized, the power is turned off, and the power is turned on again.

  As shown in the lower chart of FIG. 7, even if the voltage of the connection node N14 rises, the buffer 38 outputs an L level reset signal OUT until the voltage reaches the threshold value Vti. After the voltage at the connection node N14 reaches the threshold value Vti, an H level reset signal OUT is output.

  Turn off the power after a while in the above state.

  When the power supply is cut off, the operation of each element for which the supply of the operating voltage is cut off is stopped, and the output voltage (connection node N13) of the inverter 34 and the threshold value Vti of the buffer 38 are the power supply as shown in the middle chart of FIG. It will follow and fall down.

  On the other hand, the voltage at the connection node N14 is a time constant (τ = RC) due to the resistor 36 and the capacitor 37, and the voltage drops with a delay corresponding to the discharge time of the capacitor 37.

  Turn on the power again after a certain period of time since the power was turned off.

  When the power is turned on again, VDD and the threshold value Vti of the buffer 38 increase following the power on.

  At this time, the input of the inverter 34 does not reach the threshold value Vti, and an L level signal is output to the connection node N13. However, when the capacitor 37 is not completely discharged, the voltage is held at the connection node N14, and the held voltage decreases as the capacitor 37 is discharged.

Japanese Patent Laid-Open No. 2001-016085 Japanese Patent Laid-Open No. 10-207580

  Normally, the reset signal of the power-on reset circuit is required to release an L level reset signal after the power is turned on while the power supply voltage (VDD) is stable, and then issue an H level reset signal to cancel the reset. ing. For this reason, a configuration in which an L level reset signal is delayed by a delay circuit until VDD becomes stable is common.

  The related art power-on reset circuit has a problem that the power-on reset function does not operate normally when the power is turned off and then turned on again in a short time.

  As described with reference to FIG. 7, the voltage at the connection node N <b> 14 is a time constant due to the resistor 36 and the capacitor 37, and the voltage decreases with a delay corresponding to the discharge time of the capacitor 37. Therefore, when the time constant is large, the discharge time of the capacitor 37 takes a long time. Therefore, when the time until the power is turned on again after turning off the power supply is short, the voltage at the connection node N14 holds a voltage equal to or higher than the threshold value Vti of the buffer 38. There is a possibility that.

  In other words, when the power is turned on again when the voltage at the connection node N14 holds the voltage equal to or higher than the threshold value Vti of the buffer 38, the buffer 38 to which the operation power is supplied by turning on the power again follows the rise of VDD. As a result, an H level signal is output.

  Therefore, an L level reset signal cannot be output while VDD is stable.

  FIG. 8 shows a state in which the above-described problem that the power-on reset function does not operate normally occurs in the power-on reset circuit having the configuration of FIG. 5 when the time until the power is turned on again after the power is turned off is short. FIG.

  In order to cope with such a problem, a delay circuit including a resistor 36 and a capacitor 37 may be provided with a discharge circuit that discharges the capacitor 37 when the power is turned off. Control for a discharge circuit that externally controls the discharge circuit There is a problem that requires a signal.

  In view of the above-described problems, the present invention provides a power-on power source that stably operates without depending on the length of time until the power is turned on again after the power is turned off, and without requiring an external control signal. An object is to provide a reset circuit.

  In order to achieve the above object, a power-on reset circuit according to an aspect of the present invention includes a first internal voltage generation unit that generates a first reference voltage, and is set lower than the first reference voltage. The second internal voltage generating means for generating the second reference voltage is compared with the first reference voltage and the second reference voltage, and the first reference voltage is lower than the second reference voltage. The comparator circuit outputs an L (low) level signal in a state, and outputs an H (high) level signal when the first reference voltage is higher than the second reference voltage, and an H level output from the comparator circuit. A delay means for outputting a signal as a delayed signal that rises with a delay determined by a time constant determined by a resistance and a capacitance, and the delay signal output by the delay means is at an L level until a predetermined threshold value is reached; When this threshold is reached, the H level A buffer means for outputting a set signal; and a discharge circuit having a capacity constituting the delay means in response to the second reference voltage generated by the second internal voltage generating means when the power is turned on; and the comparing means Discharge means for releasing the discharge circuit when an H level signal is output, and the first reference voltage is set so that the rise time is slower than the second reference voltage when the power is turned on. It is characterized by.

  The present invention realizes a power-on reset circuit that operates stably without depending on the length of time until the power is turned on again after the power is turned off, and without requiring an external control signal. it can.

It is a block diagram which shows the structure of the power-on reset circuit of 1st Embodiment. It is a circuit diagram which shows the structure of the power-on reset circuit of 2nd Embodiment. It is a chart figure which shows operation of a power on reset circuit of a 2nd embodiment. It is a chart figure showing another operation of the power-on reset circuit of a 2nd embodiment. It is a circuit diagram which shows the structural example of the power-on reset circuit of related technology. FIG. 6 is a chart for explaining the operation of a power-on reset circuit having the configuration of FIG. 5. FIG. 6 is a chart for explaining the operation of the power-on reset circuit having the configuration of FIG. FIG. 6 is a chart showing a state in which a problem occurs in which the power-on reset function of the power-on reset circuit having the configuration of FIG.

  DESCRIPTION OF EMBODIMENTS Embodiments for carrying out the present invention will be described with reference to the drawings.

  The embodiment is an exemplification, and the disclosed apparatus is not limited to the configuration of the following embodiment.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration of a power-on reset circuit according to the first embodiment.

  The power-on reset circuit 100 according to the first embodiment includes a first internal voltage generation unit 1, a second internal voltage generation unit 2, a comparison unit 3, a delay unit 4, a buffer unit 5, and a discharge unit 6. It has become.

  The first internal voltage generation means 1 generates a first reference voltage.

  The second internal voltage generation means 2 generates a second reference voltage that is set lower than the first reference voltage. However, when the power is turned on, the first reference voltage is set so that the rise time is slower than the second reference voltage.

  The comparison means 3 compares the first reference voltage with the second reference voltage, and outputs an L (low) level signal when the first reference voltage is lower than the second reference voltage. Is higher than the second reference voltage, an H (high) level signal is output.

  The delay means 4 outputs the H level signal output from the comparison means 3 as a delay signal that rises with a delay determined by a time determined by a time constant of resistance and capacitance.

  The buffer unit 5 is at L level until the delay signal output from the delay unit 4 reaches a predetermined threshold value, and outputs an H level reset signal when the delay signal reaches the predetermined threshold value.

  The discharging means 6 receives the second reference voltage generated by the second internal voltage generating means when the power is turned on, and forms a discharging circuit having a capacity constituting the delay means 4, and the comparing means 3 receives the H level signal. Is output, the discharge circuit is released.

  In the power-on reset circuit 100 of the first embodiment configured as described above, the discharging means 6 receives the second reference voltage generated by the second internal voltage generating means when the power is turned on, and the delay means 4 A circuit for discharging the charge of the capacitor to be formed is formed.

  In other words, when the power is turned on, the second reference voltage is set to rise earlier than the first reference voltage. Therefore, there is a time zone during which the second reference voltage is higher than the first reference voltage. Exists. The comparison means 3 outputs an L level signal because the second reference voltage is higher than the first reference voltage during the time period. Further, during the time period, the discharge means 6 receives the second reference voltage and forms a discharge circuit having a capacity constituting the delay means 4 (discharge control).

  Since the first reference voltage is set higher than the second reference voltage, the second reference voltage (VDD) rises completely when the power supply voltage (VDD) completely rises even if the rise time is set to be slow. The voltage exceeds the reference voltage.

  At this stage, it is necessary to output an L level reset signal as a power-on reset circuit for a predetermined time, and then output an H level reset signal.

  For this reason, the H level signal output from the comparison means 3 is output as a delay signal that rises with a delay determined by the time determined by the time constant of the resistance and capacitance constituting the delay means 4. At this time, the capacitor constituting the delay means 4 must be in a state where charge can be charged. Therefore, when the comparing means 3 outputs the H level signal, the discharging means 6 functions so as to enable the delayed output operation of the signal by releasing the discharge circuit for the capacitor constituting the delay means 4 (discharge release). control).

  Further, the buffer means 5 inputs a delay signal, and forms and outputs a reset signal which is at L level until the signal level reaches a predetermined threshold value and becomes H level when the signal level reaches the predetermined threshold value.

  Even if the power supply is turned on again after the power supply is turned off and the capacity of the capacitor constituting the delay means 4 is not sufficiently discharged, it is formed by the discharge means 6 during the rise of VDD. The discharge circuit can discharge the electric charge of the capacitor. In addition, since the discharge means 6 operates by receiving the second reference voltage, no external control signal is required.

  Further, when the comparator 3 operates to output an H level signal and the delay unit 4 outputs a delay signal, the discharge unit 6 can charge the capacitor constituting the delay unit 4 with charge. Then, the discharge circuit is released. In addition, since the discharge means 6 operates in response to the H level signal output from the comparison means 3, no external control signal is required in this case.

  As described above, the power-on reset circuit according to the present embodiment is stable without depending on the length of time until the power is turned on again after the power is turned off, and does not require an external control signal. And can work.

(Second Embodiment)
Next, a power-on reset circuit according to the second embodiment will be described.

  FIG. 2 is a circuit diagram showing a configuration of a power-on reset circuit according to the second embodiment.

  The power-on reset circuit 200 of the second embodiment includes a first internal voltage generation circuit BK1, a second internal voltage generation circuit BK2, a comparison circuit 17, a delay circuit BK3, a buffer circuit 20, a switch BK4, and a switch BK5. It is configured. BK is used as an abbreviation for block.

  The first internal voltage generation circuit BK1 corresponds to the first internal voltage generation unit 1 of the power-on reset circuit 100 according to the first embodiment. Similarly, the second internal voltage generation circuit BK2 is the second internal voltage generation means 2, the comparison circuit 17 is the comparison means 3, the delay circuit BK3 is the delay means 4, and the buffer circuit 20 is the buffer means 5. Each corresponds. Further, the switch BK4 and the switch BK5 correspond to the discharging means 6.

  The first internal voltage generation circuit BK1 includes a series connection of a resistor 11, a resistor 12, and a resistor 13, and the resistor 11 is connected to a power supply voltage (VDD), and the resistor 13 is connected to the ground. Then, VDD is divided by resistance, and a first reference voltage is generated with the potential of the connection node N3 between the resistor 12 and the resistor 13.

  The second internal voltage generation circuit BK2 includes a resistor 14 and an NMOS 15. The drain of the NMOS 15 is connected to the resistor 14 at the connection node N1, and is connected to VDD via the resistor 14. The source of the NMOS 15 is connected to the ground. The gate of the NMOS 15 receives a divided voltage different from the first reference voltage divided by the first internal voltage generation circuit BK1.

  The second internal voltage generation circuit BK2 generates a second reference voltage with the potential of the connection node N1. That is, when the NMOS 15 is off, VDD via the resistor 14 becomes the second reference voltage, and when the NMOS 15 is on, VDD divided by the on-resistance of the resistor 14 and the NMOS 15 becomes the second reference voltage.

  With the above configuration, the state in which the second reference voltage of the connection node N1 is higher than the first reference voltage of the connection node N3 at the time of power-on is maintained.

  That is, when the voltage supplied to the gate of the NMOS 15 is lower than the operating region, the NMOS 15 is in an off state, so the second reference voltage follows the rise of VDD. On the other hand, since the first reference voltage is a divided voltage of VDD, the second reference voltage is higher than the first reference voltage when the power is turned on. When VDD further rises and the gate voltage of the NMOS 15 becomes higher than the operating region, the NMOS 15 is turned on. As a result, the second reference voltage of the connection node N1 is divided by VDD due to the on-resistance of the resistor 14 and the NMOS 15, and the first reference voltage of the connection node N3 is higher than the second reference voltage of the connection node N1. Become.

  The comparison circuit 17 receives the first reference voltage and the second reference voltage, outputs an H level signal if the first reference voltage is higher than the second reference voltage, and conversely, the second reference voltage. If the voltage is higher than the first reference voltage, an L level signal is output.

  The delay circuit BK3 includes a resistor 18 and a capacitor 19. An H level signal delayed by a delay time determined by the time constant of the resistor 18 and the capacitor 19 with respect to the H level signal output from the comparison circuit 17 is supplied to the connection node N2. Output.

  The buffer circuit 20 outputs an L level signal when the signal output to the connection node N2 does not reach the threshold value of the buffer circuit 20, and H when the signal output to the connection node N2 exceeds the threshold value. A level signal is output. A signal output from the buffer circuit 20 is supplied as a reset signal OUT to a microcomputer (not shown) or the like.

  The switch BK4 and the switch BK5 correspond to the discharging means 6 of the first embodiment as described above.

  The switch BK4 is composed of an NMOS 16 and the switch BK5 is composed of an NMOS 21.

  The switch BK4 is connected in parallel with the capacitor 19 constituting the delay circuit BK3, and forms a discharge circuit in which the charge of the capacitor 19 is discharged when turned on, and the capacitor 19 can be charged with charge when turned off. Release the discharge circuit.

  The drain of the NMOS 16 is connected to the connection node N2 of the delay circuit BK3, and the source is connected to the ground. The gate of the NMOS 16 is connected to the connection node N1 of the second internal voltage generation circuit BK2. The NMOS 16 is turned on when the gate voltage (voltage of the connection node N1) reaches a predetermined operation region (threshold voltage). This threshold voltage is set so that the NMOS 16 is turned on even at a low voltage.

  That is, when the power is turned on, VDD via the resistor 14 is supplied to the switch BK4 as the second reference voltage. When the second reference voltage reaches the threshold voltage of the NMOS 16 as VDD increases, the switch BK4 is turned on. (Discharge control)

  When the switch BK4 is turned on, a discharge circuit of the capacitor 19 constituting the delay circuit BK3 connected in parallel is formed and functions to discharge electric charges.

  When the NMOS 15 is turned on, VDD divided by the second reference voltage, the resistor 14 and the NMOS 15 on-resistance, is set to a voltage at which the NMOS 16 can be kept on.

  The switch BK5 performs control (discharge release control) to turn off the switch BK4.

  The switch BK5 detects the output of the comparison circuit 17, and is turned off when the output is at the L level, and turned on when the output is at the H level.

  That is, the gate of the NMOS 21 is connected to the output of the comparison circuit 17, and the NMOS 21 is turned on when the comparison circuit 17 outputs an H level signal, and is turned off when the L level signal is output.

  The drain of the NMOS 21 is connected to the connection node N1 (equivalent to the gate of the NMOS 16), and the source is connected to the ground.

  When VDD rises and the first reference voltage of the connection node N3 becomes higher than the second reference voltage of the connection node N1, the comparison circuit 17 outputs an H level signal and the NMOS 21 is turned on. When the NMOS 21 is turned on, an L level signal, which is a ground potential due to the on resistance of the NMOS 21, is supplied to the gate of the NMOS 16, and the NMOS 16 is turned off.

  When the NMOS 16 is turned off, the discharge circuit is released and the capacitor 19 can be charged with electric charges. As a result, the capacitor 19 functions as the delay circuit BK3 together with the resistor 18 by charging the electric charge.

  The power-on reset circuit 200 according to the second embodiment operates stably without depending on the length of time from power-off to power-on, and without requiring an external control signal. This will be described with reference to FIGS.

  FIG. 3 is a chart showing the operation of the power-on reset circuit 200 when the time from power-off to power-on is long.

  FIG. 4 is a chart showing the operation of the power-on reset circuit 200 when the time from power-off to power-on is short.

  Referring to FIG. 3, the first to fourth charts are shown.

  The first stage chart shows how the power supply voltage (VDD) changes with time after the power is turned on, and shows how the power is turned off and then turned on again. FIG. 3 illustrates a case where the time from power-off to power-on is long.

  The second stage chart shows how the first reference voltage at the connection node N3, the second reference voltage at the connection node N1, and the output of the comparison circuit 17 change in accordance with the change in VDD.

  The third stage chart shows how the H level signal output from the comparison circuit 17 is output to the connection node N2 after the delay circuit BK3 delays the delay time determined by the time constant of the resistor 18 and the capacitor 19. The figure also shows how VDD changes.

  The fourth stage chart shows that when the signal output to the connection node N2 does not reach the threshold value of the buffer circuit 20, the L level reset signal OUT is output. When the signal exceeds the threshold value, the H level reset signal OUT is output. A state of output from the buffer circuit 20 is shown.

  When the power is turned on, the first reference voltage and the second reference voltage increase as VDD increases. At this time, the second reference voltage of the connection node N1 of the second internal voltage generation circuit BK2 is applied to the gate of the NMOS 16 of the switch BK4. Since the operation threshold voltage of the NMOS 16 is set to a low voltage, the NMOS 16 is turned on at a relatively early stage as VDD increases after the power is turned on. When the switch BK4 is turned on, a discharge circuit for discharging the charge of the capacitor 19 of the delay circuit BK3 is formed, and the capacitor 19 is rapidly discharged.

  When VDD further rises and reaches the operation threshold voltage of the NMOS 15 of the second internal voltage generation circuit BK2, the NMOS 15 is turned on. As described above, when the NMOS 15 is turned on, the potential of the connection node N1 falls below the potential of the connection node N3, and the first reference voltage becomes higher than the second reference voltage. As a result, the comparison circuit 17 outputs an H level signal.

  When the comparison circuit 17 outputs an H level signal, the NMOS 21 of the switch BK5 is turned on, and as a result, the NMOS 16 of the switch BK4 is turned off.

  When the switch BK4 is turned off, the discharge circuit is released so that the capacitor 19 can be charged.

  On the other hand, when the comparison circuit 17 outputs an H level signal, the delay circuit BK3 delays the delay time determined by the time constant of the resistor 18 and the capacitor 19 and outputs the delayed signal to the connection node N2. Then, an L level reset signal OUT and an H level reset signal OUT corresponding to the threshold value of the buffer circuit 20 are output.

  When the power is turned on, VDD rises to reach a stable voltage and the power supply is turned off after the power supply is turned on for a while. After a certain time after the power is turned off, the power is turned on again.

  Note that if the supply of the operating voltage is cut off due to the power interruption, the operation of each element stops, and the outputs of the comparison circuit 17 and the buffer circuit 20 follow the power interruption and drop.

  The above-described operation is repeated when the power is turned on again.

  That is, when the power is turned on again, the second reference voltage of the connection node N1 of the second internal voltage generation circuit BK2 is applied to the gate of the NMOS 16 of the switch BK4. Since the operation threshold voltage of the NMOS 16 is set to a low voltage, the NMOS 16 is turned on at a relatively early stage after the power is turned on, and a discharge circuit for discharging the charge of the capacitor 19 of the delay circuit BK3 is formed. 19 discharges rapidly.

  After that, when the first reference voltage becomes higher than the second reference voltage, the comparison circuit 17 outputs an H level signal and the NMOS 21 of the switch BK5 is turned on. As a result, the NMOS 16 of the switch BK4 is turned off. Become. When the switch BK4 is turned off, the discharge circuit is released and the capacitor 19 can be charged with electric charges.

  The above is the description of the operation of the power-on reset circuit 200 according to the second embodiment when the time from power-off to power-on is long with reference to FIG.

  On the other hand, FIG. 4 is a chart showing the operation of the power-on reset circuit 200 when the time from power-off to power-on is short. The first to fourth charts are the same as those in FIG.

  Unlike FIG. 3, FIG. 4 shows an operation in the case where VDD is increased by turning on the power, reaches a stable voltage, and is turned on for a while and then turned off, and then turned on again immediately after turning off the power. .

  Therefore, unlike the third stage chart of FIG. 3, the power is turned on again in a state where the charge of the capacitor 19 of the delay circuit BK3 is not sufficiently discharged.

  However, even in such a case, the power-on reset circuit 200 according to the second embodiment is connected to the second internal voltage generation circuit BK2 by turning on the power again, as in the operation described in FIG. A second reference voltage of N1 is applied to the gate of the NMOS 16 of the switch BK4. Since the operation threshold voltage of the NMOS 16 is set to a low voltage, the NMOS 16 is turned on at a relatively early stage after the power is turned on, and a discharge circuit for discharging the charge of the capacitor 19 of the delay circuit BK3 is formed. The capacitor 19 discharges rapidly.

  The power-on reset circuit 200 according to the second embodiment is configured such that the potential of the connection node N1 is lower than the potential of the connection node N3 when the NMOS 15 of the second internal voltage generation circuit BK2 is turned on. . However, the present invention is not limited to this configuration, and the first reference voltage that is set so that the rise time is slower than the second reference voltage is higher than the second reference voltage during the rise of VDD. Any configuration is acceptable.

  As described above, the power-on reset circuit of the present embodiment includes the switch BK4 (NMOS 16) that constitutes a discharge circuit that discharges the charge of the capacitor 19 of the delay circuit BK3 at an early stage of power-on. In addition, the discharge circuit is operated by using the second reference voltage that rises when the power is turned on as a trigger, and the comparison circuit 17 outputs an H level signal when the first reference voltage becomes higher than the second reference voltage. The discharge circuit was released as a trigger.

  Therefore, the power-on reset circuit according to the present embodiment operates stably without depending on the length of time until the power is turned on again after the power is turned off, and without requiring an external control signal. Can do.

DESCRIPTION OF SYMBOLS 1 1st internal voltage generation means 2 2nd internal voltage generation means 3 Comparison means 4 Delay means 5 Buffer means 6 Discharge means 11, 12, 13, 14, 18, 33, 36 Resistance 15, 16, 21, 31, 32 NMOS
17, 35, 37 Comparison circuit 19 Capacity 20 Buffer circuit 34 Inverter 38 Buffer N1, N2, N3, N11, N12, N13, N14 Connection node BK1 First internal voltage generation circuit BK2 Second internal voltage generation circuit BK3 Delay circuit BK4, BK5 switch 100, 200 Power-on reset circuit

Claims (4)

First internal voltage generating means for generating a first reference voltage;
Second internal voltage generating means for generating a second reference voltage set lower than the first reference voltage;
The first reference voltage is compared with the second reference voltage, and an L (low) level signal is output when the first reference voltage is lower than the second reference voltage, and the first reference voltage Comparing means for outputting an H (high) level signal in a state where is higher than the second reference voltage;
Delay means for outputting an H level signal output from the comparison circuit as a delay signal that rises with a delay determined by a time determined by a time constant of a resistor and a capacitor;
Buffer means for outputting a reset signal at an L level until the delay signal output by the delay means reaches a predetermined threshold, and when reaching the predetermined threshold;
When the power supply is turned on, the second reference voltage generated by the second internal voltage generation means is received to form a discharge circuit having a capacity constituting the delay means, and when the comparison means outputs an H level signal, the discharge circuit A power-on reset circuit, wherein the first reference voltage is set to have a rise time later than that of the second reference voltage when the power is turned on. The discharging means includes
A first switch installed in parallel with the capacitor constituting the delay means, forming a circuit that discharges the charge of the capacitor when turned on, and releasing the discharge circuit of the charge of the capacitor when turned off;
A second switch that detects the output of the comparison means and is turned off when the output is at L level, and turned on when the output is at H level;
When the power is turned on, the second switch is in an off state, and the second reference voltage generated by the second internal voltage generating means is supplied to the first switch, so that the first switch is in an on state. become,
When the comparison means outputs an H level signal and the second switch is turned on, an L level signal via the second switch is supplied to the first switch and the first switch is turned off. The power-on reset circuit according to claim 1, wherein the power-on reset circuit is in a state. The second internal voltage generating means includes a first resistor connected to a power supply voltage, a drain connected to the power supply voltage via the first resistor, and a source connected to a ground potential. Including transistors,
The first switch has a gate connected to the drain of the first transistor, a drain connected to a connection point between a second resistor and a capacitor constituting the delay means, and a source connected to the ground. A second transistor connected to the potential;
The second switch has a gate connected to the output of the comparison means, a drain connected to the drain of the first transistor and the gate of the second transistor, and a source connected to the ground potential. The power-on reset circuit according to claim 2, wherein the power-on reset circuit is a transistor. The first internal voltage generating means includes a plurality of third resistors that divide the power supply voltage into a plurality of divided voltages, and one of the divided voltages is used as the first reference voltage as one of the inputs of the comparing means. Connect as one
The second internal voltage generating means uses the power supply voltage via the first resistor when the first transistor is in an off state, and the first resistor when the first transistor is in an on state. A power supply voltage divided by the on-resistance of the first transistor is connected as the second reference voltage as the other input of the comparator;
The gate of the first transistor receives a divided voltage different from the first reference voltage divided by the first internal voltage generating means,
The first reference voltage rises at a voltage lower than the second reference voltage following the rise of the power supply voltage from the time of power-on to a predetermined time, and when the predetermined time is exceeded, the first reference voltage rises. 4. The power-on reset circuit according to claim 3, wherein the reference voltage rises at a voltage having a value higher than that of the second reference voltage.

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