CN117713782A - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- CN117713782A CN117713782A CN202410157692.4A CN202410157692A CN117713782A CN 117713782 A CN117713782 A CN 117713782A CN 202410157692 A CN202410157692 A CN 202410157692A CN 117713782 A CN117713782 A CN 117713782A
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- comparator
- reset circuit
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- 230000001934 delay Effects 0.000 claims abstract description 3
- 239000003990 capacitor Substances 0.000 claims description 15
- 230000003111 delayed effect Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
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- Electronic Switches (AREA)
Abstract
The invention discloses a power-on reset circuit. In order to solve the technical problems that the prior art is difficult to meet the requirement of wide power-on time range and strict on initialization time, the invention divides the voltage of a power supply through a first switch and a voltage dividing resistor, delays the divided voltage through a delay module, is used as one of the input of a comparator, the comparator also receives a band gap reference voltage as the input, and takes an external POR signal as an enabling signal. The power-on reset circuit provided by the invention has an accurate threshold value and can overcome various ripple wave influences. The invention is suitable for the field of chip design.
Description
Technical Field
The invention relates to a power-on reset circuit, in particular to a power-on reset circuit with an accurate threshold value.
Background
The Power On Reset circuit (POR) is used for generating Reset signals when the chip is powered On and powered off, and the digital and analog modules are turned On and Reset by the generated Reset signals, so that the safe starting of the chip is ensured.
The traditional principle of the power-on reset circuit is that the power-on reset circuit outputs a reset signal after a power supply is powered up to a certain threshold value. However, the threshold value for flipping is greatly changed by the chip process and the temperature, and is difficult to be directly used as a high-precision reset signal.
A common solution is to delay the initial POR signal by a clock count until the Vdd supply voltage is powered up before it is complete, but this is difficult to meet applications with a wide power-up time range and stringent initialization time requirements. For example, the registered clock drive (Registered Clock Driver, RCD) chip protocol requires power-up times of only one to tens of milliseconds, while the time for initialization is only hundreds of microseconds. If the ring oscillator is directly used for counting, when the low flip voltage counts to the Vdd supply voltage to finish powering up, the high flip voltage counts to the millisecond delay after the Vdd supply voltage finishes powering up, so that the initialization time requirement of the RCD chip is not met.
Based on this, a power-on reset circuit with an accurate threshold is needed in the art.
Disclosure of Invention
In order to alleviate or partially alleviate the above technical problem, the solution of the present invention is as follows:
a power-on reset circuit, the power-on reset circuit comprising: the circuit comprises a first switch, a first resistor, a second resistor, a delay module and a comparator; the first switch, the first resistor and the second resistor divide the power supply to obtain resistor division; the delay module delays the resistor voltage division to obtain delayed voltage division; the comparator compares the delayed divided voltage with a bandgap reference voltage to obtain a POR output signal.
In an embodiment, the comparator also receives an external POR signal from outside, which is used to enable the comparator.
In one embodiment, the first input end of the comparator is coupled to the third filter capacitor; the second input end of the comparator is coupled with the second filter capacitor.
In one embodiment, an output terminal of the comparator is coupled to the first filter capacitor.
In an embodiment, the power supply is coupled to a first end of the first switch, a second end of the first switch is coupled to a first end of the first resistor, a second end of the first resistor is coupled to a first end of the second resistor, and a second end of the second resistor is grounded.
In one embodiment, the control terminal of the first switch receives the bandgap reference voltage as an input.
In one embodiment, the first resistor has a second end coupled to the delay module.
In an embodiment, the power-on reset circuit further includes a hysteresis module;
the hysteresis module at least comprises an inverter and a switching tube; the POR output signal is used as the input of the inverter, and the output signal of the inverter is used as the control signal of the switching tube.
In one embodiment, one end of the switch tube is grounded, and the other end of the switch tube is coupled to the first end of the second resistor.
In one embodiment, the inversion point of the external POR signal is earlier than the intersection of the delayed divided voltage and the bandgap reference voltage.
The technical scheme of the invention has one or more of the following beneficial technical effects:
1. the bandgap reference source and the comparator generate a reset signal, which by introducing an external POR signal enable ensures that the structure does not flip erroneously at low voltages.
2. The switch and the delay part are introduced, so that the bandgap reference voltage is ensured to be established before resistor voltage division, a plurality of intersection points are avoided in the establishing process at the input end, and burrs are generated at the output end.
3. The filter capacitance is added to the input and output of the comparator, so that burrs at the output end caused by charge feed-through are avoided.
4. The comparator is added with a hysteresis part to prevent the output end from generating burrs caused by ripples in the power-on process of the power supply.
5. No separate clock count is required, the inversion threshold voltage range can be controlled within 5%, and when the POR output signal is inverted, the bandgap voltage and current are stabilized, and a stable reset signal can be generated.
Furthermore, other advantageous effects that the present invention has will be mentioned in the specific embodiments.
Drawings
FIG. 1 is a schematic diagram of a POR circuit of the present invention;
FIG. 2 is a schematic diagram of various voltage set-up variations;
FIG. 3 is a schematic diagram of another POR circuit of the present invention;
FIG. 4 is a schematic diagram of external POR signal inversion resulting in ripple generation;
fig. 5 is a schematic diagram of ripple generated during power-up.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Wherein, in the description of the present invention, "/" means that the related objects are in a "or" relationship, unless otherwise specified, for example, a/B may mean a or B; the "and/or" in the present invention is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural.
In the description of the present invention, unless otherwise indicated, "a plurality" means two or more than two. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
In addition, in order to facilitate the clear description of the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In embodiments of the invention, words such as "exemplary," "such as" and the like are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary," "for example," or "example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," and the like is intended to present related concepts in a concrete fashion that may be readily understood.
Referring to fig. 1, a schematic diagram of the POR circuit of the present invention is shown. The circuit comprises a first switch, a first resistor R1, a second resistor R2, a delay module and a comparator. The POR circuit outputs a POR output signal (reference numeral por_out) and receives an external POR signal (reference numeral POR) and a reference voltage Vref from an external circuit. The reference voltage Vref is also a bandgap reference voltage Vref generated by a bandgap (bandgap) reference source.
The power supply Vdd is coupled to the first end of the first switch, the second end of the first switch is coupled to the first end of the first resistor R1, the second end of the first resistor R1 is coupled to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The control end of the first switch receives a reference voltage Vref.
The second end of the first resistor R1, i.e. the first end of the second resistor R2, is coupled to a delay module, and the first switch, the first resistor R1 and the second resistor R2 divide the power supply Vdd to generate a resistor divided voltage Va ', and the resistor divided voltage Va' is delayed by the delay module to generate a delayed divided voltage Va and is used as the first input end of the comparator.
The second input of the comparator also receives the reference voltage as an input and the output of the comparator is the POR output signal.
In addition, the external POR signal also serves as a signal for turning on the comparator into an operating state, i.e., an enable (enable) signal of the comparator.
In this type of embodiment, the first switch serves to ensure that the bandgap reference voltage Vref is established prior to the voltage division Va' generated by the first resistor and the second resistor.
In this type of embodiment, referring to fig. 2, the delay module functions to further ensure that the bandgap reference voltage Vref is established prior to the delayed divided voltage Va.
The combination of the first switch and the delay module eventually avoids multiple intersections at the input end during the voltage establishment process, thereby generating burrs at the output end.
In addition, according to the bandgap reference voltage Vref, the comparator generates a POR output signal, and by introducing an external POR signal to enable the comparator, it is ensured that the comparator does not flip erroneously under low voltage.
Referring to fig. 3, a schematic diagram of a further preferred class of embodiments of the present invention is shown.
The POR circuit comprises a first switch, a first resistor R1, a second resistor R2, a delay module, a comparator, a hysteresis module, a first filter capacitor, a second filter capacitor and a third filter capacitor.
The POR circuit outputs a POR output signal and receives an external POR signal and a reference voltage Vref from an external circuit. The reference voltage Vref is a bandgap reference voltage generated by a bandgap (bandgap) reference source.
The power supply is coupled with the first end of the first switch, the second end of the first switch is coupled with the first end of the first resistor R1, the second end of the first resistor R1 is coupled with the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The control end of the first switch receives a reference voltage Vref.
The second end of the first resistor R1, i.e. the first end of the second resistor R2, is coupled to a delay module, and the voltage division of the power supply by the first resistor R1 and the second resistor R2 generates a resistor voltage division Va ', and the resistor voltage division Va' is delayed by the delay module to generate a delayed voltage division Va and is used as the first input end of the comparator.
The second input of the comparator also receives the reference voltage as an input and the output of the comparator is the POR output signal.
In addition, the external POR signal also serves as a signal for turning on the comparator into an operating state, i.e., an enable (enable) signal of the comparator.
In this type of embodiment, the first switch serves to ensure that the bandgap reference voltage Vref is established prior to the voltage division Va' generated by the first resistor and the second resistor.
In this type of embodiment, the delay module functions to further ensure that the bandgap reference voltage Vref is established prior to the delayed divided voltage Va.
The combination of the first switch and the delay module eventually avoids multiple intersections at the input end during the voltage establishment process, thereby generating burrs at the output end.
In addition, according to the band gap reference voltage Vref, the comparator generates a POR output signal, and the comparator is started by introducing an external POR signal, so that the comparator is ensured to be started at a higher voltage, and the false overturn of the comparator under a low voltage is avoided.
Referring to fig. 4, the comparator is enabled by an external POR signal, and when the external POR signal is flipped, ripple may be generated to the input and output due to charge feedthrough, resulting in glitch of the output of the comparator.
To avoid glitches at the output due to charge feed-through, referring to the lower right corner of fig. 4, the comparator is coupled to the output by applying a first filter capacitor to the POR output signal; applying a second filter capacitor to the bandgap reference voltage Vref, wherein the capacitor is coupled to the second input terminal of the comparator; applying a third filter capacitor to the delayed divided voltage Va, i.e. the capacitor is coupled to the first input of the comparator, reduces the ripple effect to some extent. The filter capacitors are respectively connected to two inputs and one output end of the comparator.
In addition, referring to fig. 5, in order to prevent the ripple from causing the comparator to output a burr during the power-up process, for example, with continued reference to fig. 3, the hysteresis module in this embodiment includes at least one inverter and one switching tube, where the inverter and the switching tube and the second resistor R2 together form the hysteresis module.
The POR output signal is also used as an input of an inverter, which in turn is used as a control signal for the switching tube. One end (such as a source) of the switch tube is grounded, and the other end (such as a drain) of the switch tube is coupled to the first end of the second resistor R2. The switching tube, for example an NMOS tube.
Further, the inversion point of the external POR signal is earlier than the intersection point of the delayed divided voltage Va and the reference voltage Vref, in other words, the comparator has a certain state at the input before the comparator is turned on, so as to ensure that the POR output signal is stable and reliable.
Numerous specific details are set forth in the above description in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. The utility model provides a power on reset circuit which characterized in that:
the power-on reset circuit includes: the circuit comprises a first switch, a first resistor, a second resistor, a delay module and a comparator;
the first switch, the first resistor and the second resistor divide the power supply to obtain a resistor division voltage (Va');
the delay module delays the resistive voltage division (Va') to obtain a delayed voltage division (Va);
the comparator compares the delayed divided voltage (Va) with a bandgap reference voltage (Vref) to obtain a POR output signal (POR OUT).
2. The power-on reset circuit of claim 1, wherein:
the comparator also receives an external POR signal from outside, which is used to enable the comparator.
3. The power-on reset circuit of claim 1, wherein:
the first input end of the comparator is coupled with a third filter capacitor;
the second input end of the comparator is coupled with the second filter capacitor.
4. A power-on reset circuit as claimed in claim 3, wherein:
the output end of the comparator is coupled with the first filter capacitor.
5. The power-on reset circuit of claim 1, wherein:
the power supply is coupled with the first end of the first switch, the second end of the first switch is coupled with the first end of the first resistor, the second end of the first resistor is coupled with the first end of the second resistor, and the second end of the second resistor is grounded.
6. The power-on reset circuit of claim 5, wherein:
the control end of the first switch receives the band gap reference voltage as an input.
7. The power-on reset circuit of claim 6, wherein:
the first resistor second end is coupled with the delay module.
8. The power-on reset circuit of claim 7, wherein:
the power-on reset circuit further comprises a hysteresis module;
the hysteresis module at least comprises an inverter and a switching tube;
the POR output signal is used as the input of the inverter, and the output signal of the inverter is used as the control signal of the switching tube.
9. The power-on reset circuit of claim 8, wherein:
one end of the switching tube is grounded, and the other end of the switching tube is coupled with the first end of the second resistor.
10. The power-on reset circuit of claim 2, wherein:
the inversion point of the external POR signal is earlier than the intersection of the delayed divided voltage (Va) and the bandgap reference voltage (Vref).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410157692.4A CN117713782B (en) | 2024-02-04 | 2024-02-04 | Power-on reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410157692.4A CN117713782B (en) | 2024-02-04 | 2024-02-04 | Power-on reset circuit |
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| CN117713782A true CN117713782A (en) | 2024-03-15 |
| CN117713782B CN117713782B (en) | 2024-04-26 |
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| CN202410157692.4A Active CN117713782B (en) | 2024-02-04 | 2024-02-04 | Power-on reset circuit |
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| CN213585745U (en) * | 2020-12-18 | 2021-06-29 | 福建江夏学院 | Circuit for realizing high efficiency and low power consumption of power supply monitoring |
| CN112311383A (en) * | 2020-12-18 | 2021-02-02 | 福建江夏学院 | Circuit for realizing high-efficiency and low-power consumption of power supply monitoring and working method |
| CN217469914U (en) * | 2022-04-29 | 2022-09-20 | 上海料聚微电子有限公司 | Power-on reset circuit |
| CN116633333A (en) * | 2023-05-30 | 2023-08-22 | 灵动微电子(苏州)有限公司 | Power-on reset circuit and integrated circuit |
| CN117240270A (en) * | 2023-09-15 | 2023-12-15 | 深圳市紫光同创电子有限公司 | Power-on reset circuit, chip and electronic equipment |
| CN117118417A (en) * | 2023-09-26 | 2023-11-24 | 北京昂瑞微电子技术股份有限公司 | Power-on reset circuit |
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| CN117713782B (en) | 2024-04-26 |
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