CN213585745U - Circuit for realizing high efficiency and low power consumption of power supply monitoring - Google Patents
Circuit for realizing high efficiency and low power consumption of power supply monitoring Download PDFInfo
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- CN213585745U CN213585745U CN202023058627.2U CN202023058627U CN213585745U CN 213585745 U CN213585745 U CN 213585745U CN 202023058627 U CN202023058627 U CN 202023058627U CN 213585745 U CN213585745 U CN 213585745U
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Abstract
The utility model provides a circuit of high-efficient low-power consumption of realization power control, bleeder circuit, reference voltage source, comparator, high-speed power-on detection circuitry, NOR gate, clock production and turn-off circuit, time delay module and output drive module. The voltage division circuit is used for generating a reset threshold voltage which is in a certain proportion to the input voltage; the reference voltage source is used for generating a reference voltage which is independent of the power supply voltage and the temperature; the comparator is used for comparing the divided voltage with a reference voltage; the high-speed power-on detection circuit is used for generating an on-chip reset signal of the power supply monitoring circuit with anti-interference capability; the clock generating and turning-off circuit is used for generating a clock signal of the delay unit and turning off the clock generating circuit; the delay module is used for timing. The high-speed power-on detection circuit is introduced, the problem of reset failure caused by untimely comparator turnover or power burr interference is solved, and meanwhile, the clock turn-off circuit is introduced, so that the power consumption is effectively reduced.
Description
Technical Field
The utility model belongs to integrated circuit's power control field especially relates to a circuit of realizing high-efficient low-power consumption of power control.
Background
With the development of semiconductor technology and electronic technology, the portable electronic product has improved requirements on the stability of a microprocessor system, including data protection under the conditions of power-on and power-off of a power supply, burr interference resistance caused by load and power supply switching and the like, due to functionalization and rapidness. Under this demand, microprocessor systems employing power monitoring are widely used.
The existing monitoring circuit is a reset circuit formed by RC, a Schmidt-based level detection circuit and a method of adopting phase delays with different capacitance charging and discharging time and the like to achieve the monitoring purpose, although the method can achieve reset when a power supply is powered on or powered off, the method does not relate to glitch interference caused by rapid power supply or load change, and is not suitable for application environments with wide input voltage and wide load change. Even the existing independent reset chips mostly rely on the single detection of the reset threshold voltage by the comparator, and the independent reset chips are compared with the reference voltage source together to generate a level detection signal, and the level detection signal is sent to the timer and then outputs a reset signal with a certain width to the digital logic control circuit. The circuit is simple, but still has great defect in interference resistance and power consumption. When the power supply is electrified at a high speed, because the reference voltage needs time for starting, the level detection signal can not be normally generated, so that the reset failure is caused, and the stability of the system is reduced; when the power supply ripple is large, the collected voltage is jittered up and down, and the system is reset repeatedly. Although the above problem can be solved by increasing the bandwidth of the comparator, the power consumption problem caused thereby makes the power supply monitoring chip unsuitable for low power consumption products such as portable devices.
SUMMERY OF THE UTILITY MODEL
Aiming at the defects and blanks existing in the prior art, the utility model provides a circuit for realizing high-efficiency and low power consumption of power monitoring, which introduces a high-speed power-on detection circuit on the basis of a monitoring circuit for detecting the reset threshold voltage based on a comparator, improves the power-on detection speed of the power voltage through a branch circuit, and skillfully obtains the power-on reset signal in a chip without power source burr interference by adopting the phase delay property between the power-on detection signal and the burr identification signal so as to improve the monitoring efficiency; furthermore, a hysteresis comparator with a double feedback mechanism is adopted, so that the high-efficiency response is ensured, and the power consumption is reduced; furthermore, a turn-off control circuit is introduced, namely, the output reset signal is inverted and then used as a control signal PD to control the clock generation circuit to turn off, and the clock generation circuit is turned off when the reset is finished, so that the static power consumption of the system is reduced. Compare with current voltage detection monitor circuit, the utility model discloses introduced high-speed last electric detection circuitry, avoided because of the comparator upset not too late or the power burr disturbs the inefficacy problem that resets that arouses, introduced the clock turn-off circuit simultaneously, turn-off the clock after the completion that resets and produce the circuit, reduced the consumption effectively.
The utility model discloses specifically adopt following technical scheme:
a circuit for realizing power supply monitoring with high efficiency and low power consumption is characterized by comprising: the circuit comprises a voltage division circuit, a reference voltage source, a comparator, a high-speed power-on detection circuit, a NOR gate, a clock generation and turn-off circuit, a delay module and an output driving module;
the voltage dividing circuit consists of series resistors, one end of the voltage dividing circuit is connected with a power supply, the other end of the voltage dividing circuit is grounded, and a common end V is connected with a common terminalDIVThe + input end of the comparator is connected; the output end Vref of the reference voltage source is connected with the input end of the comparator; the output end Vo of the comparator is connected with one input end of the NOR gate NOR through a first-stage inverter; the other input end of the NOR gate NOR is connected with the output end V of the high-speed power-on detection circuitDETThe output end is connected with a trigger signal end R of the delay module; the delay module is a delay circuit formed by a plurality of D triggers, the clock input end of the delay module is connected with the clock signal output end of the clock generating and turning-off circuit, one output end Q is connected with the input end of the output driving module, and the other output end Q' is connected with the turning-off signal PD end of the clock generating and turning-off circuit; the output driving module is connected with the microprocessor;
the voltage division circuit is used for generating a reset threshold voltage which is in a certain proportion to the input voltage; the reference voltage source is used for generating a reference voltage which is irrelevant to the power supply voltage and the temperature; the comparator is used for comparing the divided voltage with a reference voltage, outputting a high level when the divided voltage reaches a threshold voltage, and controlling an enabling end of the delay module together with an on-chip reset signal after phase inversion so as to generate a reset signal with a certain time delay; the high-speed power-on detection circuit is used for generating an on-chip reset signal of the power supply monitoring circuit with anti-interference capability; the clock generating and turning-off circuit is used for generating a clock signal of the delay unit and turning off the clock generating circuit; the delay module is used for timing, and the timing time is determined by the number n of the D triggers.
Preferably, the high-speed power-up detection circuit includes: the circuit comprises a level detection module, a biasing module, a burr interference removal module, a second inverter INV2, a third inverter INV3 and a NAND gate NAND;
the level detection module includes: the circuit comprises a first resistor R1, a first capacitor C1, a first PMOS transistor PM1, a second PMOS transistor PM2 and a first inverter INV 1; one end of the first resistor R1 is connected with a power supply VCC, and the other end is connected with a first capacitor C1; the other end of the first capacitor C1 is grounded GND; the source electrode of the first PMOS tube PM1 is connected with a power supply, the drain electrode of the first PMOS tube PM1 is connected with the source electrode of the second PMOS tube PM2, the grid electrodes of the first PMOS tube PM1 and the second PMOS tube PM2 are connected with the common end of a first resistor R1 and a first capacitor C1, and the drain electrode of the second PMOS tube PM2 is connected with the input end of a second inverter INV 2;
the bias module comprises a first current source Ibias1A first NMOS transistor NM1 and a second NMOS transistor NM 2; the first current source Ibias1One end of the NMOS tube is connected with a power supply VCC, and the other end of the NMOS tube is connected with the drain electrode and the grid electrode of the first NMOS tube NM 1; the source of the first NMOS transistor NM1 is grounded; the grid electrode of the second NMOS tube NM2 is connected to the grid electrode of the first NMOS tube NM1, the source electrode is grounded, and the drain electrode is connected with the input end of the second inverter INV 2;
the glitch removing module comprises a second current source Ibias2The third PMOS transistor PM3, the fourth PMOS transistor PM4 and the second capacitor C2; the second current source Ibias2One end of the third PMOS tube PM3 is grounded, and the other end of the third PMOS tube PM3 is connected with the drain electrode; the drain electrode of the third PMOS tube PM3 is connected with the grid electrode, and the source electrode is connected with a power supply VCC; the grid electrode of the fourth PMOS tube PM4 is connected with the grid electrode of the third PMOS tube PM3, the source electrode is connected with a power supply VCC, and the drain electrode is connected with one end of a second capacitor C2 and is connected to one input end of a NAND gate; the other end of the second capacitor C2 is grounded; the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is connected to the other input end of the NAND gate NAND.
Preferably, the clock generation and shutdown circuit includes: a clock gating control circuit, a first comparator A1, a second comparator A2, and an output control circuit;
the positive input end of the first comparator A1 is connected with the input end of the fifth inverter INV5 and the drains of the sixth PMOS pipe PM6 and the ninth PMOS pipe PM9, the negative input end is connected with the output end of the fifth inverter INV5 and the input end of the sixth inverter INV6, and the output end is connected with the negative input end V1 of the second comparator A2; the positive input end of the second comparator A2 is connected with the common end of a resistor R2 and a capacitor C3, the other end of the resistor R2 is connected with a power supply, and the other end of the capacitor C3 is grounded; the negative output end of the second comparator A2 is connected with the grid electrode of a fifth PMOS tube PM5, and the positive output end of the second comparator A2 is connected with the grid electrode of a sixth PMOS tube PM 6; the source electrodes of the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are connected with a power supply, the drain electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the eighth NMOS tube NM8, and the drain electrode of the sixth PMOS tube PM6 is connected with the drain electrode of the ninth NMOS tube NM 9; the drain of the seventh NMOS transistor NM7 is connected to the gates of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9, the source is connected to the sources of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 and grounded, and the gate is connected to the clock turn-off control circuit.
Preferably, the clock gating control circuit includes: a fourth inverter INV4, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6 and a reference current source Ibias；
An input end of the fourth inverter INV4 and a gate of the fourth NMOS transistor NM4 are connected to a gate of the seventh NMOS transistor NM 7; the output end of the fourth inverter INV4 is connected to the gate of the third NMOS transistor NM 3; the drain of the third NMOS transistor NM3 is connected with a reference current source IbiasThe drain electrode of the fifth NMOS transistor NM5, the source electrode of which is respectively connected with the drain electrode of the fourth NMOS transistor NM4, the grid electrode of the fifth NMOS transistor NM5 and the grid electrode of the sixth NMOS transistor NM 6; the sources of the fourth NMOS transistor NM4, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are all grounded; the drain of the sixth NMOS transistor NM6 is connected to Ib via a reference current source IbiasThe mirror image is generated.
Preferably, the first comparator a1 and the second comparator a2 adopt hysteresis comparators.
Preferably, the first PMOS transistor PM1 and the second PMOS transistor PM2 are replaced by a level detection network formed by connecting more than 2 PMOS transistors in series.
Compared with the prior art, the utility model discloses and preferred scheme thereof has following beneficial effect: the utility model introduces a high-speed power-on detection circuit on the basis of a monitoring circuit for detecting the reset threshold voltage based on a comparator, improves the power-on detection speed of the power supply voltage through the branch circuit, and skillfully obtains the on-chip power-on reset signal without power supply burr interference by adopting the phase delay property between the power-on detection signal and the burr identification signal so as to improve the monitoring efficiency; furthermore, a hysteresis comparator with a double feedback mechanism is adopted, so that the high-efficiency response is ensured, and the power consumption is reduced; furthermore, a turn-off control circuit is introduced, namely, the output reset signal is inverted and then used as a control signal PD to control the clock generation circuit to turn off, and the clock generation circuit is turned off when the reset is finished, so that the static power consumption of the system is reduced. Compare with current power monitoring circuit, the utility model discloses introduced high-speed last electric detection circuitry, avoided because of the comparator upset not too late or the reset failure problem that the power burr interference arouses, introduced the clock turn-off circuit simultaneously, turn-off the clock after the completion that resets and produce the circuit, reduced the consumption effectively.
Drawings
The invention will be described in further detail with reference to the following drawings and detailed description:
FIG. 1 is a schematic diagram of a monitoring circuit of a processor according to an embodiment of the present invention;
fig. 2 is a schematic diagram of the high-speed power-on detection circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a clock generation circuit with a turn-off control circuit according to an embodiment of the present invention.
Detailed Description
In order to make the features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail as follows:
as shown in fig. 1 to fig. 3, the present embodiment provides a circuit for realizing high efficiency and low power consumption of power supply monitoring, including: the circuit comprises a voltage division circuit, a reference voltage source, a comparator, a high-speed power-on detection circuit, a NOR gate, a clock generation and turn-off circuit, a delay module and an output driving module.
The voltage dividing circuit consists of series resistors, one end of the resistor is connected with a power supply, the other end of the resistor is grounded, and a common end V is connected with a common terminalDIVThe + input end of the comparator is connected; the output end Vref of the reference voltage source is connected with the input end of the comparator; the output end Vo of the comparator is connected with one input end of the NOR gate NOR through the first-stage inverter; the other input end of the NOR gate NOR is connected with the output end V of the high-speed power-on detection circuitDETThe output end is connected with a trigger signal end R of the delay module; the delay module is a delay circuit formed by a plurality of D triggers, the clock input end of the delay module is connected with the clock signal output end of the clock generating and turning-off circuit, one output end Q is connected with the input end of the output driving module, and the other output end Q' is connected with the turning-off signal PD end of the clock generating and turning-off circuit; output drive moduleThe output end of the output driving module is shaped and then respectively generates reset signals after being connected with the microprocessor
And an inverted reset signal
(ii) a PD is composed of
The signal is obtained after first-stage phase inversion.
The voltage division circuit is used for generating a reset threshold voltage which is in a certain proportion to the input voltage; the reference voltage source is used for generating a reference voltage which is independent of the power supply voltage and the temperature; the comparator is used for comparing the divided voltage with a reference voltage, outputting a high level when the divided voltage reaches a threshold voltage, and controlling an enabling end of the delay module together with an on-chip reset signal after phase inversion so as to generate a reset signal with a certain time delay; the high-speed power-on detection circuit is used for generating an on-chip reset signal of the power supply monitoring circuit with anti-interference capability; the clock generating and turning-off circuit is used for generating a clock signal of the delay unit and turning off the clock generating circuit; the time delay module is used for timing, the timing time t is determined by the number n of the D triggers, and t =2n×Tclk。
The high-speed power-on detection circuit comprises: the circuit comprises a level detection module, a biasing module, a burr interference removal module, a second inverter INV2, a third inverter INV3 and a NAND gate NAND;
the level detection module includes: the circuit comprises a first resistor R1, a first capacitor C1, a first PMOS transistor PM1, a second PMOS transistor PM2 and a first inverter INV 1; one end of the first resistor R1 is connected with a power supply VCC, and the other end is connected with a first capacitor C1; the other end of the first capacitor C1 is grounded GND; the source electrode of the first PMOS tube PM1 is connected with a power supply, the drain electrode of the first PMOS tube PM1 is connected with the source electrode of the second PMOS tube PM2, the grid electrodes of the first PMOS tube PM1 and the second PMOS tube PM2 are connected with the common end of the first resistor R1 and the first capacitor C1, and the drain electrode of the second PMOS tube PM2 is connected with the input end of the second inverter INV 2;
the bias module comprises a first current source Ibias1The first stepAn NMOS transistor NM1 and a second NMOS transistor NM 2; a first current source Ibias1One end of the NMOS tube is connected with a power supply VCC, and the other end of the NMOS tube is connected with the drain electrode and the grid electrode of the first NMOS tube NM 1; the source of the first NMOS transistor NM1 is grounded; the grid electrode of the second NMOS tube NM2 is connected to the grid electrode of the first NMOS tube NM1, the source electrode is grounded, and the drain electrode is connected to the input end of the second inverter INV 2;
the glitch removing module comprises a second current source Ibias2The third PMOS transistor PM3, the fourth PMOS transistor PM4 and the second capacitor C2; a second current source Ibias2One end of the third PMOS tube PM3 is grounded, and the other end of the third PMOS tube PM3 is connected with the drain electrode; the drain electrode of the third PMOS pipe PM3 is connected with the grid electrode, and the source electrode is connected with a power supply VCC; the grid electrode of the fourth PMOS tube PM4 is connected with the grid electrode of the third PMOS tube PM3, the source electrode is connected with the power supply VCC, and the drain electrode is connected with one end of the second capacitor C2 and is connected to one input end of the NAND gate; the other end of the second capacitor C2 is grounded; the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is connected to the other input end of the NAND gate NAND; the output of NAND is marked as signal VDET 。
As shown in fig. 2, in the present embodiment, a level detection network is formed by the first PMOS transistor PM1 and the second PMOS transistor PM 2. The level detection network may be replaced by a level detection network formed by connecting more than 2 PMOS transistors in series as required, and the connection manner between the plurality of PMOS transistors is the same as that between the first PMOS transistor PM1 and the second PMOS transistor PM 2.
The stability of the portable microprocessor system is an improved object of the embodiment, and the preferred device is a power supply monitoring system.
The clock generation and shutdown circuit includes: a clock gating control circuit, a first comparator A1, a second comparator A2, and an output control circuit;
the positive input end of the first comparator A1 is connected with the input end of the fifth inverter INV5 and the drains of the sixth PMOS transistor PM6 and the ninth PMOS transistor PM9, the negative input end is connected with the output end of the fifth inverter INV5 and the input end of the sixth inverter INV6, and the output end is connected with the negative input end V1 of the second comparator A2; the positive input end of the second comparator A2 is connected with the common end of the resistor R2 and the capacitor C3, the other end of the resistor R2 is connected with the power supply, and the other end of the capacitor C3 is grounded; the negative output end of the second comparator A2 is connected with the grid electrode of the fifth PMOS tube PM5, and the positive output end of the second comparator A2 is connected with the grid electrode of the sixth PMOS tube PM 6; the source electrodes of the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are connected with a power supply, the drain electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the eighth NMOS tube NM8, and the drain electrode of the sixth PMOS tube PM6 is connected with the drain electrode of the ninth NMOS tube NM 9; the drain of the seventh NMOS transistor NM7 is connected to the gates of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9, the source is connected to the sources of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 and grounded, and the gate is connected to the clock turn-off control circuit.
The clock turn-off control circuit includes: a fourth inverter INV4, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6 and a reference current source Ibias；
An input end of the fourth inverter INV4 and a gate of the fourth NMOS transistor NM4 are connected to a gate of the seventh NMOS transistor NM 7; the output end of the fourth inverter INV4 is connected to the gate of the third NMOS transistor NM 3; the drain of the third NMOS transistor NM3 is connected to the reference current source IbiasThe drain electrode of the fifth NMOS transistor NM5, the source electrode of which is respectively connected with the drain electrode of the fourth NMOS transistor NM4, the grid electrode of the fifth NMOS transistor NM5 and the grid electrode of the sixth NMOS transistor NM 6; the sources of the fourth NMOS transistor NM4, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are all grounded; the drain of the sixth NMOS transistor NM6 is connected to Ib via a reference current source IbiasThe mirror image is generated. The tail current sources of the first comparator A1 and the second comparator A2 are nI respectivelybAnd mIb，IbThe reference current source I can be controlled by switching offbiasMirror generation, where n and m are scaling factors, in this embodiment, Ib200nA, n and m are taken as 4 and 6 respectively.
In the present embodiment, the first comparator a1 and the second comparator a2 employ hysteresis comparators.
In this embodiment, the voltage dividing circuit includes: composed of resistors connected in series, and selecting a node threshold voltage V according to industry standard value monitored by a power supplyDIV=2.93V (@ VCC = 3.3V) and VDIVIn the case where the voltage is not lower than 4.63V (@ VCC = 5V), the two threshold voltages are switched by dividing the resistance into unit resistances and connecting the unit resistances, and adjusting the number of the unit resistances connected.
In the high-speed power-on detection circuit, the power-on detection circuit with phase delayThe measurement signal C and the burr identification signal B are NAND-operated to obtain a high-level signal V with a certain delay length t1 (t 1 is determined by R1, C1 and C2)DET. The specific implementation process of the circuit is as follows: the power supply is charged by the resistor R1 and the capacitor C1, and sends a low level signal to a level detection network composed of n (for example, n =2 is shown in fig. 2) PMOS transistors after passing through the inverter INV 1. When the power supply voltage rises to enable n PMOS tubes to be conducted, the PMOS tubes are inverted to be in high level, the waveform of the point A is shaped by inverters INV2 and INV3 to obtain a waveform C, the waveform C and a burr identification signal B are sent to a NAND gate to obtain an output signal V of the power-on detection circuitDET. Since the detection level A varies closely with the supply voltage, VDETThe power supply change can be quickly followed up, so that the problem that the branch of the comparator in the figure 1 cannot be timely turned over to cause reset failure during high-speed power-on is solved, and the reset effectiveness is improved. As shown in FIG. 2, the glitch immunity circuit is composed of a reference current source IbiasControlling the charging and discharging of the capacitor C2, the level inversion and the holding time of the branch output glitch identification signal B are only equal to IbiasAnd C2, regardless of the supply voltage VCC.
In the embodiment, the turn-off control circuit is introduced into the clock generation circuit, namely, the output reset signal is inverted and then serves as the control signal PD to be sent to the turn-off control circuit, and the clock generation circuit is turned off when the reset is finished, so that the static power consumption of the system is reduced. The RESET signal RESET is a low level signal that lasts for a certain time length t, the time length t is determined by the number n of D flip-flops provided in the delay unit, and t =2n×Tclk(ii) a The reset signal is used as a PD signal for turning off the control circuit after being inverted, and the low level is effective. As shown in fig. 3, when PD =0, NM3 is turned on, NM4 is turned off, and NM5 has its gate-drain turned on, and IbiasNM6 constitutes a current mirror, IbAnd IbiasSupplying the clock generation circuit with a certain proportion, and starting the clock generation circuit to work; when PD =1, NM3 is off, NM4 is on, NM5 and NM6 are off, Ib=0, the clock generation circuit stops operating.
The clock generation and turn-off circuit inverts the output reset signal and transmits the inverted reset signal as a control signal PD to the clock turn-off control circuit, and the low level is effective; and is used for turning off the clock generation circuit when the reset is finished.
In this embodiment, the first resistor R1 and the first capacitor C1 form an RC series circuit, and the voltage on the capacitor is VC= VCC (1-exp (-t/RC)); when the power is on, the charging and discharging time t and VC are changed along with the change of VCC, and VCAfter being shaped by the INV1, the level detection network formed by the PM1 and the PM2 controls level inversion to form high level output, which is marked as a signal A (the level inversion point can be adjusted according to the number of the PMOS tubes in series of the level detection network); the glitch interference-resistant circuit is composed of a reference current source IbiasControlling the charge and discharge of the capacitor C2, the level inversion and the holding time of the branch output signal B are only equal to IbiasAnd C2, independently of the supply voltage VCC; the signal A is subjected to reverse phase shaping to obtain a signal C and a signal B which have phase delay due to different turnover levels, and the signal C and the signal B are subjected to NAND operation to obtain an on-chip reset signal V with a burr anti-interference functionDET(ii) a The signal and an output inverted signal VO' of the comparator are subjected to OR operation to obtain a trigger signal R to an R trigger end of the delay unit, and the signal R is not only a trigger signal, but also an on-chip power-on reset signal. The R signal not only ensures the reliable work of the internal trigger of the power supply monitoring circuit, but also ensures the resetting effectiveness of the power supply monitoring circuit to the microprocessor after the power supply is quickly electrified. And a turn-off control module is introduced to turn off the clock circuit while resetting is completed, so that low power consumption of the system is ensured. The realization process is as follows: when the power supply is quickly powered on, the level detection network responds to the comparator and sends out a trigger signal to enable the delay unit in the power supply monitoring circuit to start working, meanwhile, the reset signal is transmitted to the microprocessor, after the comparator works stably, the monitoring circuit continues to stably output the reset signal and sends the inverted signal to the delay unit, and when the preset time value is reached, the clock generation circuit is turned off, so that the power consumption is reduced.
The present invention is not limited to the above-mentioned preferred embodiments, and any person can derive other various circuits for realizing high efficiency and low power consumption of power monitoring under the teaching of the present invention.
Claims (6)
1. A circuit for realizing power supply monitoring with high efficiency and low power consumption is characterized by comprising: the circuit comprises a voltage division circuit, a reference voltage source, a comparator, a high-speed power-on detection circuit, a NOR gate, a clock generation and turn-off circuit, a delay module and an output driving module;
the voltage dividing circuit consists of series resistors, one end of the voltage dividing circuit is connected with a power supply, the other end of the voltage dividing circuit is grounded, and a common end V is connected with a common terminalDIVThe + input end of the comparator is connected; the output end Vref of the reference voltage source is connected with the input end of the comparator; the output end Vo of the comparator is connected with one input end of the NOR gate NOR through a first-stage inverter; the other input end of the NOR gate NOR is connected with the output end V of the high-speed power-on detection circuitDETThe output end is connected with a trigger signal end R of the delay module; the delay module is a delay circuit formed by a plurality of D triggers, the clock input end of the delay module is connected with the clock signal output end of the clock generating and turning-off circuit, one output end Q is connected with the input end of the output driving module, and the other output end Q' is connected with the turning-off signal PD end of the clock generating and turning-off circuit; the output driving module is connected with the microprocessor;
the voltage division circuit is used for generating a reset threshold voltage which is in a certain proportion to the input voltage; the reference voltage source is used for generating a reference voltage which is irrelevant to the power supply voltage and the temperature; the comparator is used for comparing the divided voltage with a reference voltage, outputting a high level when the divided voltage reaches a threshold voltage, and controlling an enabling end of the delay module together with an on-chip reset signal after phase inversion so as to generate a reset signal with a certain time delay; the high-speed power-on detection circuit is used for generating an on-chip reset signal of the power supply monitoring circuit with anti-interference capability; the clock generating and turning-off circuit is used for generating a clock signal of the delay unit and turning off the clock generating circuit; the delay module is used for timing, and the timing time is determined by the number n of the D triggers.
2. The circuit for realizing power supply monitoring with high efficiency and low power consumption according to claim 1, wherein: the high-speed power-up detection circuit comprises: the circuit comprises a level detection module, a biasing module, a burr interference removal module, a second inverter INV2, a third inverter INV3 and a NAND gate NAND;
the level detection module includes: the circuit comprises a first resistor R1, a first capacitor C1, a first PMOS transistor PM1, a second PMOS transistor PM2 and a first inverter INV 1; one end of the first resistor R1 is connected with a power supply VCC, and the other end is connected with a first capacitor C1; the other end of the first capacitor C1 is grounded GND; the source electrode of the first PMOS tube PM1 is connected with a power supply, the drain electrode of the first PMOS tube PM1 is connected with the source electrode of the second PMOS tube PM2, the grid electrodes of the first PMOS tube PM1 and the second PMOS tube PM2 are connected with the common end of a first resistor R1 and a first capacitor C1, and the drain electrode of the second PMOS tube PM2 is connected with the input end of a second inverter INV 2;
the bias module comprises a first current source Ibias1A first NMOS transistor NM1 and a second NMOS transistor NM 2; the first current source Ibias1One end of the NMOS tube is connected with a power supply VCC, and the other end of the NMOS tube is connected with the drain electrode and the grid electrode of the first NMOS tube NM 1; the source of the first NMOS transistor NM1 is grounded; the grid electrode of the second NMOS tube NM2 is connected to the grid electrode of the first NMOS tube NM1, the source electrode is grounded, and the drain electrode is connected with the input end of the second inverter INV 2;
the glitch removing module comprises a second current source Ibias2The third PMOS transistor PM3, the fourth PMOS transistor PM4 and the second capacitor C2; the second current source Ibias2One end of the third PMOS tube PM3 is grounded, and the other end of the third PMOS tube PM3 is connected with the drain electrode; the drain electrode of the third PMOS tube PM3 is connected with the grid electrode, and the source electrode is connected with a power supply VCC; the grid electrode of the fourth PMOS tube PM4 is connected with the grid electrode of the third PMOS tube PM3, the source electrode is connected with a power supply VCC, and the drain electrode is connected with one end of a second capacitor C2 and is connected to one input end of a NAND gate; the other end of the second capacitor C2 is grounded; the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is connected to the other input end of the NAND gate NAND.
3. The circuit for realizing power supply monitoring with high efficiency and low power consumption according to claim 2, wherein: the clock generation and shutdown circuit includes: a clock gating control circuit, a first comparator A1, a second comparator A2, and an output control circuit;
the positive input end of the first comparator A1 is connected with the input end of the fifth inverter INV5 and the drains of the sixth PMOS pipe PM6 and the ninth PMOS pipe PM9, the negative input end is connected with the output end of the fifth inverter INV5 and the input end of the sixth inverter INV6, and the output end is connected with the negative input end V1 of the second comparator A2; the positive input end of the second comparator A2 is connected with the common end of a resistor R2 and a capacitor C3, the other end of the resistor R2 is connected with a power supply, and the other end of the capacitor C3 is grounded; the negative output end of the second comparator A2 is connected with the grid electrode of a fifth PMOS tube PM5, and the positive output end of the second comparator A2 is connected with the grid electrode of a sixth PMOS tube PM 6; the source electrodes of the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are connected with a power supply, the drain electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the eighth NMOS tube NM8, and the drain electrode of the sixth PMOS tube PM6 is connected with the drain electrode of the ninth NMOS tube NM 9; the drain of the seventh NMOS transistor NM7 is connected to the gates of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9, the source is connected to the sources of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 and grounded, and the gate is connected to the clock turn-off control circuit.
4. The circuit for realizing power supply monitoring with high efficiency and low power consumption according to claim 3, wherein: the clock gating control circuit includes: a fourth inverter INV4, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6 and a reference current source Ibias；
An input end of the fourth inverter INV4 and a gate of the fourth NMOS transistor NM4 are connected to a gate of the seventh NMOS transistor NM 7; the output end of the fourth inverter INV4 is connected to the gate of the third NMOS transistor NM 3; the drain of the third NMOS transistor NM3 is connected with a reference current source IbiasThe drain electrode of the fifth NMOS transistor NM5, the source electrode of which is respectively connected with the drain electrode of the fourth NMOS transistor NM4, the grid electrode of the fifth NMOS transistor NM5 and the grid electrode of the sixth NMOS transistor NM 6; the sources of the fourth NMOS transistor NM4, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are all grounded; the drain of the sixth NMOS transistor NM6 is connected to Ib via a reference current source IbiasThe mirror image is generated.
5. The circuit for realizing power supply monitoring with high efficiency and low power consumption according to claim 3 or 4, wherein: the first comparator a1 and the second comparator a2 employ hysteresis comparators.
6. The circuit for realizing power supply monitoring with high efficiency and low power consumption as claimed in any one of claims 2-4, wherein: the first PMOS pipe PM1 and the second PMOS pipe PM2 are replaced by a level detection network formed by more than 2 PMOS pipes in series.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114041639A (en) * | 2021-11-10 | 2022-02-15 | 陕西亚成微电子股份有限公司 | Sensor power supply management system and method |
| CN115985360A (en) * | 2023-01-28 | 2023-04-18 | 广州市微嵌计算机科技有限公司 | Data protection circuit applied to abnormal power failure of memory |
| CN117713782A (en) * | 2024-02-04 | 2024-03-15 | 成都电科星拓科技有限公司 | Power-on reset circuit |
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2020
- 2020-12-18 CN CN202023058627.2U patent/CN213585745U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114041639A (en) * | 2021-11-10 | 2022-02-15 | 陕西亚成微电子股份有限公司 | Sensor power supply management system and method |
| CN114041639B (en) * | 2021-11-10 | 2022-09-02 | 陕西亚成微电子股份有限公司 | Sensor power supply management system and method |
| CN115985360A (en) * | 2023-01-28 | 2023-04-18 | 广州市微嵌计算机科技有限公司 | Data protection circuit applied to abnormal power failure of memory |
| CN115985360B (en) * | 2023-01-28 | 2023-09-19 | 广州市微嵌计算机科技有限公司 | Data protection circuit applied to abnormal power failure of memory |
| CN117713782A (en) * | 2024-02-04 | 2024-03-15 | 成都电科星拓科技有限公司 | Power-on reset circuit |
| CN117713782B (en) * | 2024-02-04 | 2024-04-26 | 成都电科星拓科技有限公司 | Power-on reset circuit |
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