CN111245370B

CN111245370B - CMOS bistable oscillator and implementation method thereof

Info

Publication number: CN111245370B
Application number: CN202010160463.XA
Authority: CN
Inventors: 方建平; 边疆; 张适
Original assignee: Tuoer Microelectronics Co ltd
Current assignee: Tuoer Microelectronics Co ltd
Priority date: 2020-03-10
Filing date: 2020-03-10
Publication date: 2024-05-24
Anticipated expiration: 2040-03-10
Also published as: CN111245370A

Abstract

The invention provides a CMOS bistable oscillator and an implementation method thereof, wherein the whole circuit adopts a CMOS process, and the circuit can generate stable switching frequency signals through the design of a comparator circuit and a logic signal processing circuit, and can set the frequency according to actual requirements. The oscillator adopts a CMOS process, has simple circuit design and small switching frequency error, has flexible and adjustable switching frequency, and can adjust the duty ratio of a switching waveform by changing the magnitudes of a current source IDC1 and a voltage VR so as to change the switching frequency.

Description

CMOS bistable oscillator and implementation method thereof

Technical Field

The invention relates to the technical field of circuits, in particular to an oscillator circuit.

Background

With the continuous development of analog circuits, the application of chips is becoming more and more widespread, and the chips are applied to oscillators in many places. In the conventional technology, the frequency stability of the RC oscillator is poor, and the range of use is limited. In view of the continuous improvement of the chip integration level, the reduction of chip finished products is realized by designing a special RC oscillator to generate an oscillator circuit which can be used in a chip circuit, most of the current chip internal oscillator circuits are complex in design, unstable in oscillation frequency, unfavorable for the integral optimization of the circuits, and also improve the design cost and have great influence on the performance of the chip.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a CMOS bistable oscillator and an implementation method thereof. The invention aims to provide a simple and practical CMOS bistable oscillator, the whole circuit adopts a CMOS process, and the circuit can generate stable switching frequency signals through the design of a comparator circuit and a logic signal processing circuit, and can set the frequency according to actual requirements.

The technical scheme adopted for solving the technical problems is as follows:

A CMOS bistable oscillator comprises P-channel enhancement MOS transistors PM1-PM10, N-channel enhancement MOS transistors NM1-NM16, capacitors C1-C3, a current source IDC1, inverters INV1-INV4, NOR gates NOR1-NOR4, a VCC input port, an EN_OSC input port, a VR voltage input port, a HOLD control input port and a CLK logic output port;

The source electrode of the P-channel enhancement type MOS tube PM1 is connected with the VCC input port and the source electrodes of the P-channel enhancement type MOS tubes PM2-PM10, the grid electrode is connected with the EN_OSC input port, the grid electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the P-channel enhancement type MOS tubes PM3 and PM7, and the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM1 is grounded, the grid electrode is connected with the EN_OSC input port and the source electrodes of the P-channel enhancement type MOS tubes PM1, PM3 and PM7, and the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8, NM13 and NM 16. The P-channel enhancement type MOS tube PM1 and the N-channel enhancement type MOS tube NM1 form an inverter circuit, and the voltage of the EN_OSC input port is transmitted to the grid electrode of the switching tube after being subjected to inversion treatment to control the on-off of the switching tube;

The source electrode of the P-channel enhancement type MOS tube PM2 is connected with the VCC input port, and the drain electrode of the grid electrode is connected with one end of a current source, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM4 is connected with the VCC input port, the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3, the grid electrodes of the P-channel enhancement type MOS tubes PM5-PM6 and PM8-PM10, and the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM2, the drain electrode of the N-channel enhancement type MOS tube NM3, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM 12; the source electrode of the P-channel enhancement type MOS tube PM5 is connected with the VCC input port, the drain electrode is connected with the source electrodes of the P-channel enhancement type MOS tubes PM11-PM12, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4, PM6 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM6 is connected with the VCC input port, the drain electrode of the P-channel enhancement type MOS tube PM7 is connected with the drain electrode of the N-channel enhancement type MOS tube NM9 and the input port of the inverter INV1, and the grid electrode of the N-channel enhancement type MOS tube NM9 is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM5 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM8 is connected with the VCC input port, the drain electrode is connected with the grid electrode of the P-channel enhancement type MOS tube PM14, the drain electrode of the N-channel enhancement type MOS tube NM10 and the upper polar plate of the capacitor C3, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM9-PM 10; the source electrode of the P-channel enhancement type MOS tube PM9 is connected with the VCC input port, the drain electrode is connected with the source electrodes of the P-channel enhancement type MOS tubes PM13-PM14, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6, PM8 and PM 10; the source electrode of the P-channel enhancement type MOS tube PM10 is connected with the VCC input port, the drain electrodes of the N-channel enhancement type MOS tubes NM15 and NM16 are connected with the input port of the inverter INV2, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM5 and PM8-PM 9. The P-channel enhancement type MOS transistors PM2, PM4-PM6 and PM8-PM10 jointly form a current mirror circuit, and the current mirror circuit plays a role in providing mirror currents for branches where the P-channel enhancement type MOS transistors PM2, PM4-PM6 and PM8-PM10 are located;

The source electrode of the P-channel enhancement type MOS tube PM11 is connected with the drain electrode of the P-channel enhancement type MOS tube PM5 and the source electrode of the P-channel enhancement type MOS tube PM12, the drain electrode is connected with the gate electrode of the N-channel enhancement type MOS tube NM5, the drain electrode of the N-channel enhancement type MOS tube NM6 and the gate electrode of the N-channel enhancement type MOS tube NM7, and the gate electrode is connected with the VR voltage input port and the gate electrode of the P-channel enhancement type MOS tube PM 13; the source electrode of the P-channel enhancement type MOS tube PM12 is connected with the drain electrode of the P-channel enhancement type MOS tube PM5 and the source electrode of the P-channel enhancement type MOS tube PM11, the drain electrode is connected with the drain electrodes of the N-channel enhancement type MOS tubes NM7-NM9, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM2, the drain electrode of the N-channel enhancement type MOS tube NM3 and the upper polar plate of the capacitor C2; the grid drain electrode of the N-channel enhancement type MOS tube NM5 is connected with the drain electrode of the P-channel enhancement type MOS tube PM11, the drain electrode of the N-channel enhancement type MOS tube NM6 and the grid electrode of the N-channel enhancement type MOS tube NM7, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM7 is connected with the drain electrode of the P-channel enhancement type MOS tube PM12, the drain electrode of the N-channel enhancement type MOS tube NM8 and the grid electrode of the N-channel enhancement type MOS tube NM9, the grid electrode is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM5, the drain electrode of the P-channel enhancement type MOS tube PM11 and the drain electrode of the N-channel enhancement type MOS tube NM6, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM9 is connected with the drain electrode of the P-channel enhancement type MOS tube PM6, the drain electrode of the P-channel enhancement type MOS tube PM7 and the input end of the inverter INV1, the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM12 and the drain electrodes of the N-channel enhancement type MOS tubes NM7 and NM8, and the source electrode is grounded. The P-channel enhancement type MOS tubes PM11 and PM12 and the N-channel enhancement type MOS tubes NM5, NM7 and NM9 form a comparator circuit together, the gate voltage VR of the P-channel enhancement type MOS tube PM11 is mainly compared with the gate voltage of the P-channel enhancement type MOS tube PM12, and then an output result is transmitted to the input end of the inverter INV 1;

The source electrode of the P-channel enhancement type MOS tube PM13 is connected with the drain electrode of the P-channel enhancement type MOS tube PM9 and the source electrode of the P-channel enhancement type MOS tube PM14, the drain electrode is connected with the gate electrode drain electrode of the N-channel enhancement type MOS tube NM12, the drain electrode of the N-channel enhancement type MOS tube NM13 and the gate electrode of the N-channel enhancement type MOS tube NM14, and the gate electrode is connected with the VR voltage input port and the gate electrode of the P-channel enhancement type MOS tube PM 11; the source electrode of the P-channel enhancement type MOS tube PM14 is connected with the drain electrode of the P-channel enhancement type MOS tube PM9 and the source electrode of the P-channel enhancement type MOS tube PM13, the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM14 and the grid electrode of the N-channel enhancement type MOS tube NM15, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the drain electrode of the N-channel enhancement type MOS tube NM10 and the upper polar plate of the capacitor C3; the grid drain electrode of the N-channel enhancement type MOS tube NM12 is connected with the drain electrode of the P-channel enhancement type MOS tube PM13, the drain electrode of the N-channel enhancement type MOS tube NM13 and the grid electrode of the N-channel enhancement type MOS tube NM14, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM14 is connected with the drain electrode of the P-channel enhancement type MOS tube PM14 and the grid electrode of the N-channel enhancement type MOS tube NM15, the grid electrode is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM12, the drain electrode of the P-channel enhancement type MOS tube PM13 and the drain electrode of the N-channel enhancement type MOS tube NM13, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM15 is connected with the drain electrode of the P-channel enhancement type MOS tube PM10, the drain electrode of the N-channel enhancement type MOS tube NM16 and the input end of the inverter INV2, the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM14, the drain electrode of the N-channel enhancement type MOS tube NM14, and the source electrode is grounded. The P-channel enhancement type MOS tubes PM13 and PM14 and the N-channel enhancement type MOS tubes NM12, NM14 and NM15 form a comparator circuit together, the gate voltage VR of the P-channel enhancement type MOS tube PM13 is mainly compared with the gate voltage of the P-channel enhancement type MOS tube PM14, and then an output result is transmitted to the input end of the inverter INV 2;

The source electrode of the P-channel enhancement type MOS tube PM3 is connected with the VCC input port, the drain electrode is connected with the gate electrode and the drain electrode of the P-channel enhancement type MOS tube PM2, one end of a current source and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM8-PM10, and the grid electrode is connected with the EN_OSC input port, the grid electrode of the N-channel enhancement type MOS tube NM1, the grid electrode of the P-channel enhancement type MOS tube PM1 and the grid electrode of the P-channel enhancement type MOS tube PM 7; the source electrode of the P-channel enhancement type MOS tube PM7 is connected with the VCC input port, the drain electrode of the P-channel enhancement type MOS tube PM6, the drain electrode of the N-channel enhancement type MOS tube NM9 and the input end of the inverter INV1, and the grid electrode of the N-channel enhancement type MOS tube NM1, the grid electrode of the P-channel enhancement type MOS tube PM1 and the grid electrode of the P-channel enhancement type MOS tube PM7 are connected with the EN_OSC input port; the source electrode of the N-channel enhancement type MOS tube NM2 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM3, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM12, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM6, NM8, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM6 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM11, the grid electrode drain electrode of the N-channel enhancement type MOS tube NM5 and the grid electrode of the N-channel enhancement type MOS tube NM7, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM8, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM8 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM12, the drain electrode of the N-channel enhancement type MOS tube NM7 and the grid electrode of the N-channel enhancement type MOS tube NM9, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM13 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM13, the grid electrode drain electrode of the N-channel enhancement type MOS tube NM12 and the grid electrode of the N-channel enhancement type MOS tube NM14, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM16 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM10, the drain electrode of the N-channel enhancement type MOS tube NM15 and the input end of the inverter INV2, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8 and NM 13. The P-channel enhancement type MOS transistors PM3 and PM7 and the N-channel enhancement type MOS transistors NM2, NM6, NM8, NM13 and NM16 all play the role of switching tubes in the circuit;

The drain electrode of the N-channel enhancement type MOS tube NM3 is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM2, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM12, the source electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM4, and the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM4 and the CLK output end; the drain electrode of the N-channel enhancement type MOS tube NM4 is connected with the source electrode of the N-channel enhancement type MOS tube NM3, the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM3 and the CLK output end, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM10 is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the upper polar plate of the capacitor C3 and the grid electrode of the P-channel enhancement type MOS tube PM14, the source electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM11, and the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM11 and the output end of the inverter INV 4; the drain electrode of the N-channel enhancement type MOS tube NM11 is connected with the source electrode of the N-channel enhancement type MOS tube NM10, the grid electrode of the N-channel enhancement type MOS tube NM10 is connected with the grid electrode of the inverter INV4, and the source electrode is grounded; the upper polar plate of the capacitor C1 is connected with the VR input port and the grids of the P-channel enhancement MOS tubes PM11 and PM13, and the lower polar plate is grounded; the upper polar plate of the capacitor C2 is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM3, the drain electrode of the N-channel enhancement type MOS tube NM2 and the grid electrode of the P-channel enhancement type MOS tube PM12, and the lower polar plate is grounded; the upper polar plate of the capacitor C3 is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the drain electrode of the N-channel enhancement type MOS tube NM10 and the grid electrode of the P-channel enhancement type MOS tube PM14, and the lower polar plate is grounded. The capacitor C1 mainly acts as a VR input port to provide voltage stabilization, and the capacitors C2 and C3 serve as charge and discharge capacitors in respective branches to provide voltages for the gates of the corresponding P-channel enhancement type MOS tube PM12 and the corresponding P-channel enhancement type MOS tube PM 14;

the input end of the inverter INV1 is connected with the drains of the P-channel enhancement MOS transistors PM6 and PM7 and the drain of the N-channel enhancement MOS transistor NM9, and the output end of the inverter INV1 is connected with one input end of the NOR gate NOR 1; the input end of the inverter INV2 is connected with the drain electrode of the P-channel enhancement type MOS tube PM10 and the drain electrodes of the N-channel enhancement type MOS tubes NM15 and NM16, and the output end of the inverter INV2 is connected with one input end of the NOR gate NOR 2; one input end of the NOR gate NOR1 is connected with the output end of the inverter INV1, the other input end of the NOR gate NOR1 is connected with the output end of the NOR gate NOR2 and the input end of the NOR gate NOR4, and the output end of the NOR gate NOR1 is connected with one input end of the NOR gate NOR2 and the other input end of the NOR gate NOR 3; one input end of the NOR gate NOR2 is connected with the output end of the inverter INV2, the other input end of the NOR gate NOR2 is connected with the output end of the NOR gate NOR1 and the input end of the NOR gate NOR3, and the output end of the NOR gate NOR2 is connected with one input end of the NOR gate NOR4 and the other input end of the NOR gate NOR 1; one input end of the NOR gate NOR3 is connected with the HOLD input port, the other input port is connected with the output end of the NOR gate NOR1 and one input end of the NOR gate NOR2, and the output end is connected with the input end of the inverter INV 3; one input end of the NOR gate NOR4 is connected with the output end of the NOR gate NOR2 and the other input end of the NOR gate NOR1, and the output end of the NOR gate NOR4 is connected with the input end of the inverter INV 4; the input end of the inverter INV3 is connected with the output end of the NOR gate NOR3, and the output end of the inverter INV is connected with the CLK output port and the grid electrodes of the N-channel enhancement MOS transistors NM3 and NM 4; the input end of the inverter INV4 is connected with the output end of the NOR gate NOR4, and the output end of the inverter INV is connected with the grid electrodes of the N-channel enhancement type MOS transistors NM10 and NM 11. The inverters INV1 to INV4 and the NOR gates NOR1 to NOR4 together form an oscillator circuit logic signal processing circuit which converts an analog signal generated by the operational amplifier circuit into a digital signal.

The invention also provides a realization method related to the CMOS bistable oscillator, which comprises the following detailed steps:

When the VCC input end is powered by a power supply and the EN_OSC input end provides a high level, the current source IDC1 provides a current, the VR input end provides a stable power supply voltage VR, a constant current source formed by a P-channel enhancement type MOS tube PM4 branch mirror image P-channel enhancement type MOS tube PM2 branch is used for charging a capacitor C2, and when the voltage of the upper polar plate of the capacitor C2 is higher than the VR voltage, the high level is transmitted to the input end of the inverter INV1 through the output end of a comparator circuit formed by P-channel enhancement type MOS tubes PM11 and PM12 and N-channel enhancement type MOS tubes NM5 and NM7 and NM 9; when the voltage of the upper polar plate of the capacitor C3 is higher than VR voltage, the high level is transmitted to the input end of the inverter INV2 through the output end of the comparator circuit formed by the P-channel enhancement type MOS tubes PM13 and PM14 and the N-channel enhancement type MOS tubes NM12, NM14 and NM 15; the analog signals transmitted by the inverters INV1 and INV2 are output to logic signals with high and low levels after being subjected to edge starting through a latch formed by the NOR gates NOR1 and NOR2, then the signals at the output end of the NOR gate NOR1 are subjected to NOR processing through the NOR gate NOR3 and HOLD input signals, the on-off of the N-channel enhancement type MOS tubes NM3 and NM4 are controlled through the inverter INV3, so that when the voltage of the upper polar plate of the C2 is larger than VR, the MOS tubes NM3 and NM4 are started, the upper polar plate of the capacitor C2 is pulled down, at the moment, the capacitor C2 begins to discharge, and when the voltage of the upper polar plate of the capacitor C2 is lower than VR, the low level is transmitted to the input end of the inverter 1 through the output end of a comparator circuit formed by the P-channel enhancement type MOS tubes PM11, PM12 and N-channel enhancement type MOS tubes NM5, NM7 and NM 9; after the output end signal of the NOR gate NOR2 is NOR-processed with the ground through the NOR gate NOR4, the on-off of the N-channel enhancement type MOS transistors NM10 and NM11 is controlled through the inverter INV4, so that when the upper plate voltage of the C3 is larger than the VR voltage, the MOS transistors NM10 and NM11 are turned on, the upper plate of the capacitor C3 is pulled down to the ground, at this time, the capacitor C3 starts to discharge, and when the upper plate voltage of the capacitor C3 is lower than the VR voltage, the low level is transferred to the input end of the inverter INV2 through the output end of the comparator circuit formed by the P-channel enhancement type MOS transistors PM13, PM14 and the N-channel enhancement type MOS transistors NM12, NM14 and NM 15. Therefore, after the capacitors C2 and C3 are charged and discharged continuously and the output signals of the two comparators are processed by the latch, the CLK oscillation switching waveform signal is obtained.

The invention has the beneficial effects that:

1. The oscillator adopts a CMOS process, the circuit design is simple, and the switching frequency error is small.

2. The switching frequency of the oscillator is flexible and adjustable, and the duty ratio of the switching waveform can be adjusted by changing the magnitudes of the current source IDC1 and the voltage VR, so that the switching frequency is changed.

Drawings

FIG. 1 is a schematic diagram of a CMOS bistable oscillator according to the present invention.

Detailed Description

The invention will be further described with reference to the drawings and examples.

The CMOS bistable oscillator, as shown in FIG. 1, includes P-channel enhancement MOS transistors PM1-PM10, N-channel enhancement MOS transistors NM1-NM16, capacitors C1-C3, current sources IDC1, inverters INV1-INV4, NOR gates NOR1-NOR4, and VCC input port, EN_OSC input port, VR voltage input port, HOLD control input port, and CLK logic output port.

The source electrode of the P-channel enhancement type MOS tube PM1 is connected with the VCC input port and the source electrodes of the P-channel enhancement type MOS tubes PM2-PM10, the grid electrode is connected with the EN_OSC input port, the grid electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the P-channel enhancement type MOS tubes PM3 and PM7, and the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM1 is grounded, the grid electrode is connected with the EN_OSC input port and the source electrodes of the P-channel enhancement type MOS tubes PM1, PM3 and PM7, and the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8, NM13 and NM 16. The P-channel enhancement type MOS tube PM1 and the N-channel enhancement type MOS tube NM1 form an inverter circuit, and the voltage of the EN_OSC input port is transmitted to the grid electrode of the switching tube after being subjected to inversion treatment, so that the on-off control of the switching tube is performed.

The source electrode of the P-channel enhancement type MOS tube PM2 is connected with the VCC input port, and the drain electrode of the grid electrode is connected with one end of a current source, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM4 is connected with the VCC input port, the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3, the grid electrodes of the P-channel enhancement type MOS tubes PM5-PM6 and PM8-PM10, and the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM2, the drain electrode of the N-channel enhancement type MOS tube NM3, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM 12; the source electrode of the P-channel enhancement type MOS tube PM5 is connected with the VCC input port, the drain electrode is connected with the source electrodes of the P-channel enhancement type MOS tubes PM11-PM12, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4, PM6 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM6 is connected with the VCC input port, the drain electrode of the P-channel enhancement type MOS tube PM7 is connected with the drain electrode of the N-channel enhancement type MOS tube NM9 and the input port of the inverter INV1, and the grid electrode of the N-channel enhancement type MOS tube NM9 is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM5 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM8 is connected with the VCC input port, the drain electrode is connected with the grid electrode of the P-channel enhancement type MOS tube PM14, the drain electrode of the N-channel enhancement type MOS tube NM10 and the upper polar plate of the capacitor C3, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM9-PM 10; the source electrode of the P-channel enhancement type MOS tube PM9 is connected with the VCC input port, the drain electrode is connected with the source electrodes of the P-channel enhancement type MOS tubes PM13-PM14, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6, PM8 and PM 10; the source electrode of the P-channel enhancement type MOS tube PM10 is connected with the VCC input port, the drain electrodes of the N-channel enhancement type MOS tubes NM15 and NM16 are connected with the input port of the inverter INV2, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM5 and PM8-PM 9. The P-channel enhancement type MOS transistors PM2, PM4-PM6 and PM8-PM10 jointly form a current mirror circuit, and the current mirror circuit plays a role in providing mirror currents for branches where the P-channel enhancement type MOS transistors PM2, PM4-PM6 and PM8-PM10 are located.

The source electrode of the P-channel enhancement type MOS tube PM11 is connected with the drain electrode of the P-channel enhancement type MOS tube PM5 and the source electrode of the P-channel enhancement type MOS tube PM12, the drain electrode is connected with the gate electrode of the N-channel enhancement type MOS tube NM5, the drain electrode of the N-channel enhancement type MOS tube NM6 and the gate electrode of the N-channel enhancement type MOS tube NM7, and the gate electrode is connected with the VR voltage input port and the gate electrode of the P-channel enhancement type MOS tube PM 13; the source electrode of the P-channel enhancement type MOS tube PM12 is connected with the drain electrode of the P-channel enhancement type MOS tube PM5 and the source electrode of the P-channel enhancement type MOS tube PM11, the drain electrode is connected with the drain electrodes of the N-channel enhancement type MOS tubes NM7-NM9, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM2, the drain electrode of the N-channel enhancement type MOS tube NM3 and the upper polar plate of the capacitor C2; the grid drain electrode of the N-channel enhancement type MOS tube NM5 is connected with the drain electrode of the P-channel enhancement type MOS tube PM11, the drain electrode of the N-channel enhancement type MOS tube NM6 and the grid electrode of the N-channel enhancement type MOS tube NM7, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM7 is connected with the drain electrode of the P-channel enhancement type MOS tube PM12, the drain electrode of the N-channel enhancement type MOS tube NM8 and the grid electrode of the N-channel enhancement type MOS tube NM9, the grid electrode is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM5, the drain electrode of the P-channel enhancement type MOS tube PM11 and the drain electrode of the N-channel enhancement type MOS tube NM6, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM9 is connected with the drain electrode of the P-channel enhancement type MOS tube PM6, the drain electrode of the P-channel enhancement type MOS tube PM7 and the input end of the inverter INV1, the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM12 and the drain electrodes of the N-channel enhancement type MOS tubes NM7 and NM8, and the source electrode is grounded. The P-channel enhancement type MOS transistors PM11, PM12 and the N-channel enhancement type MOS transistors NM5, NM7, NM9 together form a comparator circuit, and the gate voltage VR of the P-channel enhancement type MOS transistor PM11 is mainly compared with the gate voltage of the P-channel enhancement type MOS transistor PM12, and then the output result is transmitted to the input end of the inverter INV 1.

The source electrode of the P-channel enhancement type MOS tube PM13 is connected with the drain electrode of the P-channel enhancement type MOS tube PM9 and the source electrode of the P-channel enhancement type MOS tube PM14, the drain electrode is connected with the gate electrode drain electrode of the N-channel enhancement type MOS tube NM12, the drain electrode of the N-channel enhancement type MOS tube NM13 and the gate electrode of the N-channel enhancement type MOS tube NM14, and the gate electrode is connected with the VR voltage input port and the gate electrode of the P-channel enhancement type MOS tube PM 11; the source electrode of the P-channel enhancement type MOS tube PM14 is connected with the drain electrode of the P-channel enhancement type MOS tube PM9 and the source electrode of the P-channel enhancement type MOS tube PM13, the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM14 and the grid electrode of the N-channel enhancement type MOS tube NM15, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the drain electrode of the N-channel enhancement type MOS tube NM10 and the upper polar plate of the capacitor C3; the grid drain electrode of the N-channel enhancement type MOS tube NM12 is connected with the drain electrode of the P-channel enhancement type MOS tube PM13, the drain electrode of the N-channel enhancement type MOS tube NM13 and the grid electrode of the N-channel enhancement type MOS tube NM14, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM14 is connected with the drain electrode of the P-channel enhancement type MOS tube PM14 and the grid electrode of the N-channel enhancement type MOS tube NM15, the grid electrode is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM12, the drain electrode of the P-channel enhancement type MOS tube PM13 and the drain electrode of the N-channel enhancement type MOS tube NM13, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM15 is connected with the drain electrode of the P-channel enhancement type MOS tube PM10, the drain electrode of the N-channel enhancement type MOS tube NM16 and the input end of the inverter INV2, the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM14, the drain electrode of the N-channel enhancement type MOS tube NM14, and the source electrode is grounded. The P-channel enhancement type MOS transistors PM13 and PM14 and the N-channel enhancement type MOS transistors NM12, NM14 and NM15 together form a comparator circuit, and the gate voltage VR of the P-channel enhancement type MOS transistor PM13 is mainly compared with the gate voltage of the P-channel enhancement type MOS transistor PM14, and then the output result is transmitted to the input end of the inverter INV 2.

The source electrode of the P-channel enhancement type MOS tube PM3 is connected with the VCC input port, the drain electrode is connected with the gate electrode and the drain electrode of the P-channel enhancement type MOS tube PM2, one end of a current source and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM8-PM10, and the grid electrode is connected with the EN_OSC input port, the grid electrode of the N-channel enhancement type MOS tube NM1, the grid electrode of the P-channel enhancement type MOS tube PM1 and the grid electrode of the P-channel enhancement type MOS tube PM 7; the source electrode of the P-channel enhancement type MOS tube PM7 is connected with the VCC input port, the drain electrode of the P-channel enhancement type MOS tube PM6, the drain electrode of the N-channel enhancement type MOS tube NM9 and the input end of the inverter INV1, and the grid electrode of the N-channel enhancement type MOS tube NM1, the grid electrode of the P-channel enhancement type MOS tube PM1 and the grid electrode of the P-channel enhancement type MOS tube PM7 are connected with the EN_OSC input port; the source electrode of the N-channel enhancement type MOS tube NM2 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM3, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM12, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM6, NM8, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM6 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM11, the grid electrode drain electrode of the N-channel enhancement type MOS tube NM5 and the grid electrode of the N-channel enhancement type MOS tube NM7, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM8, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM8 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM12, the drain electrode of the N-channel enhancement type MOS tube NM7 and the grid electrode of the N-channel enhancement type MOS tube NM9, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM13 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM13, the grid electrode drain electrode of the N-channel enhancement type MOS tube NM12 and the grid electrode of the N-channel enhancement type MOS tube NM14, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM16 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM10, the drain electrode of the N-channel enhancement type MOS tube NM15 and the input end of the inverter INV2, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8 and NM 13. The P-channel enhancement type MOS transistors PM3 and PM7 and the N-channel enhancement type MOS transistors NM2, NM6, NM8, NM13 and NM16 all play a role of switching tubes in a circuit.

The drain electrode of the N-channel enhancement type MOS tube NM3 is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM2, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM12, the source electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM4, and the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM4 and the CLK output end; the drain electrode of the N-channel enhancement type MOS tube NM4 is connected with the source electrode of the N-channel enhancement type MOS tube NM3, the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM3 and the CLK output end, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM10 is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the upper polar plate of the capacitor C3 and the grid electrode of the P-channel enhancement type MOS tube PM14, the source electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM11, and the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM11 and the output end of the inverter INV 4; the drain electrode of the N-channel enhancement type MOS tube NM11 is connected with the source electrode of the N-channel enhancement type MOS tube NM10, the grid electrode of the N-channel enhancement type MOS tube NM10 is connected with the grid electrode of the inverter INV4, and the source electrode is grounded; the upper polar plate of the capacitor C1 is connected with the VR input port and the grids of the P-channel enhancement MOS tubes PM11 and PM13, and the lower polar plate is grounded; the upper polar plate of the capacitor C2 is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM3, the drain electrode of the N-channel enhancement type MOS tube NM2 and the grid electrode of the P-channel enhancement type MOS tube PM12, and the lower polar plate is grounded; the upper polar plate of the capacitor C3 is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the drain electrode of the N-channel enhancement type MOS tube NM10 and the grid electrode of the P-channel enhancement type MOS tube PM14, and the lower polar plate is grounded. The capacitor C1 mainly acts as a VR input port to provide voltage stabilization, and the capacitors C2 and C3 serve as charge and discharge capacitors in respective branches to provide voltages for the gates of the corresponding P-channel enhancement MOS transistor PM12 and P-channel enhancement MOS transistor PM 14.

The implementation method of the CMOS bistable oscillator comprises the following steps:

In summary, the invention provides a simple and practical CMOS bistable oscillator, which can effectively generate stable oscillation waveforms and ensure the safety and reliability of a circuit. Compared with the prior oscillator generation circuit, the method has the advantages that the whole circuit design is simple, the generated switching waveform is stable, the internal power consumption of the circuit is small, and good switching signal waveforms can be provided for other circuits.

Claims

1. A CMOS bistable oscillator, characterized by:

The CMOS bistable oscillator comprises P-channel enhancement type MOS transistors PM1-PM10, N-channel enhancement type MOS transistors NM1-NM16, capacitors C1-C3, a current source IDC1, inverters INV1-INV4, NOR gates NOR1-NOR4, a VCC input port, an EN_OSC input port, a VR voltage input port, a HOLD control input port and a CLK logic output port;

The source electrode of the P-channel enhancement type MOS tube PM1 is connected with the VCC input port and the source electrodes of the P-channel enhancement type MOS tubes PM2-PM10, the grid electrode is connected with the EN_OSC input port, the grid electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the P-channel enhancement type MOS tubes PM3 and PM7, and the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM1 is grounded, the grid electrode is connected with an EN_OSC input port and the source electrodes of the P-channel enhancement type MOS tubes PM1, PM3 and PM7, and the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8, NM13 and NM 16; the P-channel enhancement type MOS tube PM1 and the N-channel enhancement type MOS tube NM1 form an inverter circuit, and the voltage of the EN_OSC input port is transmitted to the grid electrode of the switching tube after being subjected to inversion treatment to control the on-off of the switching tube;

The source electrode of the P-channel enhancement type MOS tube PM2 is connected with the VCC input port, and the drain electrode of the grid electrode is connected with one end of a current source, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM4 is connected with the VCC input port, the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3, the grid electrodes of the P-channel enhancement type MOS tubes PM5-PM6 and PM8-PM10, and the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM2, the drain electrode of the N-channel enhancement type MOS tube NM3, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM 12; the source electrode of the P-channel enhancement type MOS tube PM5 is connected with the VCC input port, the drain electrode is connected with the source electrodes of the P-channel enhancement type MOS tubes PM11-PM12, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4, PM6 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM6 is connected with the VCC input port, the drain electrode of the P-channel enhancement type MOS tube PM7 is connected with the drain electrode of the N-channel enhancement type MOS tube NM9 and the input port of the inverter INV1, and the grid electrode of the N-channel enhancement type MOS tube NM9 is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM5 and PM8-PM 10; the source electrode of the P-channel enhancement type MOS tube PM8 is connected with the VCC input port, the drain electrode is connected with the grid electrode of the P-channel enhancement type MOS tube PM14, the drain electrode of the N-channel enhancement type MOS tube NM10 and the upper polar plate of the capacitor C3, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM9-PM 10; the source electrode of the P-channel enhancement type MOS tube PM9 is connected with the VCC input port, the drain electrode is connected with the source electrodes of the P-channel enhancement type MOS tubes PM13-PM14, and the grid electrode is connected with one end of a current source, the grid electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6, PM8 and PM 10; the source electrode of the P-channel enhancement type MOS tube PM10 is connected with a VCC input port, the drain electrodes of the N-channel enhancement type MOS tubes NM15 and NM16 are connected with the drain electrodes of the inverter INV2, and the gate electrode is connected with one end of a current source, the gate electrode drain electrode of the P-channel enhancement type MOS tube PM2, the drain electrode of the P-channel enhancement type MOS tube PM3 and the gate electrodes of the P-channel enhancement type MOS tubes PM4-PM5 and PM8-PM 9; the P-channel enhancement type MOS transistors PM2, PM4-PM6 and PM8-PM10 jointly form a current mirror circuit, and the current mirror circuit plays a role in providing mirror currents for branches where the P-channel enhancement type MOS transistors PM2, PM4-PM6 and PM8-PM10 are located;

The source electrode of the P-channel enhancement type MOS tube PM11 is connected with the drain electrode of the P-channel enhancement type MOS tube PM5 and the source electrode of the P-channel enhancement type MOS tube PM12, the drain electrode is connected with the gate electrode of the N-channel enhancement type MOS tube NM5, the drain electrode of the N-channel enhancement type MOS tube NM6 and the gate electrode of the N-channel enhancement type MOS tube NM7, and the gate electrode is connected with the VR voltage input port and the gate electrode of the P-channel enhancement type MOS tube PM 13; the source electrode of the P-channel enhancement type MOS tube PM12 is connected with the drain electrode of the P-channel enhancement type MOS tube PM5 and the source electrode of the P-channel enhancement type MOS tube PM11, the drain electrode is connected with the drain electrodes of the N-channel enhancement type MOS tubes NM7-NM9, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM2, the drain electrode of the N-channel enhancement type MOS tube NM3 and the upper polar plate of the capacitor C2; the grid drain electrode of the N-channel enhancement type MOS tube NM5 is connected with the drain electrode of the P-channel enhancement type MOS tube PM11, the drain electrode of the N-channel enhancement type MOS tube NM6 and the grid electrode of the N-channel enhancement type MOS tube NM7, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM7 is connected with the drain electrode of the P-channel enhancement type MOS tube PM12, the drain electrode of the N-channel enhancement type MOS tube NM8 and the grid electrode of the N-channel enhancement type MOS tube NM9, the grid electrode is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM5, the drain electrode of the P-channel enhancement type MOS tube PM11 and the drain electrode of the N-channel enhancement type MOS tube NM6, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM9 is connected with the drain electrode of the P-channel enhancement type MOS tube PM6, the drain electrode of the P-channel enhancement type MOS tube PM7 and the input end of the inverter INV1, the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM12 and the drain electrodes of the N-channel enhancement type MOS tubes NM7 and NM8, and the source electrode is grounded; the P-channel enhancement type MOS tubes PM11 and PM12 and the N-channel enhancement type MOS tubes NM5, NM7 and NM9 form a comparator circuit together, the gate voltage VR of the P-channel enhancement type MOS tube PM11 is mainly compared with the gate voltage of the P-channel enhancement type MOS tube PM12, and then an output result is transmitted to the input end of the inverter INV 1;

The source electrode of the P-channel enhancement type MOS tube PM13 is connected with the drain electrode of the P-channel enhancement type MOS tube PM9 and the source electrode of the P-channel enhancement type MOS tube PM14, the drain electrode is connected with the gate electrode drain electrode of the N-channel enhancement type MOS tube NM12, the drain electrode of the N-channel enhancement type MOS tube NM13 and the gate electrode of the N-channel enhancement type MOS tube NM14, and the gate electrode is connected with the VR voltage input port and the gate electrode of the P-channel enhancement type MOS tube PM 11; the source electrode of the P-channel enhancement type MOS tube PM14 is connected with the drain electrode of the P-channel enhancement type MOS tube PM9 and the source electrode of the P-channel enhancement type MOS tube PM13, the drain electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM14 and the grid electrode of the N-channel enhancement type MOS tube NM15, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the drain electrode of the N-channel enhancement type MOS tube NM10 and the upper polar plate of the capacitor C3; the grid drain electrode of the N-channel enhancement type MOS tube NM12 is connected with the drain electrode of the P-channel enhancement type MOS tube PM13, the drain electrode of the N-channel enhancement type MOS tube NM13 and the grid electrode of the N-channel enhancement type MOS tube NM14, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM14 is connected with the drain electrode of the P-channel enhancement type MOS tube PM14 and the grid electrode of the N-channel enhancement type MOS tube NM15, the grid electrode is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM12, the drain electrode of the P-channel enhancement type MOS tube PM13 and the drain electrode of the N-channel enhancement type MOS tube NM13, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM15 is connected with the drain electrode of the P-channel enhancement type MOS tube PM10, the drain electrode of the N-channel enhancement type MOS tube NM16 and the input end of the inverter INV2, the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM14, the drain electrode of the N-channel enhancement type MOS tube NM14, and the source electrode is grounded; the P-channel enhancement type MOS tubes PM13 and PM14 and the N-channel enhancement type MOS tubes NM12, NM14 and NM15 form a comparator circuit together, the gate voltage VR of the P-channel enhancement type MOS tube PM13 is mainly compared with the gate voltage of the P-channel enhancement type MOS tube PM14, and then an output result is transmitted to the input end of the inverter INV 2;

The source electrode of the P-channel enhancement type MOS tube PM3 is connected with the VCC input port, the drain electrode is connected with the gate electrode and the drain electrode of the P-channel enhancement type MOS tube PM2, one end of a current source and the grid electrodes of the P-channel enhancement type MOS tubes PM4-PM6 and PM8-PM10, and the grid electrode is connected with the EN_OSC input port, the grid electrode of the N-channel enhancement type MOS tube NM1, the grid electrode of the P-channel enhancement type MOS tube PM1 and the grid electrode of the P-channel enhancement type MOS tube PM 7; the source electrode of the P-channel enhancement type MOS tube PM7 is connected with the VCC input port, the drain electrode of the P-channel enhancement type MOS tube PM6, the drain electrode of the N-channel enhancement type MOS tube NM9 and the input end of the inverter INV1, and the grid electrode of the N-channel enhancement type MOS tube NM1, the grid electrode of the P-channel enhancement type MOS tube PM1 and the grid electrode of the P-channel enhancement type MOS tube PM7 are connected with the EN_OSC input port; the source electrode of the N-channel enhancement type MOS tube NM2 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM3, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM12, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM6, NM8, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM6 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM11, the grid electrode drain electrode of the N-channel enhancement type MOS tube NM5 and the grid electrode of the N-channel enhancement type MOS tube NM7, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM8, NM13 and NM 16;

The source electrode of the N-channel enhancement type MOS tube NM8 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM12, the drain electrode of the N-channel enhancement type MOS tube NM7 and the grid electrode of the N-channel enhancement type MOS tube NM9, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM13 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM13 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM13, the grid electrode drain electrode of the N-channel enhancement type MOS tube NM12 and the grid electrode of the N-channel enhancement type MOS tube NM14, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8 and NM 16; the source electrode of the N-channel enhancement type MOS tube NM16 is grounded, the drain electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM10, the drain electrode of the N-channel enhancement type MOS tube NM15 and the input end of the inverter INV2, and the grid electrode is connected with the drain electrode of the P-channel enhancement type MOS tube PM1, the drain electrode of the N-channel enhancement type MOS tube NM1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM6, NM8 and NM 13; the P-channel enhancement type MOS transistors PM3 and PM7 and the N-channel enhancement type MOS transistors NM2, NM6, NM8, NM13 and NM16 all play the role of switching tubes in the circuit;

The drain electrode of the N-channel enhancement type MOS tube NM3 is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM2, the upper polar plate of the capacitor C2 and the grid electrode of the P-channel enhancement type MOS tube PM12, the source electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM4, and the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM4 and the CLK output end; the drain electrode of the N-channel enhancement type MOS tube NM4 is connected with the source electrode of the N-channel enhancement type MOS tube NM3, the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM3 and the CLK output end, and the source electrode is grounded; the drain electrode of the N-channel enhancement type MOS tube NM10 is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the upper polar plate of the capacitor C3 and the grid electrode of the P-channel enhancement type MOS tube PM14, the source electrode is connected with the drain electrode of the N-channel enhancement type MOS tube NM11, and the grid electrode is connected with the grid electrode of the N-channel enhancement type MOS tube NM11 and the output end of the inverter INV 4; the drain electrode of the N-channel enhancement type MOS tube NM11 is connected with the source electrode of the N-channel enhancement type MOS tube NM10, the grid electrode of the N-channel enhancement type MOS tube NM10 is connected with the grid electrode of the inverter INV4, and the source electrode is grounded; the upper polar plate of the capacitor C1 is connected with the VR input port and the grids of the P-channel enhancement MOS tubes PM11 and PM13, and the lower polar plate is grounded; the upper polar plate of the capacitor C2 is connected with the drain electrode of the P-channel enhancement type MOS tube PM4, the drain electrode of the N-channel enhancement type MOS tube NM3, the drain electrode of the N-channel enhancement type MOS tube NM2 and the grid electrode of the P-channel enhancement type MOS tube PM12, and the lower polar plate is grounded; the upper polar plate of the capacitor C3 is connected with the drain electrode of the P-channel enhancement type MOS tube PM8, the drain electrode of the N-channel enhancement type MOS tube NM10 and the grid electrode of the P-channel enhancement type MOS tube PM14, and the lower polar plate is grounded; the capacitor C1 mainly acts as a VR input port to provide voltage stabilization, and the capacitors C2 and C3 serve as charge and discharge capacitors in respective branches to provide voltages for the gates of the corresponding P-channel enhancement type MOS tube PM12 and the corresponding P-channel enhancement type MOS tube PM 14;

The input end of the inverter INV1 is connected with the drains of the P-channel enhancement MOS transistors PM6 and PM7 and the drain of the N-channel enhancement MOS transistor NM9, and the output end of the inverter INV1 is connected with one input end of the NOR gate NOR 1; the input end of the inverter INV2 is connected with the drain electrode of the P-channel enhancement type MOS tube PM10 and the drain electrodes of the N-channel enhancement type MOS tubes NM15 and NM16, and the output end of the inverter INV2 is connected with one input end of the NOR gate NOR 2; one input end of the NOR gate NOR1 is connected with the output end of the inverter INV1, the other input end of the NOR gate NOR1 is connected with the output end of the NOR gate NOR2 and the input end of the NOR gate NOR4, and the output end of the NOR gate NOR1 is connected with one input end of the NOR gate NOR2 and the other input end of the NOR gate NOR 3; one input end of the NOR gate NOR2 is connected with the output end of the inverter INV2, the other input end of the NOR gate NOR2 is connected with the output end of the NOR gate NOR1 and the input end of the NOR gate NOR3, and the output end of the NOR gate NOR2 is connected with one input end of the NOR gate NOR4 and the other input end of the NOR gate NOR 1; one input end of the NOR gate NOR3 is connected with the HOLD input port, the other input port is connected with the output end of the NOR gate NOR1 and one input end of the NOR gate NOR2, and the output end is connected with the input end of the inverter INV 3; one input end of the NOR gate NOR4 is connected with the output end of the NOR gate NOR2 and the other input end of the NOR gate NOR1, and the output end of the NOR gate NOR4 is connected with the input end of the inverter INV 4; the input end of the inverter INV3 is connected with the output end of the NOR gate NOR3, and the output end of the inverter INV is connected with the CLK output port and the grid electrodes of the N-channel enhancement MOS transistors NM3 and NM 4; the input end of the inverter INV4 is connected with the output end of the NOR gate NOR4, and the output end of the inverter INV is connected with the grids of the N-channel enhancement MOS transistors NM10 and NM 11; the inverters INV1 to INV4 and the NOR gates NOR1 to NOR4 together form an oscillator circuit logic signal processing circuit which converts an analog signal generated by the operational amplifier circuit into a digital signal.

2. A method of implementing a CMOS bistable oscillator according to claim 1, comprising the steps of:

When the VCC input end is powered by a power supply and the EN_OSC input end provides a high level, the current source IDC1 provides a current, the VR input end provides a stable power supply voltage VR, a constant current source formed by a P-channel enhancement type MOS tube PM4 branch mirror image P-channel enhancement type MOS tube PM2 branch is used for charging a capacitor C2, and when the voltage of the upper polar plate of the capacitor C2 is higher than the VR voltage, the high level is transmitted to the input end of the inverter INV1 through the output end of a comparator circuit formed by P-channel enhancement type MOS tubes PM11 and PM12 and N-channel enhancement type MOS tubes NM5 and NM7 and NM 9; when the voltage of the upper polar plate of the capacitor C3 is higher than VR voltage, the high level is transmitted to the input end of the inverter INV2 through the output end of the comparator circuit formed by the P-channel enhancement type MOS tubes PM13 and PM14 and the N-channel enhancement type MOS tubes NM12, NM14 and NM 15; the analog signals transmitted by the inverters INV1 and INV2 are output to logic signals with high and low levels after being subjected to edge starting through a latch formed by the NOR gates NOR1 and NOR2, then the signals at the output end of the NOR gate NOR1 are subjected to NOR processing through the NOR gate NOR3 and HOLD input signals, the on-off of the N-channel enhancement type MOS tubes NM3 and NM4 are controlled through the inverter INV3, so that when the voltage of the upper polar plate of the C2 is larger than VR, the MOS tubes NM3 and NM4 are started, the upper polar plate of the capacitor C2 is pulled down, at the moment, the capacitor C2 begins to discharge, and when the voltage of the upper polar plate of the capacitor C2 is lower than VR, the low level is transmitted to the input end of the inverter 1 through the output end of a comparator circuit formed by the P-channel enhancement type MOS tubes PM11, PM12 and N-channel enhancement type MOS tubes NM5, NM7 and NM 9; after the output end signal of the NOR gate NOR2 is NOR processed with the ground through the NOR gate NOR4, the on-off of the N-channel enhancement type MOS transistors NM10 and NM11 is controlled through the inverter INV4, so that when the upper plate voltage of the C3 is larger than the VR voltage, the MOS transistors NM10 and NM11 are turned on, the upper plate of the capacitor C3 is pulled down to the ground, at the moment, the capacitor C3 starts to discharge, and when the upper plate voltage of the capacitor C3 is lower than the VR voltage, the low level is transmitted to the input end of the inverter INV2 through the output end of the comparator circuit formed by the P-channel enhancement type MOS transistors PM13, PM14 and the N-channel enhancement type MOS transistors NM12, NM14 and NM 15; therefore, after the capacitors C2 and C3 are charged and discharged continuously and the output signals of the two comparators are processed by the latch, the CLK oscillation switching waveform signal is obtained.