CN212435662U - Low-temperature drift low-power consumption on-chip clock circuit - Google Patents
Low-temperature drift low-power consumption on-chip clock circuit Download PDFInfo
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- CN212435662U CN212435662U CN202020806087.2U CN202020806087U CN212435662U CN 212435662 U CN212435662 U CN 212435662U CN 202020806087 U CN202020806087 U CN 202020806087U CN 212435662 U CN212435662 U CN 212435662U
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Abstract
The utility model relates to a low temperature floats on-chip clock circuit of low-power consumption, a serial communication port, include: the device comprises a charge-discharge control circuit module, a comparator A1, a hysteresis comparator A2, an output control circuit module and a clock turn-off control circuit module; the charge-discharge control circuit module is respectively connected with the negative input end of the comparator A1, the clock turn-off control circuit module and the positive input end of the hysteresis comparator A2; the output control circuit module is respectively connected with the positive input end of the comparator A1, the clock turn-off control circuit module and the output end of the hysteresis comparator A2; the output end of the comparator A1 is respectively connected with the negative input end of the hysteresis comparator A2 and the capacitor C; the comparator A1 and the hysteresis comparator A2 are respectively connected with a first tail current source and a second tail current source. The utility model has the advantages that the output period is not affected by the voltage and the temperature of the power supply, thereby realizing the high precision and the low temperature drift of the oscillation signal; the introduced clock turn-off circuit can perform turn-off control according to system requirements, and power consumption is effectively reduced.
Description
Technical Field
The utility model belongs to integrated circuit's on-chip clock field, concretely relates to low temperature floats on-chip clock circuit of low-power consumption.
Background
With the development of semiconductor technology and electronic technology, digital-analog hybrid electronic systems are increasingly integrated, low in power consumption and high in stability. The performance of a clock circuit, which is an important component of an electronic system, directly affects the performance of the system. Therefore, the realization of the performances of the clock circuit such as low power consumption, low temperature drift, high precision and the like has important practical significance.
The existing oscillator circuits are mainly ring oscillator circuits and relaxation oscillators based on comparators for reference comparison. The ring oscillator is formed by connecting odd number of phase inverters which are connected end to end, and an RC circuit is added for reducing the frequency, wherein the clock period is Tosc approximately equal to 2.2 RC; the period of the implementation mode mainly depends on the RC size, the area is enlarged when the frequency is small, integration is not facilitated, meanwhile, the loop feedback quantity is single, the loop feedback quantity is easily influenced by power noise, and the frequency deviation is large in a wide voltage range. The relaxation oscillator for reference comparison by the comparator has a stable contrast and a stable output clock waveform, but the bandgap reference voltage source has a large circuit scale because of the transistor.
Disclosure of Invention
In view of this, an object of the present invention is to provide an on-chip clock circuit with low power consumption and low temperature drift, which has an output period not affected by the power supply voltage and temperature, and realizes high accuracy and low temperature drift of the oscillation signal.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a low temperature drift low power on-chip clock circuit comprising: the device comprises a charge-discharge control circuit module, a comparator A1, a hysteresis comparator A2, an output control circuit module and a clock turn-off control circuit module; the charge-discharge control circuit module is respectively connected with the negative input end of the comparator A1, the clock turn-off control circuit module and the positive input end of the hysteresis comparator A2; the output control circuit module is respectively connected with the positive input end of the comparator A1, the clock turn-off control circuit module and the output end of the hysteresis comparator A2; the output end of the comparator A1 is respectively connected with the negative input end of the hysteresis comparator A2 and the capacitor C; the comparator A1 and the hysteresis comparator A2 are respectively connected with a first tail current source and a second tail current source.
Further, the charge-discharge control circuit comprises a first resistor R1, a first capacitor C1, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and an NMOS transistor NMb; one end of the first resistor R1 is connected with a power supply, and the other end is connected with a first capacitor C1; the other end of the first capacitor C1 is grounded; the common end of the first resistor R1 and the first capacitor C is marked as a node VR(ii) a The gate of the first NMOS transistor NM1 is connected to the negative input terminal of the comparator A1, and the drain is connected to VRThe source is connected with the drain of the second NMOS tube NM 2; the grid electrode of the second NMOS tube NM2 is connected with the grid electrode of the NMOS tube NMb, and the source electrode is grounded; the grid of the third NMOS transistor NM3 is connected with the grid of the second NMOS transistor NM2, and the drain is connected with VRThe source electrode is grounded; the drain current of the NMOS tube NMb is connected with Ib。
Further, the output control circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first inverter INV1, and a second inverter INV 2; the grid electrode of the first PMOS tube PM1 is connected with the negative output end V of the hysteresis comparator A2ONThe source electrode is connected with a power supply, and the drain electrode is connected with the drain electrode of a fourth NMOS tube NM 4; the grid electrode of the fourth NMOS tube NM4 is connected with a clock turn-off control signal PD, and the source electrode is grounded; the drain of the fifth NMOS transistor NM5 is connected to NM4The grid electrode of the drain electrode is connected with the drain electrode, and the source electrode is grounded; the grid electrode of the sixth NMOS tube NM6 is connected with the grid electrode of NM5, the source electrode is grounded, and the drain electrode is connected with the drain electrode of the second PMOS tube PM 2; the gate of the second PMOS transistor PM2 is connected with the positive output end V of the hysteresis comparator A2OPA source connected to the power supply, a drain connected to the input end V of the first inverter INV1O1(ii) a An output end V of the first inverter INV1O2The output end of the INV2 is connected to the input end of the second inverter INV2, and outputs the clock signal CLK.
Further, the clock turn-off control circuit includes a third inverter INV3, a seventh NMOS tube NM7, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, and a reference current source Ibias; the clock turn-off control signal PD of the third inverter INV3, the output end is connected with the grid of a seventh NMOS tube NM 7; the drain of the seventh NMOS transistor NM7 is connected to Ibias, and the source is connected to the drain of the eighth NMOS transistor NM 8; the source electrode of the eighth NMOS tube NM8 is grounded, and the grid electrode of the eighth NMOS tube NM8 is connected with a clock turn-off control signal PD; the gate of the ninth NMOS transistor NM9 is connected to the drain of the eighth NMOS transistor NM8, and the drain is connected to IbiasThe source electrode is grounded; the gate of the tenth NMOS transistor NM10 is connected to the drain of NM4, and the drain is connected to IbAnd the source is grounded.
In the charge and discharge control circuit, the resistor R1 is formed by connecting two resistors with positive and negative temperature coefficients in series, and the proportionality coefficient is determined according to the condition that alpha R11+ beta R12 is 0, wherein alpha and beta are temperature coefficients.
Further, the capacitor C is a poly-type capacitor with a low temperature coefficient.
Further, the circuit is provided with a turn-off control signal PD, when PD is high, NM4 is on, the gate voltages of NM5 and NM6 are low, NM5 and NM6 are off, and the output control branch has no current passing.
Compared with the prior art, the utility model following beneficial effect has:
1. the utility model discloses introduced charge-discharge control circuit, utilized reference current to change and fill threshold voltage, output cycle is not influenced by mains voltage and temperature to oscillation signal's high accuracy and low temperature have been realized and have been floated
2. The utility model discloses introduce and turn-off control circuit, be about to system control signal PD control clock generation circuit and turn-off, turn-off clock production circuit when system's work finishes, reduced the static consumption of system.
Drawings
FIG. 1 is a schematic diagram of the on-chip clock generating circuit of the present invention;
fig. 2 is a schematic diagram of the power monitoring circuit of the embodiment of the present invention.
Detailed Description
The present invention will be further explained with reference to the drawings and the embodiments.
The present embodiment uses the stability of the portable microprocessor system as an improved object of the present embodiment, and the preferred device is a power monitoring system. Referring to fig. 2, the power monitoring circuit includes: the circuit comprises a voltage division circuit, a reference voltage source, a comparator, a clock generation circuit and a delay module; the voltage division circuit is used for generating a reset threshold voltage which is in a certain proportion to the input voltage; the reference voltage source is used for generating a reference voltage which is independent of the power supply voltage and the temperature; the comparator is used for comparing the divided voltage with a reference voltage, outputting a high level when the divided voltage reaches a threshold voltage, and controlling an enabling end of the delay module together with an on-chip reset signal after phase inversion so as to generate a reset signal with a certain time delay; the clock generating circuit is used for generating a clock signal of the delay unit; the time delay module is used for timing (the timing time t can be determined by setting the number n of the D triggers, and t is 2n×Tclk)。
As shown in fig. 1, in this embodiment, a circuit for implementing low temperature drift and low power consumption of an on-chip clock circuit includes a charge/discharge control circuit, a comparator a1, a hysteresis comparator a2, an output control circuit, and a clock turn-off control circuit.
The charge-discharge control circuit is used for controlling the charge-discharge voltage threshold of the capacitor C; the comparator A1 is used for judging the high and low potential of the output signal and controlling the capacitor C to provide a charge-discharge process; the hysteresis comparator A2 is used for comparing the voltage of the capacitor C with a reference potential VRComparing, and turning over to control output signals; the output control circuit is used for controlling the output signalHigh-low level of (1); the clock turn-off control circuit is used for turning off the clock under the system requirement, so that low power consumption is realized.
In this embodiment, the charge and discharge control circuit includes: the first resistor R1, the first capacitor C1, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3 and the NMOS transistor NMb; one end of the first resistor R1 is connected with a power supply, one end is connected with the first capacitor C1, the other end of the first capacitor C1 is grounded, and the common end of the first resistor R1 and the common end of the first capacitor C1 is marked as a node VR(ii) a The gate of the first NMOS transistor NM1 is connected to the negative input terminal of the comparator A1, and the drain is connected to VRThe source is connected with the drain of a second NMOS transistor NM2, the gate of NM2 is connected with the gate of NMb, and the source is grounded; the grid of the third NMOS tube NM3 is connected with the grid of NM2, and the drain is connected with VRThe source electrode is grounded; the drain current of the NMOS tube NMb is controlled by I of a turn-off control circuitbObtaining mirror images with consistent values of Ib；
The output control circuit includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first inverter INV1, and a second inverter INV 2; the grid electrode of the first PMOS tube PM1 is connected with the negative output end V of the hysteresis comparator A2ONThe source electrode is connected with a power supply, and the drain electrode is connected with the drain electrode of a fourth NMOS tube NM 4; the grid electrode of the fourth NMOS tube NM4 is connected with a clock turn-off control signal PD, and the source electrode is grounded; the drain of the fifth NMOS transistor NM5 is connected with the drain of NM4, the grid is connected with the drain, and the source is grounded; the grid electrode of the sixth NMOS tube NM6 is connected with the grid electrode of NM5, the source electrode is grounded, and the drain electrode is connected with the drain electrode of the second PMOS tube PM 2; the gate of the second PMOS transistor PM2 is connected with the positive output end V of the hysteresis comparator A2OPA source connected to the power supply, a drain connected to the input end V of the first inverter INV1O1. An output end V of the first inverter INV1O2The input end of the second inverter INV2 is connected, and the output end of the INV2 is the clock signal CLK.
The clock gating control circuit includes: a third inverter INV3, a seventh NMOS tube NM7, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, and a reference current source Ibias; the input end of INV3 is connected to the turn-off signal PD, the output end is connected to the grid of NM7, the drain of NM7 is connected to Ibias, the source is connected to the drain of NM8, the source of NM8Grounding, and connecting the grid with the PD; the gate of NM9 is connected to the drain of NM8, and the drain is connected to IbiasThe source is grounded, the gate of NM10 is connected to the drain of NM4, and the drain is connected to IbAnd the source is grounded.
The positive input end of the comparator A1 is connected with the input end V of the first inverter INV1O1The negative input end is connected with the output end V of the INV1O2INV1 output terminal VO2The input end of the INV2 is connected, and the output end of the INV2 is marked as a clock signal CLK; the output end of A1 is connected with the capacitor C and the negative input end V of the comparator A2CThe positive input end of A2 is connected with the output end V of the charge-discharge control circuitR(ii) a The tail current sources of the comparator A1 and the hysteresis comparator A2 are nI respectivelybAnd mIb，IbCan be controlled by a reference current source IbiasMirroring occurs where n and m are scaling factors.
Preferably, in the present embodiment, the capacitor C is a poly-type capacitor having a low temperature coefficient.
Preferably, in this embodiment, in the charge and discharge control circuit, the resistor R1 is formed by connecting two resistors with positive and negative temperature coefficients in series, and the proportionality coefficient is determined according to α R11+ β R12 being 0, where α and β are temperature coefficients and can be found in a model file of a process library; determination of VRTwo currents I1 and I2 of the node voltage are obtained by mirroring Ib according to a certain proportionality coefficient.
Preferably, in this embodiment, the output control circuit introduces a turn-off control signal PD, when PD is at a high level, NM4 is turned on, the gate voltages of NM5 and NM6 are at a low level, NM5 and NM6 are turned off, and the output control branch has no current passing therethrough, thereby reducing static power consumption.
In this embodiment, the circuit operates as follows:
when the power supply is powered on, the node voltage VCLess than the node voltage VRThe hysteresis comparator A2 outputs low level in positive direction, PM1 is turned off, PM2 is turned on, and the node V is connectedO1At a high level, VO2At low level, the comparator A1 outputs high level to charge the capacitor C, and the charging current is the tail current source nI of A1bWhile a low level signal VO2Turn off NM2 and branch currentWhen I1 is equal to 0, the voltage drop across the resistor R1 decreases, and the node voltage V is reducedRRise to VR1＝VCC-I2×R1；
The capacitor C is continuously charged when the voltage V on the capacitorCIs slightly larger than VR1The hysteresis comparator A2 outputs V in positive directionOPWhen the voltage is inverted from low to high, PM1 is turned on, PM2 is turned off, and node VO1At a low level, VO2At high level, the comparator A1 outputs low level, the capacitor C discharges, the tail current source nIb charges with A1, and the high level signal V is appliedO2NM2 is opened, branch current I1 passes through, the voltage drop on resistor R1 is increased, and node voltage VR is reduced to VR2＝VCC-(I1+I2)×R1；
The capacitor C is continuously discharged when the voltage V on the capacitorCSlightly less than VR2The hysteresis comparator A2 outputs V in positive directionOPAnd the high level is inverted into the low level. This is repeated to form the square wave oscillation output CLK.
In this embodiment, the capacitor C is at a voltage VR1And VR2Is periodically charged and discharged, wherein VR1＝VCC-I2×R1，VR2＝VCC-(I1+I2)×R1(ii) a Voltage variation Δ V on capacitorC＝VR1-VR2＝R1×I2From
To obtain
Wherein I is the tail current source of the comparator A1, and I2 are both IbiasThe temperature effect is eliminated after the ratio of the two.
The period of the clock CLK is
I is tail current source of comparator A1, and I2 is mirror image current of Ibias, and the ratio of the two currents obtains zero temperatureThe algebraic value of the degree coefficient. From the equation, the output signal CLK of the clock circuit is not affected by the power supply voltage, and the low temperature drift characteristic of the circuit is ensured by the low temperature coefficient capacitor C and the positive and negative temperature complementary resistor R1.
The above is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made according to the claims of the present invention should be covered by the present invention.
Claims (6)
1. An on-chip clock circuit with low temperature drift and low power consumption, comprising: the device comprises a charge-discharge control circuit module, a comparator A1, a hysteresis comparator A2, an output control circuit module and a clock turn-off control circuit module; the charge-discharge control circuit module is respectively connected with the negative input end of the comparator A1, the clock turn-off control circuit module and the positive input end of the hysteresis comparator A2; the output control circuit module is respectively connected with the positive input end of the comparator A1, the clock turn-off control circuit module and the output end of the hysteresis comparator A2; the output end of the comparator A1 is respectively connected with the negative input end of the hysteresis comparator A2 and the capacitor C; the comparator A1 and the hysteresis comparator A2 are respectively connected with a first tail current source and a second tail current source.
2. A low-temperature-drift low-power-consumption on-chip clock circuit according to claim 1, characterized in that: the charge-discharge control circuit comprises a first resistor R1, a first capacitor C1, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3 and an NMOS tube NMb; one end of the first resistor R1 is connected with a power supply, and the other end is connected with a first capacitor C1; the other end of the first capacitor C1 is grounded; the common end of the first resistor R1 and the first capacitor C is marked as a node VR(ii) a The gate of the first NMOS transistor NM1 is connected to the negative input terminal of the comparator A1, and the drain is connected to VRThe source is connected with the drain of the second NMOS tube NM 2; the grid electrode of the second NMOS tube NM2 is connected with the grid electrode of the NMOS tube NMb, and the source electrode is grounded; the grid of the third NMOS transistor NM3 is connected with the grid of the second NMOS transistor NM2, and the drain is connected with VRThe source electrode is grounded; the drain current of the NMOS tube NMb is connected with Ib。
3. A low-temperature-drift low-power-consumption on-chip clock circuit according to claim 1, characterized in that: the output control circuit comprises a first PMOS tube PM1, a second PMOS tube PM2, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a first inverter INV1 and a second inverter INV 2; the grid electrode of the first PMOS tube PM1 is connected with the negative output end V of the hysteresis comparator A2ONThe source electrode is connected with a power supply, and the drain electrode is connected with the drain electrode of a fourth NMOS tube NM 4; the grid electrode of the fourth NMOS tube NM4 is connected with a clock turn-off control signal PD, and the source electrode is grounded; the drain of the fifth NMOS transistor NM5 is connected with the drain of NM4, the grid is connected with the drain, and the source is grounded; the grid electrode of the sixth NMOS tube NM6 is connected with the grid electrode of NM5, the source electrode is grounded, and the drain electrode is connected with the drain electrode of the second PMOS tube PM 2; the gate of the second PMOS transistor PM2 is connected with the positive output end V of the hysteresis comparator A2OPA source connected to the power supply, a drain connected to the input end V of the first inverter INV1O1；An output end V of the first inverter INV1O2The output end of the INV2 is connected to the input end of the second inverter INV2, and outputs the clock signal CLK.
4. A low-temperature-drift low-power-consumption on-chip clock circuit according to claim 1, characterized in that: the clock turn-off control circuit comprises a third inverter INV3, a seventh NMOS tube NM7, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10 and a reference current source Ibias; the clock turn-off control signal PD of the third inverter INV3, the output end is connected with the grid of a seventh NMOS tube NM 7; the drain of the seventh NMOS transistor NM7 is connected to Ibias, and the source is connected to the drain of the eighth NMOS transistor NM 8; the source electrode of the eighth NMOS tube NM8 is grounded, and the grid electrode of the eighth NMOS tube NM8 is connected with a clock turn-off control signal PD; the gate of the ninth NMOS transistor NM9 is connected to the drain of the eighth NMOS transistor NM8, and the drain is connected to IbiasThe source electrode is grounded; the gate of the tenth NMOS transistor NM10 is connected to the drain of NM4, and the drain is connected to IbAnd the source is grounded.
5. The low-temperature drift low-power consumption on-chip clock circuit according to claim 2, wherein: in the charge-discharge control circuitThe resistor R1 is composed of two resistors with positive and negative temperature coefficients connected in series, and the proportionality coefficient is determined by
Is determined wherein
Is the temperature coefficient.
6. A low-temperature-drift low-power-consumption on-chip clock circuit according to claim 1, characterized in that: and the capacitor C is a poly-type capacitor with a low temperature coefficient.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113885633A (en) * | 2021-11-02 | 2022-01-04 | 中微半导体(深圳)股份有限公司 | Low-dropout NMOS (N-channel metal oxide semiconductor) type voltage stabilizer and hysteresis control method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113885633A (en) * | 2021-11-02 | 2022-01-04 | 中微半导体(深圳)股份有限公司 | Low-dropout NMOS (N-channel metal oxide semiconductor) type voltage stabilizer and hysteresis control method |
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