CN219122665U - Power-on reset system - Google Patents

Abstract

The utility model discloses a power-on reset system which comprises a reset signal generation module, a power-on reset module and a D trigger, wherein the reset signal generation module generates a reset enabling signal when power voltage is powered on, and inputs the reset enabling signal to an enabling end of the power-on reset module, a reset end of the D trigger and an input end of the D trigger respectively, an output end of the power-on reset module is connected with a clock end of the D trigger, an output end of the D trigger is connected with a control end of the power-on reset module and outputs a reset signal, and an output end of the power-on reset module outputs a signal to control the D trigger to output the reset signal; when the voltage of the enabling end of the power-on reset module is at a high level, the power-on reset module is turned off. After the power-on reset system of the power supply is powered on a system chip, the power-on reset module does not generate power consumption any more; meanwhile, the reset signal generating module does not generate power consumption, so that the whole power-on reset system does not generate power consumption, and the working performance of the whole system chip is improved.

Description

Power-on reset system

Technical Field

The utility model relates to the field of integrated circuits, in particular to a power-on reset system.

Background

In the power management system, a power-on reset circuit (POR) is required, and the POR is used for detecting the power supply voltage VDD in real time; as shown in fig. 1, a RESET signal (RESET signal) is generated at the initial stage of power-up of the power supply VDD to initialize the whole system chip; when VDD is high enough, POR follows the power supply voltage output through a set delay (Tdelay), so that each module works normally, resetting the whole chip circuit.

In the power-on stage, as shown in fig. 2, the power supply VDD starts to rise from 0, and when the power supply VDD is at a lower voltage, because the voltage of the node a is obtained by dividing the power supply VDD by the resistors R1 and R2, the voltage will be a voltage value lower than the power supply VDD, the voltage of the reference voltage VREF is the reference voltage obtained from other modules (reference modules), at this time, the voltage of the node a is compared with the voltage of the reference voltage VREF through the comparator, because the reference voltage VREF is greater than the voltage of the node a, and then the low level (RESET signal) is output through the delay module POR, the power supply VDD continuously rises, when the power supply VDD rises to the voltage of the node a is greater than the voltage VREF, the POR outputs the high level (following VDD voltage) through the delay module, and the RESET signal RESET releases, so that the chip system module works normally; the POR finishes resetting the initial state of the chip system in the power-on process of the power supply voltage VDD, and outputs high potential after the power supply is normal.

However, in the operation process of the POR circuit, relatively large power consumption is generated, and the main sources of the power consumption are as follows: a reference circuit for generating a reference voltage VREF, a comparator, and a voltage dividing circuit composed of a resistor R1 and a resistor R2; the presence of these power losses will affect the operation performance of the whole chip.

Accordingly, there is a need to provide a low-power or even no-power-on reset circuit or system that overcomes the above-described drawbacks.

Disclosure of Invention

The utility model aims to provide a power-on reset system, which is characterized in that after a system chip is powered on, the whole power-on reset module is turned off, so that the power-on reset module does not generate power consumption after the system chip is powered on and reset; meanwhile, the reset signal generation module does not generate power consumption, so that the whole power-on reset system does not generate power consumption, and the working performance of the whole system chip is improved.

In order to achieve the above purpose, the present utility model provides a power-on reset system, which includes a reset signal generating module, a power-on reset module and a D flip-flop, wherein the reset signal generating module generates a reset enable signal when a power voltage is powered on, and inputs the reset enable signal to an enable end of the power-on reset module, a reset end of the D flip-flop and an input end of the D flip-flop, an output end of the power-on reset module is connected with a clock end of the D flip-flop, an output end of the D flip-flop is connected with a control end of the power-on reset module and outputs a reset signal, and an output end of the power-on reset module outputs a signal to control the D flip-flop to output a reset signal; and when the voltage of the enabling end of the power-on reset module is at a high level, the power-on reset module is turned off.

Preferably, the power-on reset system further includes a first delay unit, and the first delay unit is connected between the reset signal generating module and an enable end of the power-on reset module.

Preferably, the power-on reset system further comprises a second delay unit, the second delay unit is connected between the D trigger and the control end of the power-on reset module, and the output end of the D trigger outputs a reset signal after passing through the second delay unit.

Preferably, the reset signal generating module includes a resistor, a capacitor, and a buffer, wherein one end of the resistor is connected with the power voltage, the other end of the resistor is connected with one end of the capacitor, the other end of the capacitor is grounded, the buffer is connected between the resistor and the capacitor, and the buffer outputs the reset enable signal.

Preferably, the buffer is formed by cascading a plurality of inverters.

Preferably, when the output signal of the D flip-flop is high level 1, a reset signal is output through the second delay unit and the power-on reset module is turned off.

Compared with the prior art, the power-on reset system has the advantages that the reset signal generation module does not have DC power consumption, so that no power consumption is generated in the operation process of the whole power-on reset system; in addition, after the power supply power-on reset system enables the system chip to be powered on, the whole power-on reset module is turned off through control of the reset signal, so that the power-on reset module does not generate power consumption after the system chip is powered on and reset; in the power-on reset system, the D trigger and the delay unit are all idle devices; therefore, the whole power-on reset system does not generate power consumption in the operation process, and the working performance of the whole system chip is improved.

The utility model will become more apparent from the following description taken in conjunction with the accompanying drawings which illustrate embodiments of the utility model.

Drawings

FIG. 1 is a timing diagram of a power supply voltage and a reset signal of a conventional power-on reset circuit.

Fig. 2 is a schematic block diagram of a prior art power-on reset circuit.

FIG. 3 is a block diagram of a power-on reset system of the present utility model.

Fig. 4 is a schematic structural diagram of a reset signal generating module of the power-on reset system of the present utility model.

FIG. 5 is a timing diagram of the voltage at each node of the power-on-reset system shown in FIG. 3.

Detailed Description

Embodiments of the present utility model will now be described with reference to the drawings, wherein like reference numerals represent like elements throughout. As described above, the present utility model provides a power-on reset system, and after the power-on reset system of the present utility model is powered on the system chip, the whole power-on reset module is turned off, so that the power-on reset module does not generate power consumption after the power-on reset of the system chip; meanwhile, the reset signal generation module does not generate power consumption, so that the whole power-on reset system does not generate power consumption, and the working performance of the whole system chip is improved.

Referring to fig. 3, fig. 3 is a block diagram illustrating a power-on reset system according to the present utility model. As shown in fig. 3, the power-on reset system of the present utility model includes a reset signal generating module, a power-on reset module and a D flip-flop DFF, wherein the reset signal generating module generates a reset enable signal VA at a node a when a power voltage VDD is powered on, and inputs the reset enable signal VA to an enable terminal EN of the power-on reset module, a reset terminal RST of the D flip-flop DFF and an input terminal D of the D flip-flop DFF, respectively, so that when the reset enable signal VA generated by the reset signal generating module is 0, the power-on reset module and the D flip-flop DFF are reset simultaneously; correspondingly, when the reset enabling signal VA generated by the reset signal generating module is 1, the power-on reset module is enabled to start working, and meanwhile, the D trigger outputs a reset signal. The output end VOUT of the power-on RESET module is connected with the clock end CLK of the D flip-flop to control the timing sequence of the output signal of the D flip-flop, and meanwhile, the output end VOUT output signal VF of the power-on RESET module controls the D flip-flop DFF to output a RESET signal RST, that is, when the output signal VF of the power-on RESET module is at a high level, the D flip-flop DFF is controlled to output the signal of the input end D thereof through the output end Q thereof, that is, an output signal VC (that is, a RESET signal RESET). The output end Q of the D trigger DFF is also connected with the control end PD of the power-on RESET module and outputs a RESET signal RESET, and when the voltage of the control end PD of the power-on RESET module is high (the output end Q of the D trigger DFF is 1), the power-on RESET module is turned off, and no power consumption is generated after the power-on RESET module is turned off; as described above, when the output Q of the D flip-flop is 1, it outputs the RESET signal RESET to RESET the system chip, and simultaneously, the control terminal PD turns off the power-on RESET module, so that the power-on RESET module turns off after the power-on RESET of the system chip, and thus, no power consumption is generated, and the working performance of the whole system chip is improved. The working principle of the D trigger DFF is as follows: the rising pulse edge occurs on the clock Clk, the data signal D is outputted, and the value of the last time (the data acquired on the last rising edge) is maintained during the falling edge until the next rising pulse edge comes to acquire new data, and q=0 is outputted when reset (rst=0) irrespective of the clock Clk.

In addition, as a preferred embodiment of the present utility model, the power-on reset system of the present utility model further includes a first delay unit and a second delay unit, where the first delay unit is connected between the reset signal generating module and the enable end EN of the power-on reset module; the second delay unit is connected between the D trigger and the control end PD of the power-on RESET module, and the output signal VC of the D trigger is output as a RESET signal RESET (signal VE) after passing through the second delay unit, and meanwhile, the RESET signal RESET is also input to the control end PD of the power-on RESET module, so that when the output signal VC of the D trigger DFF is high level 1, the RESET signal RESET is also output as 1 through the second delay unit, and the power-on RESET module is turned off through the control end PD; in the utility model, by setting the first delay unit and the second delay unit, the signal input to the enable end EN of the power-on reset module, the signal input to the reset end RST of the D trigger and the signal input to the control end PD of the power-on reset module are more stable, so that the edge information of the reset signal VA output by the reset signal generating module and the VC in the output signal of the D trigger is effectively prevented from being output, and the influence on the output result caused by the generation of various possible transient jump edges is prevented; the specific delay time periods of the first delay unit and the second delay unit may be set according to actual use requirements, which is not particularly limited in the present utility model.

Referring to fig. 4 in combination, as shown in fig. 4, the reset signal generating module includes a resistor R, a capacitor C, and a buffer, wherein one end of the resistor R is connected to an external power VDD, the other end of the resistor R is connected to one end of the capacitor C, the other end of the capacitor C is grounded, the buffer is connected between the resistor R and the capacitor C, and the buffer outputs the reset enable signal; the buffer is formed by cascading a plurality of inverters (P1, P2 … … Pn), and the buffer formed by cascading the inverters does not generate power consumption in the operation process, so that the whole reset signal generation module is ensured not to generate power consumption. In the initial stage of rising of the power supply voltage VDD, the voltage of the node a also slowly rises due to the existence of the resistor R and the capacitor C, and a buffer cascaded by using inverters (P1, P2 … … Pn) is connected at the rear of the node G, when the voltage of the node G reaches a certain value, the whole reset signal generating module outputs a high level, and follows the power supply voltage VDD, namely the output reset enable signal VA is a high level; in the circuit structure, in the direct current state, the whole reset signal generation module has no power consumption overhead due to the existence of the capacitor C, so that the power-on reset system of the whole power supply is further ensured to generate no power consumption in the operation process.

The following describes the working principle of the power-on reset system according to the present utility model with reference to fig. 3, 4 and 5: when the power supply is powered on, after a delay Tdelay0 (the delay is brought by the reset signal generating module), the relation between the node A voltage VA and the power supply voltage VDD is shown in FIG. 5; after passing through the first delay unit, the node B voltage VB is obtained by passing through a delay Tdelay1 (the delay is brought by the first delay unit), and in the delay Tdelay1 stage, because the node B is 0, the output of the power-on reset module (i.e. the node F) is 0, so that the node C is also 0; therefore, when the voltage VB of the node B changes from 0 to 1 at the end of the delay Tdelay1 stage, the power-on reset module starts to work normally, and then the output node F of the power-on reset module starts to change from 0 to 1, see the rising edge of VF in fig. 5, and meanwhile, the node F is connected to the clock end Clk of the D flip-flop DFF, and outputs data when the rising edge of the clock arrives, where the data is the voltage of the node a, and the voltage of the node a is high, so that the voltage of the node C is high (see the working principle of the D flip-flop DFF). At this time, the node D (i.e., the output RESET signal RESET) is obtained by the node C through a delay Tdelay2 (this delay is brought by the second delay unit). When the RESET signal RESET changes from 0 to 1, i.e. when the delay Tdelay2 phase is finished, the control terminal PD of the power-on RESET module of the RESET signal RESET is connected, so that the power-on RESET module is turned off, the output of the power-on RESET module is 0 (i.e. node F), the timing chart is shown in fig. 5, and at this time, the power-on RESET module also has no power consumption overhead. The power-on process of the voltage power supply VDD is finished, but the whole power-on reset system has no power consumption overhead in the power-on process.

In summary, in the power-on reset system of the present utility model, the reset signal generating module has no DC power consumption, so no power consumption is generated in the operation process of the whole power-on reset system; in addition, after the power supply power-on RESET system enables the system chip to be powered on, the whole power-on RESET module is turned off through control of the RESET signal RESET, so that the power-on RESET module does not generate power consumption after the system chip is powered on and RESET; in the power-on reset system, the D trigger DFF and the delay units (a first delay unit and a second delay unit) are all idle devices; therefore, the whole power-on reset system does not generate power consumption in the operation process, and the working performance of the whole system chip is improved.

The utility model has been described in connection with the preferred embodiments, but the utility model is not limited to the embodiments disclosed above, but it is intended to cover various modifications, equivalent combinations according to the essence of the utility model.

Claims (6)

1. The power-on reset system is characterized by comprising a reset signal generation module, a power-on reset module and a D trigger, wherein the reset signal generation module generates a reset enabling signal when power voltage is powered on, and inputs the reset enabling signal to an enabling end of the power-on reset module, a reset end of the D trigger and an input end of the D trigger respectively, an output end of the power-on reset module is connected with a clock end of the D trigger, an output end of the D trigger is connected with a control end of the power-on reset module and outputs a reset signal, and an output end of the power-on reset module outputs a signal to control the D trigger to output the reset signal; and when the voltage of the enabling end of the power-on reset module is at a high level, the power-on reset module is turned off.

2. The power-on reset system of claim 1, further comprising a first delay unit coupled between the reset signal generation module and an enable terminal of the power-on reset module.

3. The power-on reset system of claim 2, further comprising a second delay unit, wherein the second delay unit is connected between the D flip-flop and the control terminal of the power-on reset module, and the output terminal of the D flip-flop outputs a reset signal after passing through the second delay unit.

4. The power-on reset system of claim 1, wherein the reset signal generation module comprises a resistor, a capacitor and a buffer, wherein one end of the resistor is connected with a power voltage, the other end of the resistor is connected with one end of the capacitor, the other end of the capacitor is grounded, the buffer is connected between the resistor and the capacitor, and the buffer outputs the reset enable signal.

5. The power-on reset system of claim 4 wherein said buffer is formed by a cascade of inverters.

6. The power-on reset system of claim 3 wherein when the output signal of said D flip-flop is high 1, a reset signal is output through said second delay element and said power-on reset module is turned off.

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