KR100240604B1 - Reset circuit for ic circuit power supply - Google Patents

Abstract

Disclosed is a power on reset circuit for an integrated circuit for resetting the integrated circuit immediately before powering on the integrated circuit when the integrated circuit is powered on. When power is applied to the circuit from the outside, the counter circuit section outputs a counter value counted by counting a clock signal from the outside to a logic product gate whose output terminal is connected to the power supply of the circuit, and the logic product gate is output from the counter circuit section. Reset the connected circuit according to the logic signal. It can provide a constant power-on reset period, regardless of the component value of the device, and is composed of digital logic devices, which does not limit the semiconductor manufacturing process and design.

Description

Power-On Reset Circuit for Integrated Circuits

The present invention relates to a power-on reset circuit for an integrated circuit. More particularly, the present invention relates to an integrated circuit power-on reset circuit for resetting the integrated circuit immediately before the integrated circuit is powered on.

1 is a circuit diagram showing a conventional power-on reset circuit for an integrated circuit.

The conventional power-on reset circuit 100 for an integrated circuit is composed of a resistor (R), a capacitor (C), and a buffer 110. One end of the resistor R is connected to an external power source, and the other end of the resistor R is connected to the capacitor C and the buffer 110. The input terminal of the capacitor C is connected to the resistor R, and the output terminal thereof is grounded. An input terminal of the buffer 110 is connected to the resistor R, and an output terminal thereof is connected to a power supply wiring (not shown) in the integrated circuit to supply power to other circuits in the integrated circuit.

2A and 2B are waveform diagrams for explaining the operation of the power-on reset circuit for the integrated circuit of FIG. In the reset circuit 100 shown in FIG. 1, when a power source V _DD is applied to the circuit from the outside, power is supplied to the resistor R connected to the external power source as shown in FIG. 2A. The power supply which jumped to V _DD at the initial voltage V _t0 at the time point t ₀ is applied to the resistor R. The initial voltage V _t0 is a voltage just before the power supply V _DD of the capacitor C is applied to the resistor R.

When the power source V _DD is applied to the resistor R, the output voltage of the capacitor C (the input voltage of the buffer) gradually increases by the charging time of the capacitor C as shown in FIG. 2B. Done. When the threshold voltage V _T of the buffer 110 is set to the time constant (R · C) voltage of the capacitor C, the output voltage V _O of the buffer 110 is the capacitor C The logic low voltage is maintained until the charge voltage of the buffer rises to the threshold voltage V _T of the buffer. The voltage output of the logic low of the buffer 110 eventually resets the integrated circuit, and the time for which the charging voltage of the capacitor C rises to the threshold voltage V _T of the buffer 110 is increased. Is the reset time.

However, in the power-on reset circuit, in order to implement the circuit in an integrated circuit, a process for forming the resistor and the capacitor, which are passive elements, is required, and the values of the resistor and the capacitor are varied according to the process so that the resistor and the capacitor are There is a problem that the power-on reset cycle is irregular due to the change of the value. In addition, the power-on reset circuit has a problem that the inspection process becomes complicated as the power-on reset cycle becomes irregular.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a power-on reset circuit for an integrated circuit that provides a constant power-on reset period irrespective of the component value of the device.

Another object of the present invention is to provide a power-on reset circuit for an integrated circuit composed of digital logic elements, which does not limit the semiconductor manufacturing process and design.

1 is a circuit diagram showing a conventional power-on reset circuit for an integrated circuit.

2A and 2B are waveform diagrams for explaining the operation of the power-on reset circuit for the integrated circuit of FIG.

3 is a diagram illustrating a power-on reset circuit for an integrated circuit according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

200: frequency division circuit unit 300: counter circuit unit

310, 320, 330, 340: Counter 400: Logic Product Gate

210, 311, 321, 331, 341: inverter gate

A power-on reset circuit for an integrated circuit according to the present invention for realizing the above objects of the present invention is a reset for generating a reset signal based on a clock signal input from a clock signal generating means to a predetermined circuit when power is applied from the outside. Signal generating means; And reset driving means for grounding the circuit or powering on in the ground state in accordance with the reset signal generated by the reset signal generating means.

According to the present invention, the integrated circuit is grounded when the power is applied to the integrated circuit, the clock signal is counted from the clock generator, and the period of the reset signal is adjusted according to the count, thereby providing a sufficient reset period when the integrated circuit is powered. Can reset the integrated circuit.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a diagram illustrating a power-on reset circuit for an integrated circuit according to an exemplary embodiment of the present invention.

In FIG. 3, the power-on reset circuit for the integrated circuit is composed of a divider circuit portion 200, a counter circuit portion 300, and a logic product gate 400. The division circuit unit 200 divides a clock signal generated by a clock generator (not shown) to generate a division signal 201, and provides the generated division signal 201 to the counter circuit unit 300. The counter circuit unit 300 includes first, second, third and fourth counters 310, 320, 330, and 340, and first, second, third and fourth inverter gates 311, 321, and 331. , And 341). The first, second, third and fourth counters 310, 320, 330, and 340 have first, second, third, and fourth counter values, respectively. The first, second, third and fourth counter values are arbitrarily set in circuit design. The first, second, third, and fourth counters 310, 320, 330, and 340 may be configured to determine clock signals (or divided signals) corresponding to the set first, second, third, and fourth counter values. On the rising edge, output its output value, that is, the signal whose logic state has changed. For example, when the first counter value of the first counter 311 is 4, the first counter 311 counts an input clock signal and goes from a logic low to a logic high at the rising edge of the fourth clock. Output the changed counter signal.

In addition, the first, second, third and fourth counters 310, 320, 330, and 340 respectively input counter signals 3101, 3201, 3301, and 3401 to the input terminal of the logical product gate 400. And output to the first, second, third and fourth inverter gates 311, 321, 331, and 341, respectively. The first, second, third and fourth inverter gates 311, 321, 331, and 341 may be formed of the first, second, third, and fourth counters 310, 320, 330, and 340, respectively. The first, second, third and fourth counter signals 3101, 3201, 3301, and 3401 connected to the respective output terminals RCO and the respective control terminals CEN to be output from the respective output terminals RCO. Inverting is provided to each control terminal CEN of the first, second, third and fourth counters 310, 320, 330, and 340. The first, second, third, and fourth counters 310, 320, 330, and 340 may be configured to have counters regardless of clock input when a logic low signal is input to the control terminal CEN, respectively. Maintain the output of the signal.

The logical product gate 400 is configured to provide the respective first, second, third and fourth counter signals from the first, second, third and fourth counters 310, 320, 330, and 340. When any one of (3101, 3201, 3301, and 3401) is a logic low, the logic low signal is output, and the first, second, third, and fourth counter signals 3101, 3201, 3301, and When all of 3401 are logic high signals, transition from logic low to logic high generates a reset signal 401.

Hereinafter, the operation of the power-on reset circuit for integrated circuits configured as described above will be described in detail.

First, when power is supplied to an integrated circuit (not shown) including the power-on reset circuit of FIG. 3, the division circuit unit 200, the counter circuit unit 300, and the logic product gate 400 are connected to an in-line circuit. Enabled. In addition, the first, second, third, and fourth counters 310, 320, 330, and 340 of the counter circuit unit 300 output the logic low signals through the output terminals RCO. To 400). Accordingly, the logic product gate 400 connects a logic low signal from the first, second, third, and fourth counters 310, 320, 330, and 340 to an output terminal of the logic product gate 400. Output to other circuits in the integrated circuit to ground the integrated circuit. The output of the logic low of the logic product gate 400 is an input signal of the logic product gate 400, that is, the output of the first, second, third and fourth counters 310, 320, 330, and 340. All of this continues until the logic high signal is output.

As the divided signals are continuously output from the divided circuit 200, the first, second, third and fourth counters 310, 320, 330, and 340 count rising edges of the divided divided signals. The first, second, third, and fourth counters 310, 320, 330, and 340 each have a number of rising edges of the divided signal 201 for the first, second, third, and fourth counter values. When the rising edge of is inputted, the first, second, third and fourth counters 310, 320, 330, and 340 respectively receive the first, second, third and fourth counter signals 3101 and 3201. , 3301, and 3401 output a logic high signal to the logic product gate 400. The logic product gate 400 then outputs a logic high signal at a logic low to power the other circuitry in the integrated circuit.

Therefore, according to the above configuration, the integrated circuit is grounded when power is applied to the integrated circuit, the clock signal is counted from the clock generator, and the period of the reset signal is adjusted according to the count, thereby providing sufficient reset when powering on the integrated circuit. It is possible to reset the integrated circuit with a period.

As described above, the present invention provides a power-on reset circuit for an integrated circuit that can provide a constant power-on reset period regardless of the component value of the device, and is composed of digital logic elements, which does not limit the semiconductor manufacturing process and design. It can be realized.

Although this invention was demonstrated concretely by the said Example, this invention is not restrict | limited by this, A deformation | transformation and improvement are possible within the normal knowledge of a person skilled in the art.

Claims (5)

Reset signal generating means (200, 300) for generating a reset signal on the basis of a clock signal input when power is supplied from an external source to a predetermined circuit; And And reset driving means (400) for grounding or off from the ground in accordance with the reset signal generated by the reset signal generating means. The counter signal generating apparatus of claim 1, wherein the reset signal generating means (200, 300) counts the input clock signal and generates one or more counters (300) for generating the logic signal for the reset signal according to whether the clock is input a predetermined number of times. Power-on reset circuit for an integrated circuit, characterized in that consisting of. The logic of claim 1, wherein the reset signal generating means (200, 300) comprises at least one divider (200) for dividing the input clock signal, and generates logic from the at least one divider. And a signal is output as the reset signal. 2. The apparatus of claim 1, wherein the reset signal generating means comprises: at least one frequency division circuit part (200) for frequency division of the input clock signal; And And one or more counters 300 for counting the divided signals generated by the one or more frequency division circuits to generate the logic signals for the reset signals according to whether the logic signal of the frequency division circuit portion has been input a predetermined number of times. Power-on reset circuit for integrated circuits. 2. The integrated circuit according to claim 1, wherein said reset driving means (400) comprises a logic product gate (400) whose input end is connected to an output end of said reset signal generating means and whose output end is connected to said circuit. Power-on reset circuit for the circuit.