JPH10207580A - Power on reset generation circuit, semiconductor integrated circuit and ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a power ON reset generation circuit capable of accurately generating a power ON reset signal when power supply voltage reaches a prescribed level and interrupting the generation of the power ON reset signal when power supply voltage is within an allowable range even if the voltage is changed. SOLUTION: Reference voltage is inputted to the input terminal of a comparator CMP for comparing voltage divided by voltage dividing resistor circuits R11, R12 for dividing power supply voltage with reference voltage Vref generated from a band gap reference voltage generation circuit through a resistor R13. A pull down circuit consists of a resistor R14 and a switch transistor(TR) Qs mutually connected in series, the TR Qs is controlled by an output signal, and after generating a power ON reset signal, the comparing level of the comparator CMP is forcedly reduced by the resistors R13, R14 as compared with that held before the generation of the power ON reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a power-on reset generation circuit in a semiconductor integrated circuit, and more particularly to a power-on reset generation circuit in a semiconductor integrated circuit for a transceiver used in a non-contact type IC card. Regarding effective technology to use.

[0002]

2. Description of the Related Art There has been proposed a non-contact type IC card which transmits and receives data and receives electric power by utilizing a mutual induction phenomenon of coils. Such a non-contact type IC card includes a microcomputer for performing data processing, and a semiconductor integrated circuit for a transceiver connected between the microcomputer and the coil for transmitting and receiving data to and from an external device. In such a semiconductor integrated circuit for a transceiver, a power supply voltage and a received data signal are generated from an AC signal input through a coil using electromagnetic coupling. A power-on reset generation circuit is provided for generating a reset pulse supplied to the microcomputer when the DC signal is generated by rectifying the AC signal, that is, when the power supply voltage rises.

Conventionally, as a power-on reset generation circuit, for example, there has been a circuit as shown in FIGS. 7A and 7B.

Among them, the circuit shown in FIG.
A time constant circuit and an inverter are combined, and a power-on reset pulse is generated when the potential of the time constant circuit exceeds the logical threshold level of the inverter G1. On the other hand, the circuit shown in FIG. 7B includes a voltage dividing circuit for dividing the power supply voltage by resistance before the circuit of FIG. 7A, and a comparator CMP for comparing the divided voltage with the reference voltage Vref. Is provided.

[0005]

SUMMARY OF THE INVENTION The present inventors have studied a power-on reset generation circuit in a transceiver semiconductor integrated circuit used for a non-contact type IC card.

A power-on reset generation circuit that outputs a reset pulse to a microcomputer when the power supply voltage rises needs to output a reset pulse after the power supply voltage has reached a level at which the microcomputer does not malfunction. In the circuit A), the power supply voltage of the inverter itself for detecting the level of the power supply voltage fluctuates, and the logic threshold value of the inverter varies due to process variations. Is difficult to set.

On the other hand, in the circuit of FIG. 7B, there is a possibility that an unnecessary reset pulse is generated when the power supply voltage drops. Particularly, in the case of a non-contact type IC card, since the positioning of the card is relatively rough, the coupling state between the card and its read / write device changes, and the power supply voltage tends to fluctuate. Highly likely to occur.

An object of the present invention is to provide a power-on reset generation circuit that can accurately generate a power-on reset signal when a power supply voltage reaches a predetermined level.

Another object of the present invention is to provide a power-on reset generation circuit which does not generate a power-on reset signal if the power supply voltage fluctuates within an allowable range.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, the power-on reset generation circuit of the present invention provides an input terminal of a comparator for comparing a voltage divided by a resistance voltage division circuit for dividing a power supply voltage with a reference voltage from a band gap reference voltage generation circuit. A reference voltage is input through a resistor, and a pull-down circuit including a resistor in series form and a switch transistor is connected to the switch transistor. The switch transistor is controlled by an output signal. The comparator comparison level is forcibly made lower than before the power-on reset signal is generated. A time-constant circuit which starts the charging with a power supply voltage by a signal from a receiving circuit or an input circuit which makes an output of the comparator an enable signal, and shapes an input AC signal at a stage subsequent to the comparator; And a logic circuit that outputs a power-on reset signal when the level of the charging voltage is determined and reaches a predetermined level.

According to the above-mentioned means, a power-on reset signal is generated based on a reference voltage from a bandgap reference voltage generating circuit capable of generating a constant voltage in a semiconductor integrated circuit irrespective of a change in temperature or a change in power supply voltage. Output, a power-on reset signal can be accurately generated when the power supply voltage reaches a predetermined level, and after the power-on reset signal is generated, the power supply voltage fluctuates to lower the comparison level of the comparator. Even if it is within an allowable range, that is, higher than a stable operation level of a circuit (microcomputer or the like), a power-on reset signal can be prevented from being generated. Further, since a time constant circuit that uses the output of the comparator as an enable signal is provided at a stage subsequent to the comparator, it is possible to generate a power-on reset signal after the power supply voltage sufficiently exceeds the stable operation level of the circuit. it can.

The time constant circuit includes a switch which is turned on and off by a signal from a receiving circuit or an input circuit for shaping an input AC signal, and a charge comprising a capacitor into which electric charge is injected when the switch is turned on. Use a pump circuit. This allows the charge pump circuit to perform the charging operation in accordance with the intensity, that is, the amplitude of the input AC signal, and output the power-on reset signal at an appropriate timing in accordance with the rising speed of the power supply voltage.

Further, a reset pulse generating circuit which counts a clock signal from the clock generating circuit after generating the power-on reset signal and outputs a reset pulse when the count exceeds a predetermined number is provided at the next stage of the power-on reset generating circuit. It is good to provide. As a result, a reset pulse for a microcomputer or the like can be generated after the clock signal is reliably generated, and malfunction of the microcomputer or the like can be prevented.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a transceiver IC 10 used in a non-contact type IC card provided with a power-on reset generation circuit according to the present invention and a schematic configuration of an entire IC card on which the transceiver is mounted.

An IC card mounted with a transceiver IC according to this embodiment has, for example, a coil L spirally formed by a printed wiring layer, and is connected to both terminals of the coil L to transmit / receive data and generate a power supply voltage. Transceiver IC 10, a microcomputer chip 20 connected to the transceiver IC 10 for processing, storing, and forming transmission data, and external capacitors CF, C connected to the transceiver IC 10.
It is composed of t1, Ct2 and the like. Although the figure shows a coil having one spiral pattern, a coil having two similar spiral patterns may be used depending on the configuration of the head of an external read / write device.

The microcomputer chip 20 is an electrically programmable and erasable EEPROM as a storage device.
M is built in so that data can be retained even when the IC card is ejected from the read / write device and is not supplied with power.

Although not particularly limited, transceiver ICs
Circuit elements constituting each block in 10 are formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

1 is an external terminal T of the transceiver IC 10
1, a rectifier circuit comprising a diode bridge for rectifying an AC signal input from a coil L as an electromagnetic coupling means connected (externally connected) to T2 to generate a DC power supply voltage;
The output node of the rectifier circuit 1 is connected to an external terminal T3, and a power supply filter capacitor CF having a relatively large capacitance value such as 10 nF can be connected to the external terminal T3. Reference numeral 2 denotes a voltage limiter circuit that absorbs fluctuations in the voltage rectified by the rectifier circuit 1 to generate a power supply voltage Vcc having a predetermined potential of 6 to 20 V, and 3 denotes a generated power supply voltage Vcc.
A power supply stabilizing circuit comprising a series regulator for stabilizing cc. The power supply voltage VDD output from the power supply stabilizing circuit 3 is supplied to each circuit inside the chip, and a microcomputer connected to an external terminal T4. It is also supplied to the chip 20.

4 is a power-on reset generation circuit for monitoring the power supply voltage VDD output from the power supply stabilization circuit 3 and generating a power-on reset signal when the power is turned on. 5 is a reset pulse Pr for the external microcomputer chip 20. Is a reset pulse generation circuit that generates the reset pulse.
The reset pulse generation circuit 5 generates a reset pulse Pr when a predetermined number of clock signals output from a clock generation circuit composed of a PLL circuit described later are counted after the output of the power-on reset generation circuit 4 rises to a high level. And outputs it to the microcomputer chip 20 from the external terminal T5.

Reference numeral 6 denotes the coil connecting external terminals T1 and T2.
And a data receiving circuit 7 for waveform-shaping and outputting the input AC signal, and outputting "0" and "1" from the waveform-shaped signal.
The demodulated data is supplied from an external terminal T6 to the microcomputer chip 20.
Output to Although not particularly limited, the transceiver IC of this embodiment is configured to detect a phase change of a PSK (Phase Shift Keying) modulated signal and demodulate data. The data demodulation circuit 7 can be composed of, for example, a flip-flop that latches a signal output from the data reception circuit 6 in synchronization with a clock signal supplied from a clock generation circuit described later.

Reference numeral 8 denotes 4.91 included in the input AC signal based on the signal shaped by the data receiving circuit 6.
A clock generation circuit for generating a clock signal CLK synchronized with a reference clock signal having a frequency of MHz.
And the microcomputer 20 and the like outside the chip via the external terminal T7. Reference numeral 9 denotes a drive MOSFET Qd having a drain terminal connected to the external terminals T9 and T10 based on serial transmission data input from the microcomputer chip 20 via the external terminal T8.
1 and Qd2 are turned on and off, and capacitors Ct1,
A data transmission circuit including a buffer circuit and the like for transmitting data by switching a resonance circuit including Ct2 and the coil L between a resonance state and a non-resonance state.

The clock generation circuit 8 composed of the PLL circuit of this embodiment includes a reference clock signal CKin extracted from an AC signal inputted from the outside and a feedback clock signal C
A phase comparator 80 for detecting a phase difference of Kf;
A control voltage Vc according to the phase difference, which is composed of R2 and the capacitor C1.
o, a voltage-controlled oscillator 84 that oscillates at a frequency corresponding to the control voltage Vco from the loop filter 83, and monitors the output voltage Vco of the loop filter 83 to prevent erroneous locking of the PLL. An erroneous lock prevention circuit 85 that forms a signal and an oscillation allowable signal of the oscillator and supplies the signal to the charge pump 82 and the voltage controlled oscillator 84 and a frequency divider 86 that divides the oscillation signal of the voltage controlled oscillator 84. ing.

The clock signal CLK output from the frequency divider 86 is used as the feedback clock CKf as the phase comparator 8
1 and supplied to the data demodulation circuit 7, the reset pulse generation circuit 5, and the external microcomputer chip 20 as a system clock.

FIG. 2 shows an embodiment of the power-on reset generation circuit 4.

The power-on reset generation circuit 4 of this embodiment is provided with a power supply voltage V supplied from the power supply stabilization circuit 3.
Resistors R11, R1 connected in series between DD and ground
2 and a voltage corresponding to the bandgap of silicon (1...) Receiving the potential of the connection node n1 of the resistors R11 and R12 at the inverting input terminal and the non-inverting input terminal.
0 to 1.2 V) from the bandgap reference voltage generating circuit.
And a time constant circuit CRG that operates using the output of the comparator CMP as an enable signal, and inverters G1 and G2 connected to the subsequent stage.

A reference voltage Vref is input to a non-inverting input terminal of the comparator CMP via a resistor R13, and a pull-down circuit including a resistor R14 in series form and a switch transistor Qs is connected to the switch. The output signal of the inverter G2 is fed back to the base of the transistor Qs via the resistor R15. Further, the time constant circuit CRG is provided with the comparator CM
An output voltage Vcom of P is received at a base via a resistor R16, and a control transistor Q1 having an emitter connected to a ground point, and a switch MO connected to the collector of the transistor Q1.
The MOSFET Q includes a constant current source I1 connected via an SFET Q2, and a capacitor C2 connected between the collector of the transistor Q1 and a ground point.
The pulse φi from the data receiving circuit 6 described above
Is input, and the input terminal of the inverter G1 is connected to a connection node n2 between Q2 and the capacitor C2.

Next, the power-on reset generation circuit 4
Will be described with reference to the timing chart of FIG.

When the power supply voltage VDD starts to rise, first, the comparator CMP is activated, the output thereof becomes high level, the transistor Q1 is turned on, the charge of the capacitor C2 is extracted, and the potential of the node n2 is changed to the ground potential. It is said. Therefore, at this time, the output of the inverter G1 is high level,
2 is low level, the transistor Qs on the non-inverting input terminal side of the comparator CMP is turned off, and the reference voltage Vref is applied to the non-inverting input terminal as it is. Then, the power supply voltage VDD further rises and the resistances R11, R1
2 is divided by the reference voltage Vre
f, the output Vcom of the comparator CMP
Is inverted to a low level to turn off the transistor Q1 (timing t1 in FIG. 3).

On the other hand, since the clock-like pulse φi is input from the data receiving circuit 6 to the gate of the switch MOSFET Q2, Q2 is repeatedly turned on and off, and the capacitor from the constant current source I1 is turned on while Q2 is on. Electric charge flows into C2 and is charged, and the potential Vn2 of the node n2 gradually increases. The potential Vn2 of the node n2 becomes higher than the logical threshold value of the inverter G1 (timing t2 in FIG. 3).
Then, the output of the inverter G1 changes from the high level to the low level, and this is supplied to the next-stage reset pulse generation circuit 5 as the power-on reset signal Pon. Then, the reset pulse generation circuit 5 composed of a counter counts the clock pulses, and when a predetermined number is counted, the output changes from a low level to a high level (at timing t in FIG. 3).
3) This is output to the microcomputer chip 20 and the like as a reset pulse Pr.

When the output of the inverter G1 goes low, the output of the next-stage inverter G2 goes high, thereby turning on the transistor Qs. Then, the reference voltage Vref is applied to the non-inverting input terminal of the comparator CMP.
Is divided by the ratio of the resistors R13 and R14, and the comparison level is forcibly lowered compared to before the power-on reset signal is generated. As a result, in the case where the power supply voltage level is determined only by the reference voltage Vref without the transistor Qs, the power supply voltage VDD is reduced to the determination level Vb (= Vref) or less, as indicated by the symbol A in FIG. The output of the device CMP is inverted to turn on the transistor Qs,
Although the charge of the capacitor C2 is discharged and the power-on reset signal Pon rises to a high level and causes the reset pulse Pr to fall, the circuit of this embodiment is used when the power supply voltage VDD falls below Vc lower than Vb. For the first time, the output of the comparator CMP is inverted and the power-on reset signal Pon changes to low level (FIG. 3).
Timing t4).

Therefore, the resistors R13 and R1 are set so that the voltage Vc matches the operation stable voltage of the microcomputer.
By setting the resistance ratio to 4, the power supply voltage VDD has risen sufficiently and the microcomputer has started operation. In such a case, if the power supply voltage is higher than the operation stable voltage Vc of the microcomputer, it is possible to prevent the reset pulse Pr from falling and resetting. That is, when the power supply voltage VDD fluctuates as shown by a chain line A in FIG. When the power-on reset generation circuit of the above embodiment is used, the microcomputer is not reset. In FIG. 3, Vd is the lowest voltage level at which the circuit of the embodiment operates.

FIG. 4 shows a more specific embodiment of the power-on reset generation circuit 4.

In FIG. 4, the same circuit portions as those in FIG. 2 are denoted by the same reference numerals. The circuit of this embodiment has the same basic configuration as the circuit of FIG. 2 and has the same operation and effect. In this embodiment, in addition to the circuit of the first embodiment, a capacitor C3 for removing noise from the power supply voltage VDD is provided between the inverting input terminal (-) of the comparator CMP and the ground point. A resistor R1 for dividing the power supply voltage VDD
1 and R12 are set to resistance values such as 10 kΩ and 90 kΩ, respectively, and the capacitance C2 is set to a capacitance value such as 25 pF.

The comparator CMP includes a differential amplifier circuit 11 composed of Darlington-connected input transistors Q11, Q12 and Q13, Q14, active load transistors Q15, Q16, a common output emitter transistor Q17, and constant current transistors Q21 to Q24. , And a bias circuit 12 for applying a base bias voltage to the constant current transistors Q21 to Q24. The constant current source I1 constituting the time constant circuit CRG includes a transistor Q41 having a base applied with the same reference voltage as the reference voltage Vref applied to the non-inverting input terminal of the comparator CMP and flowing a predetermined current;
MOSFETs Q42 and Q43 which are connected to the collector side of this transistor Q41 and constitute a current mirror circuit
And the drain of Q43 is connected to the switch MO
It is connected to the drain of the SFET Q2 to supply a current for charging up the capacitor C2. The inverter G1 is formed by series-type MOSFETs Q51 and Q52, and the inverter G2 is formed by a series-type MOSFET Q6.
1 and Q62.

FIGS. 5 and 6 show modifications of the power-on reset generation circuit of FIG.

5 uses a MOSFET in place of the bipolar transistors Qs and Q1 in the embodiment of FIG. 2, and is substantially the same as the power-on reset generation circuit of FIG. Has an effect. By using MOSFETs as Qs and Q1, the resistors R15 and R16 serving as base resistors become unnecessary. The inverters G1 and G2 are also omitted.

The circuit of the embodiment of FIG. 6 uses a resistor R17 instead of the MOSFET Q2 of the time constant circuit CRG in the embodiment of FIG. 2, and uses a CR time constant circuit instead of the charge pump type time constant circuit. Has almost the same operation and effect as the power-on reset generation circuit of FIG.

As described above, the power-on reset generation circuit according to the above-described embodiment compares the voltage divided by the resistance voltage dividing circuit for dividing the power supply voltage with the reference voltage from the band gap reference voltage generating circuit. A reference voltage is input to the input terminal of the device via a resistor, and a pull-down circuit including a resistor in series form and a switch transistor is connected, and the switch transistor is controlled by an output signal. A receiving circuit for forcibly lowering the comparison level of the comparator by a resistor as compared with before the power-on reset signal is generated, and using the output of the comparator as an enable signal at the subsequent stage of the comparator to shape the waveform of the input AC signal or A time constant circuit that starts charging with the power supply voltage by a signal from the input circuit,
A logic circuit that determines the level of the charging voltage of the time constant circuit and outputs a power-on reset signal when the level reaches a predetermined level. The power-on reset signal is output based on the reference voltage from the bandgap reference voltage generation circuit that can generate a constant voltage regardless of whether the power-on reset signal is accurate when the power supply voltage reaches a predetermined level. Can be generated, and after the power-on reset signal is generated, if the power supply voltage fluctuates within the allowable range, that is, is higher than the stable operation level of the circuit (microcomputer or the like) in order to lower the comparison level of the comparator. For example, a power-on reset signal can be prevented from being generated. Further, since a time constant circuit that uses the output of the comparator as an enable signal is provided at a stage subsequent to the comparator, it is possible to generate a power-on reset signal after the power supply voltage sufficiently exceeds the stable operation level of the circuit. There is an effect that can be.

As the time constant circuit, a charge pump comprising a switch for turning on and off by a signal from a receiving circuit or an input circuit for shaping an input AC signal and a capacitor into which electric charge is injected when the switch is turned on. Because the circuit is used, the charge pump circuit is charged according to the intensity, that is, the amplitude of the input AC signal,
There is an effect that the power-on reset signal can be output at an appropriate timing according to the rising speed of the power supply voltage.

Further, at the next stage of the power-on reset generation circuit, there is provided a reset pulse generation circuit which counts the clock signal from the clock generation circuit after the generation of the power-on reset signal and outputs a reset pulse when the count exceeds a predetermined number. Since it is provided, the reset pulse for the microcomputer or the like can be generated after the clock signal is reliably generated, and the malfunction of the microcomputer or the like can be prevented.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment. For example, in the above-described embodiment, the invention is provided next to the power-on reset generation circuit. A reset pulse generation circuit is provided which outputs a reset pulse when the clock signal is counted based on a signal formed by the power-on reset generation circuit and a predetermined number is counted. The reset pulse generation circuit is a data reception circuit. May be configured to count the pulses output from and output a reset pulse.

In the above description, a transceiver IC used in a non-contact type IC card of electromagnetic coupling, which is a field of application which is a background of the invention made mainly by the present inventors.
Has been described above, the present invention is not limited to this, and can be used in general for a power-on reset generation circuit in a semiconductor integrated circuit.

[0046]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a power-on reset signal can be accurately generated when the power supply voltage reaches a predetermined level, and a power-on reset signal that does not generate a power-on reset signal within a permissible range even when the power supply voltage fluctuates. An on-reset generation circuit can be realized.

[Brief description of the drawings]

FIG. 1 shows a transceiver I used for a non-contact type IC card having a power-on reset generation circuit according to the present invention.
It is a block diagram which shows the structure of C.

FIG. 2 is a circuit diagram showing an embodiment of a power-on reset generation circuit.

FIG. 3 is a waveform diagram showing a power supply voltage and a signal waveform of each part in the power-on reset generation circuit.

FIG. 4 is a circuit diagram showing a specific example of a power-on reset generation circuit of FIG. 2;

FIG. 5 is a circuit diagram showing a second embodiment of the power-on reset generation circuit.

FIG. 6 is a circuit diagram showing a third embodiment of the power-on reset generation circuit.

FIG. 7 is a circuit diagram showing a configuration example of a power-on reset generation circuit studied prior to the present invention.

[Explanation of symbols]

 L coil 1 Rectifier circuit 2 Voltage limiter circuit (constant voltage power supply circuit) 3 Power supply stabilization circuit 4 Power-on reset generation circuit 5 Reset pulse generation circuit 6 Data reception circuit 7 Data demodulation circuit 8 Clock generation circuit 9 Data transmission circuit 10 For transceiver Semiconductor integrated circuit 20 Microcomputer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Ogawara 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. Central Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. A resistor voltage dividing circuit for dividing a power supply voltage, a comparator for comparing a voltage divided by the voltage dividing circuit with a reference voltage, and a reference voltage input terminal of the comparator. An input resistor, a pull-down circuit including a series-connected resistor and a switch transistor connected between the reference voltage input terminal and the ground point, and a time constant circuit that gradually raises a voltage by the output of the comparator. A power-on reset generating circuit, wherein after the power-on reset signal is output, the pull-down circuit is operated to lower the voltage applied to the reference voltage input terminal of the comparator. 2. The power-on reset generation circuit according to claim 1, wherein said reference voltage is a voltage generated by a band gap reference voltage generation circuit. 3. A time constant circuit comprising: a capacitor; a first switch transistor for selectively injecting charge into the capacitor;
3. The power-on reset generation circuit according to claim 1, further comprising a second switch transistor for extracting the electric charge of the capacitance according to the output of the comparator. 4. A logic circuit for determining a charging voltage level of the time constant circuit and outputting a power-on reset signal when a predetermined level is reached is connected to a stage subsequent to the time constant circuit. The power-on reset generation circuit according to claim 1, 2 or 3. 5. An external terminal to which the electromagnetic coupling means is connected,
A rectifier circuit that rectifies the AC voltage input through the electromagnetic coupling means connected to the external terminal to form a DC voltage;
A constant voltage power supply circuit for forming a power supply voltage of a predetermined level from the voltage formed by the rectifier circuit, and a power-on reset signal is formed by detecting a rise of the power supply voltage generated by the constant voltage power supply circuit. An IC comprising the power-on reset generation circuit according to any one of claims 1 to 4.
Semiconductor integrated circuits for card transceivers. 6. A reset which starts counting a clock signal based on a signal formed by the power-on reset generation circuit at the next stage of the power-on reset generation circuit and outputs a reset pulse when a predetermined number is counted. The IC according to claim 5, further comprising a pulse generation circuit.
Semiconductor integrated circuits for card transceivers. 7. The transceiver according to claim 6, wherein the semiconductor integrated circuit for a transceiver, the electromagnetic coupling means connected to the semiconductor integrated circuit, and the microcomputer chip are mounted on a single card-shaped substrate. A reset pulse is supplied to the microcomputer chip based on a signal from a power-on reset generation circuit of the semiconductor integrated circuit, and the microcomputer chip is connected to an external device through the transceiver semiconductor integrated circuit. A non-contact IC card configured to transmit and receive data.