CN112769429A - Single event transient resistant buffer for low-level reset circuit - Google Patents
Single event transient resistant buffer for low-level reset circuit Download PDFInfo
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- CN112769429A CN112769429A CN202011555521.5A CN202011555521A CN112769429A CN 112769429 A CN112769429 A CN 112769429A CN 202011555521 A CN202011555521 A CN 202011555521A CN 112769429 A CN112769429 A CN 112769429A
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- level reset
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- 239000000872 buffer Substances 0.000 title claims abstract description 76
- 230000001052 transient effect Effects 0.000 title claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000002245 particle Substances 0.000 abstract description 18
- 238000010586 diagram Methods 0.000 description 5
- 230000002787 reinforcement Effects 0.000 description 5
- 238000010849 ion bombardment Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- LPLLVINFLBSFRP-UHFFFAOYSA-N 2-methylamino-1-phenylpropan-1-one Chemical compound CNC(C)C(=O)C1=CC=CC=C1 LPLLVINFLBSFRP-UHFFFAOYSA-N 0.000 description 1
- 240000003023 Cosmos bipinnatus Species 0.000 description 1
- 235000005956 Cosmos caudatus Nutrition 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
Abstract
The invention discloses a single-particle transient resistance buffer for a low-level reset circuit, which comprises a first-stage inverter circuit and a second-stage inverter circuit which are sequentially connected, wherein the first-stage inverter circuit comprises a first resistor and a first transistor, the second-stage inverter circuit comprises a second transistor and a second resistor, the grid electrode of the first transistor is connected with an input signal of the buffer, the drain electrode of the first transistor is respectively connected with the grid electrode of the second transistor and is connected with a power supply through the first resistor, the source electrode of the second transistor is connected with the power supply, and the drain electrode of the second transistor is respectively connected with an output signal end of the buffer and the second resistor. The invention can be used for a low-level reset circuit, simultaneously improves the single-particle transient resistance of the reset circuit, and reduces the influence of the single-particle transient generated by the reset circuit on a functional circuit.
Description
Technical Field
The invention relates to the technical field of CMOS integrated circuit reset circuits, in particular to a single-event transient resistance buffer for a low-level reset circuit.
Background
In the cosmos space, there are a large number of energetic particles (protons, electrons, heavy ions, etc.). After being bombarded by the high-energy particles, the integrated circuit can generate single-particle transient pulses. For example, when the single-event transient pulse is transmitted to a reset port of the time sequence unit, the time sequence unit adopts an asynchronous reset mode, and the time sequence unit can be immediately reset only by meeting the minimum pulse width of a reset signal, so that the data value stored by the time sequence unit is changed. Because the reset signal is a global signal, if a single-event transient pulse is generated at the root node of the reset circuit, the whole integrated circuit is reset, thereby causing errors. Single event transients have now become a major source of soft errors. Therefore, it is necessary to perform single event transient resistance reinforcement for the reset circuit.
CMOS integrated circuit reset circuits are typically formed by a CMOS buffer formed by a plurality of transistors which must be turned off when the CMOS buffer is in operation, and such off transistors are sensitive to particle bombardment. When the high energy particles bombard the transistors in the off state in the CMOS buffer, a single event transient occurs, and thus the CMOS buffer is more sensitive to the single event transient. As shown in fig. 1, the CMOS buffer at least includes 2 PMOS transistors and 2 NMOS transistors, and when the CMOS buffer operates and forms a low level reset circuit, at least 1 PMOS transistor and 1 NMOS transistor are in an off state, and the 2 transistors in the off state are sensitive to the heavy ion bombardment, which is a sensitive node. As shown in fig. 2, for the low level reset circuit, when the low level reset circuit is formed by the CMOS buffer shown in fig. 1, the CMOS buffer is activated to operate, when the input is at a high level, the transistor P1 and the transistor N2 are both in an off state, and when particles bombard the two transistors, a single-particle transient is generated, that is, the transistor P1 and the transistor N2 are sensitive nodes, which affects the stability of the circuit. Therefore, it is desirable to provide a Single-Event Transient (SET) resistant buffer for a low level reset circuit to improve the Single-Event Transient (SET) resistance of the low level reset circuit.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the single event transient resistant buffer for the low-level reset circuit, which has the advantages of simple structure and low cost, can improve the single event transient resistance of the reset circuit and reduce the influence of the single event transient generated by the reset circuit on the functional circuit.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
the utility model provides an anti single event transient buffer for low level reset circuit, is including the first order inverter circuit, the second order inverter circuit that connect gradually, the first order inverter circuit includes first resistance R1, first transistor N1, the second order inverter circuit includes second transistor P2, second resistance R2, the gate access of first transistor N1 the input signal of buffer, the drain electrode of first transistor N1 is connected respectively the gate of second transistor P2 and pass through first resistance R1 connects the power, the source connection power of second transistor P2, the drain electrode of second transistor P2 is connected respectively the output signal end of buffer and second resistance R2.
Further: when the input signal is in a high state, the first transistor N1 and the second transistor P2 are both in an open state.
Further: the first resistor R1 and/or the second resistor R2 are polysilicon resistors.
Further: the first transistor N1 is an NMOS transistor and the second transistor P2 is a PMOS transistor.
Further: the source of the first transistor N1 is grounded, and the drain of the second transistor P2 is grounded through the second resistor R2.
Further: the buffer comprises more than two stages, and the buffers at all stages are connected in series.
A low-level reset circuit comprises more than two stages of the buffers, wherein the buffers are sequentially connected in series.
Compared with the prior art, the invention has the advantages that:
1. the buffer for the low-level reset circuit is formed by using the resistor at the sensitive node position when the low-level reset is realized and keeping using the transistor at other nodes, so that the sensitive node sensitive to heavy ion bombardment in the buffer can be eliminated, the buffer has no sensitive node, and the single-particle transient-resistant reinforcement of the buffer of the low-level reset circuit is realized;
2. after the functional circuit works normally, the particle bombardment buffer circuit can not generate single-particle transient pulse, so that the normal work of the functional circuit can be ensured.
Drawings
Fig. 1 is a structure of a CMOS buffer in the prior art.
Fig. 2 is a schematic diagram of the sensitive node when the input is high in the CMOS buffer in the prior art.
Fig. 3 is a schematic structural diagram of the anti-single event transient buffer for the low level reset circuit according to the present embodiment.
Fig. 4 is a schematic diagram of a reset circuit formed by connecting a plurality of buffers.
FIG. 5 is a diagram of simulated waveforms for particle bombardment during testing of a low-level reset circuit constructed using conventional buffers in an exemplary embodiment.
FIG. 6 is a diagram of simulated waveforms of particle bombardment during testing of a low-level reset circuit constructed using the buffers of the present invention in an exemplary embodiment.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
As shown in fig. 3, the anti-single event transient buffer for the low level reset circuit of the present embodiment includes a first stage inverter circuit and a second stage inverter circuit, which are connected in sequence, where the first stage inverter circuit includes a first resistor R1 and a first transistor N1, the second stage inverter circuit includes a second transistor P2 and a second resistor R2, a gate of the first transistor N1 is connected to an input signal of the buffer, a drain of the first transistor N1 is connected to a gate of the second transistor P2, and is connected to a power supply VDD through the first resistor R1, a source of the second transistor P2 is connected to the power supply VDD, a drain of the second transistor P2 is connected to an output signal terminal of the buffer and the second resistor R2, and when the input signal is at a high level, both the first transistor N1 and the second transistor P2 are in an open state.
Since the reset circuit gives the circuit reset signal only when the functional circuit starts to work normally and then keeps outputting normally, the sensitive node in the reset circuit is fixed after the functional circuit starts to work. The present embodiment first determines the sensitive node in the low reset circuit buffer. As shown in fig. 2, when the low-level reset circuit is formed by the CMOS buffer shown in fig. 1, the CMOS buffer is activated, and when the input is high, the transistors P1 and N2 are turned off, and the transistors P1 and N2 are sensitive nodes. In the embodiment, after the sensitive node of the buffer for the low-level reset circuit is determined, the resistor is used at the sensitive node, and the transistors are kept at other nodes to form the buffer for the low-level reset circuit.
As shown in fig. 3, where the input is a, the output is Y, the power supply is VDD, the ground is GND, the buffer in this embodiment is formed by cascading two stages of inverter circuits, the first transistor N1 is an NMOS transistor, the second transistor P2 is a PMOS transistor, the first stage of inverter circuit 1 is composed of a first transistor N1 and a first resistor R1, the input is a, and the output is X0; the second-stage inverter circuit 2 is composed of a second resistor R2 and a second transistor P2, the input is X1, and the output is Y; the source of the first transistor N1 is grounded GND, the gate of the first transistor N1 is connected to the input signal a of the buffer, the drain of the first transistor N1 is connected to the gate of the second transistor P2 and the power supply VDD through the first resistor R1, the source of the second transistor P2 is connected to the power supply VDD, and the drain of the second transistor P2 is connected to the output signal terminal Y of the buffer and the GND through the second resistor R2. In the present embodiment, when the input of the buffer is in a high level state, the first transistor N1 and the second transistor P2 are both in an open state, and there is no single event transient sensitive node, so that the buffer can be used in a low level reset circuit to implement the single event transient resistance reinforcement of the reset buffer.
In this embodiment, the first resistor R1 and the second resistor R2 specifically adopt polysilicon resistors. The polysilicon resistor has good stability and high precision, can further improve the single-particle transient resistance of the buffer by using the polysilicon resistor at the sensitive node of the buffer unit, and is more suitable for engineering application.
In order to construct the buffer, in a specific application embodiment, a first-stage inverter circuit can be constructed by using 1 NMOS transistor N1 and 1 polysilicon resistor R1, wherein the source of the NMOS transistor N1 is grounded, the drain is connected to the output, and the gate is connected to the input, one end of the polysilicon resistor R1 is connected to the power supply, and the other end is connected to the output; then, a second-stage inverter is constructed by using 1 PMOS transistor P2 and 1 polysilicon resistor R2, wherein the source electrode of the PMOS transistor P2 is connected with a power supply, the drain electrode of the PMOS transistor P2 is connected with an output, and the grid electrode of the PMOS transistor P3526 is connected with an input, one end of the polysilicon resistor R2 is grounded, and the other end of the polysilicon resistor R2 is connected with the output; the output of the first-stage inverter circuit 1 is connected to the input of the second-stage inverter circuit 2, that is, a buffer required for a low-level reset circuit is constructed, the input of the first-stage inverter circuit 1 is the input of the buffer, and the output of the second-stage inverter circuit 2 is the output of the buffer. The buffer has no single-event transient sensitive node, and can realize the single-event transient resistance reinforcement of the reset buffer.
In this embodiment, the reset circuit may further include more than two stages of buffers, and as shown in fig. 4, the reset circuit is formed by cascading 99 stages of buffers, where the input of the 1 st stage of buffer is a 1 node, and the output is a 2 node; the input of the 2 nd-level buffer is 2 nodes, and the output is 3 nodes; and so on.
To verify the effectiveness of the present invention, a low level reset circuit is constructed in the same connection manner as fig. 4 using a conventional buffer as shown in fig. 1 in a specific application embodiment, and the function of the low level reset circuit is verified. When the functional circuit works normally, the low level reset circuit inputs high level and outputs high level; the N2 transistor of the reset circuit buffer1 is bombarded by simulated particles of an exponential current source, a SET pulse of 10ns is injected, and the SET pulse continuously propagates, so that the functional circuit is reset, and further the functional circuit is in error. The SPICE simulation waveform obtained in the specific application embodiment is shown in fig. 5, wherein v (1) represents the voltage waveform of the input node of buffer1, v (2) represents the voltage waveform of the output node of buffer1, v (3) represents the voltage waveform of the output node of buffer2, and v (100) represents the voltage waveform of the output node of buffer 99.
This embodiment also adopts the buffer structure of the present invention as shown in fig. 3 and configures a reset circuit in a connection manner as shown in fig. 4, and verifies the function of the reset circuit. When the functional circuit works normally, the reset circuit inputs a high level and outputs a high level, and since the buffer of the present invention has two transistors (transistor N1 and transistor P2) in an on state at this input, and there is no sensitive node, when the P2 transistor of the reset circuit buffer1 is bombarded by analog particles through an exponential current source, although the output voltage v (2) of the buffer1 is pulled high, it is still high, and the pulse of v (2) cannot propagate continuously, as shown in fig. 6. As can be seen from FIG. 6, the low-level reset circuit buffer circuit of the present invention has single-event transient immunity and single-event transient reinforcement resistance.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (7)
1. A single event transient (SEU) resistant buffer for a low level reset circuit, comprising: including the first order inverter circuit, the second order inverter circuit that connect gradually, the first order inverter circuit includes first resistance R1, first transistor N1, the second order inverter circuit includes second transistor P2, second resistance R2, first transistor N1's gate access the input signal of buffer, first transistor N1's drain is connected respectively the gate of second transistor P2 and pass through first resistance R1 connects the power, the source connection power of second transistor P2, the drain of second transistor P2 is connected respectively the output signal end of buffer and second resistance R2.
2. The single event transient resistant buffer for a low level reset circuit of claim 1, wherein: when the input signal is in a high state, the first transistor N1 and the second transistor P2 are both in an open state.
3. The single event transient resistant buffer for a low level reset circuit of claim 1, wherein: the first resistor R1 and/or the second resistor R2 are polysilicon resistors.
4. The single event transient resistant buffer for a low level reset circuit of claim 1, wherein: the first transistor N1 is an NMOS transistor and the second transistor P2 is a PMOS transistor.
5. The single event transient resistant buffer for a low level reset circuit of claim 1, wherein: the source of the first transistor N1 is grounded, and the drain of the second transistor P2 is grounded through the second resistor R2.
6. The single event transient resistant buffer for a low level reset circuit according to any one of claims 1 to 5, wherein: the buffer comprises more than two stages, and the buffers at all stages are connected in series.
7. A low level reset circuit, comprising: the buffer of any one of claims 1 to 6 comprising more than two stages, the stages being connected in series in sequence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011555521.5A CN112769429A (en) | 2020-12-24 | 2020-12-24 | Single event transient resistant buffer for low-level reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011555521.5A CN112769429A (en) | 2020-12-24 | 2020-12-24 | Single event transient resistant buffer for low-level reset circuit |
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| CN112769429A true CN112769429A (en) | 2021-05-07 |
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| CN202011555521.5A Pending CN112769429A (en) | 2020-12-24 | 2020-12-24 | Single event transient resistant buffer for low-level reset circuit |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5307142A (en) * | 1991-11-15 | 1994-04-26 | The United States Of America As Represented By The United States Department Of Energy | High performance static latches with complete single event upset immunity |
| US6275433B1 (en) * | 2000-08-30 | 2001-08-14 | Micron Technology, Inc. | Four transistor SRAM cell with improved read access |
| US20020131294A1 (en) * | 2001-03-15 | 2002-09-19 | Micron Technology, Inc. | SRAM cell with horizontal merged devices |
| US20060109036A1 (en) * | 2004-11-25 | 2006-05-25 | Po-Chin Hsu | Power-low reset circuit |
| US20060119379A1 (en) * | 2004-12-02 | 2006-06-08 | Honeywell International Inc. | Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions |
| CN101622704A (en) * | 2008-02-06 | 2010-01-06 | 松下电器产业株式会社 | Semiconductor device and method for resetting the same |
| US7688117B1 (en) * | 2008-04-21 | 2010-03-30 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | N channel JFET based digital logic gate structure |
| JP2016082501A (en) * | 2014-10-21 | 2016-05-16 | 株式会社デンソー | Power-on reset circuit |
| CN107342762A (en) * | 2017-05-31 | 2017-11-10 | 北京时代民芯科技有限公司 | A kind of anti-single particle transient state clock tree construction |
-
2020
- 2020-12-24 CN CN202011555521.5A patent/CN112769429A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5307142A (en) * | 1991-11-15 | 1994-04-26 | The United States Of America As Represented By The United States Department Of Energy | High performance static latches with complete single event upset immunity |
| US6275433B1 (en) * | 2000-08-30 | 2001-08-14 | Micron Technology, Inc. | Four transistor SRAM cell with improved read access |
| US20020131294A1 (en) * | 2001-03-15 | 2002-09-19 | Micron Technology, Inc. | SRAM cell with horizontal merged devices |
| US20060109036A1 (en) * | 2004-11-25 | 2006-05-25 | Po-Chin Hsu | Power-low reset circuit |
| US20060119379A1 (en) * | 2004-12-02 | 2006-06-08 | Honeywell International Inc. | Single event upset hardened circuitry without sensitivity to overshoot and/or undershoot conditions |
| CN101622704A (en) * | 2008-02-06 | 2010-01-06 | 松下电器产业株式会社 | Semiconductor device and method for resetting the same |
| US7688117B1 (en) * | 2008-04-21 | 2010-03-30 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | N channel JFET based digital logic gate structure |
| JP2016082501A (en) * | 2014-10-21 | 2016-05-16 | 株式会社デンソー | Power-on reset circuit |
| CN107342762A (en) * | 2017-05-31 | 2017-11-10 | 北京时代民芯科技有限公司 | A kind of anti-single particle transient state clock tree construction |
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Application publication date: 20210507 |