CN114301428A - Latch circuit - Google Patents

Abstract

The present invention relates to a latch circuit. The method comprises the following steps: the transmission module comprises a first output end and a second output end, wherein the first output end is used for outputting a first signal in a first level state according to an input signal, the second output end is used for outputting a second signal in a second level state according to the input signal, and the first level state and the second level state are different; the output module is respectively connected with the first output end and the second output end and is used for generating an output signal according to the first signal and the second signal; and the feedback control module is respectively connected with the output end of the output module, the first output end and the second output end and is used for controlling the level state of the first output end to be the first level state and controlling the level state of the second output end to be the second level state according to the output signal, the first signal and the second signal.

Description

Latch circuit

Technical Field

The present invention relates to the field of integrated circuit design, and more particularly, to a latch circuit.

Background

As the feature size of integrated circuits continues to decrease, the supply voltage and logic gate node capacitance also continue to decrease, and the circuits become more and more sensitive to radiation. The reduction in the supply voltage and node capacitance results in a reduction in the amount of charge stored on the node, making the circuit susceptible to radiation-induced soft errors. When an energetic particle, such as an alpha or neutron, hits an off-state transistor in the timing circuit, it will disturb the logic value stored at the node to its complement. This phenomenon occurring in sequential logic circuits is called Single Event Upset (SEU).

The intermediate nodes as well as the output nodes of conventional CMOS latch circuits are very sensitive to radiation effects. When an energetic particle strikes any of the sensitive nodes described above, the logical value of the strike node may change to its complement. Due to the circuit structure of the latch, the logic level change of any sensitive node will be transferred to another node through a feedback path between two inverters, thereby causing the wrong logic to pass and finally affecting the output logic value of the latch.

The amount of charge that an energetic particle deposits in a sensitive node and causes a single event upset is called the critical charge. The critical charge depends on the capacitance of the node and the supply voltage of the circuit. These two parameters decrease as the scale of integrated circuit technology increases, and therefore the critical charge of the sensitive node also gradually decreases. Thus, a lower energy particle striking a sensitive node may cause a single event upset. A typical technique for SEU hardening latches is triple modular redundancy latch (TMR), in which three parallel latches and a voter circuit are used to eliminate the problem of single event upsets. However, although TMR can completely prevent the occurrence of single event upset events, this technique results in higher power consumption, larger area overhead, and higher latency. Moreover, the triple modular redundancy latch only has nodes inside the three latches which are completely immune to SEU, and when high-energy particles bombard the voter circuit, single event upset can still occur. Therefore, how to reduce the power consumption, the time delay and the area overhead as much as possible on the basis of keeping the SEU immunity becomes an urgent problem to be solved.

Disclosure of Invention

Accordingly, there is a need for a latch circuit that eliminates single event upsets at each node in the latch circuit and reduces power consumption of the latch circuit.

The present application provides a latch circuit, comprising:

the transmission module comprises a first output end and a second output end, wherein the first output end is used for outputting a first signal in a first level state according to an input signal, the second output end is used for outputting a second signal in a second level state according to the input signal, and the first level state and the second level state are different;

the output module is respectively connected with the first output end and the second output end and is used for generating an output signal according to the first signal and the second signal;

and the feedback control module is respectively connected with the output end of the output module, the first output end and the second output end and is used for controlling the level state of the first output end to be the first level state and controlling the level state of the second output end to be the second level state according to the output signal, the first signal and the second signal.

In one embodiment, the transmission module comprises:

the input end of the first transmission circuit is used for receiving the input signal, and the output end of the first transmission circuit is the first output end and is used for outputting a first signal in a first level state according to the input signal under the control of a control signal;

and the input end of the second transmission circuit is used for receiving the input signal, and the output end of the second transmission circuit is the second output end and is used for outputting a second signal in a second level state according to the input signal under the control of the control signal.

In one embodiment, the first transmission circuit includes:

the input end of the first transmission gate is used for receiving the input signal, the controlled end of the first transmission gate is used for receiving the control signal, and the output end of the first transmission gate is the first output end.

In one embodiment, the second transmission circuit includes:

a second transmission gate, an input terminal of which is used for receiving the input signal, and a controlled terminal of which is used for receiving the control signal;

and the input end of the phase inverter is connected with the output end of the second transmission gate, and the output end of the phase inverter is the second output end.

In one embodiment, the output module comprises:

a first pull-up circuit, a first end of the first pull-up circuit being connected to the first output terminal, a second end of the first pull-up circuit being connected to the second output terminal;

and a first end of the first pull-down circuit is connected with the first output end, a second end of the first pull-down circuit is connected with the second output end, and a third end of the first pull-down circuit is connected with a third end of the first pull-up circuit so as to output the output signal together.

In one embodiment, the first pull-up circuit includes:

a first transistor, a first end of which is connected to a power supply voltage, and a control end of which is connected to the second output end;

and a first end of the second transistor is connected with a second end of the first transistor, a control end of the second transistor is connected with the first output end, and a second end of the second transistor is a third end of the first pull-up circuit.

In one embodiment, the first pull-down circuit includes:

a third transistor, a first end of the third transistor being a third end of the first pull-down circuit, a control end of the third transistor being connected to the first output end;

a first end of the fourth transistor is connected to the second end of the third transistor, a control end of the fourth transistor is connected to the second output end, and a second end of the fourth transistor is grounded.

In one embodiment, the feedback control module comprises:

the first feedback circuit is respectively connected with the output end of the output module, the second output end and the first output end, and is used for controlling the level state of the first output end to be the first level state according to the output signal and the second signal;

and the second feedback circuit is respectively connected with the output end of the output module, the first output end and the second output end and is used for controlling the level state of the second output end to be the second level state according to the output signal and the first signal.

In one embodiment, the first feedback circuit comprises:

a first end of the second pull-up circuit is connected with the second output end, a second end of the second pull-up circuit is connected with the output end of the output module, and a third end of the second pull-up circuit is connected with the first output end;

and the first end of the second pull-down circuit is connected with the second output end, the second end of the second pull-down circuit is connected with the output end of the output module, and the third end of the second pull-down circuit is connected with the first output end.

In one embodiment, the second feedback circuit comprises:

a first end of the third pull-up circuit is connected with the first output end, a second end of the third pull-up circuit is connected with the output end of the output module, and a third end of the third pull-up circuit is connected with the second output end;

and the first end of the third pull-down circuit is connected with the first output end, the second end of the third pull-down circuit is connected with the output end of the output module, and the third end of the third pull-down circuit is connected with the second output end.

In the latch circuit, the first output end of the transmission module outputs a first signal in a first level state according to an input signal, the second output end outputs a second signal in a second level state according to the input signal, the output module generates an output signal according to the first signal and the second signal, the feedback control module controls the level state of the first output end to be in the first level state and controls the level state of the second output end to be in the second level state according to the output signal, the first signal and the second signal, the influence of single event upset on the first output end, the second output end and the output end of the output module is eliminated, the function of preventing the single event upset of an internal node of the latch circuit is achieved, the circuit structure is simple, and the power consumption of the circuit is low.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of a latch circuit in embodiment 1;

FIG. 2 is a block diagram of a latch circuit in embodiment 2;

FIG. 3 is a diagram illustrating a latch circuit according to embodiment 1;

FIG. 4 is a diagram showing a latch circuit in the embodiment of FIG. 2;

FIG. 5 is a diagram illustrating a latch circuit according to embodiment 3;

FIG. 6 is a diagram illustrating a latch circuit according to embodiment 4;

FIG. 7 is a diagram showing a latch circuit in the embodiment of FIG. 5;

FIG. 8 is a diagram illustrating a latch circuit according to embodiment 6.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first output may be referred to as a second output, and similarly, a second output may be referred to as a first output, without departing from the scope of the present application. Both the first output and the second output are outputs of the transmission module, but they are not the same output.

It is to be understood that "connection" in the following embodiments is to be understood as "electrical connection", "communication connection", and the like if the connected circuits, modules, units, and the like have communication of electrical signals or data with each other.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 is a block diagram illustrating a latch circuit in embodiment 1, and as shown in fig. 1, in this embodiment, a latch circuit is provided, which includes: a transmission module 102, an output module 104, and a feedback control module 106.

A transmission module 102, including a first output terminal 1 and a second output terminal 2, where the first output terminal 1 is configured to output a first signal in a first level state according to an input signal D, and the second output terminal 2 is configured to output a second signal in a second level state according to the input signal D, where the first level state and the second level state are different; the level state is divided into a high level state and a low level state, where the first level state and the second level state are different, and the first level state is the high level state, the second level state is the low level state, and the first level state is the low level state, the second level state is the high level state.

The output module 104 is respectively connected to the first output terminal 1 and the second output terminal 2, and is configured to generate an output signal Q according to the first signal and the second signal.

The feedback control module 106 is connected to the output terminal 3 of the output module 104, the first output terminal 1, and the second output terminal 2, and configured to control the level state of the first output terminal 1 to be the first level state and control the level state of the second output terminal 2 to be the second level state according to the output signal Q, the first signal, and the second signal.

In the latch circuit, the first output end of the transmission module outputs a first signal in a first level state according to an input signal, the second output end outputs a second signal in a second level state according to the input signal, the output module generates an output signal according to the first signal and the second signal, the feedback control module controls the level state of the first output end to be in the first level state and controls the level state of the second output end to be in the second level state according to the output signal, the first signal and the second signal, the influence of single event upset on the first output end, the second output end and the output end of the output module is eliminated, the function of preventing the single event upset of an internal node of the latch circuit is achieved, the circuit structure is simple, and the power consumption of the circuit is low.

Fig. 2 is a block diagram of a latch circuit in embodiment 2. as shown in fig. 2, in one embodiment, the transmission module 102 includes: a first transmission circuit 202 and a second transmission circuit 204; an input end of the first transmission circuit 202 is configured to receive the input signal D, an output end of the first transmission circuit 202 is the first output end 1, and the first transmission circuit 202 is configured to output a first signal in a first level state according to the input signal D under the control of a control signal; the input end of the second transmission circuit 204 is configured to receive the input signal D, the output end of the second transmission circuit 204 is the second output end 2, and the second transmission circuit 204 is configured to output a second signal in a second level state according to the input signal D under the control of the control signal.

Fig. 3 is a schematic diagram of the latch circuit in embodiment 1, and as shown in fig. 3, in one embodiment, the first transmission circuit 202 includes a first transmission gate, an input end of the first transmission gate is used for receiving the input signal D, controlled ends CLKB and CLK of the first transmission gate are used for receiving the control signal, and an output end of the first transmission gate is the first output end 1. When the controlled terminal CLKB receives the control signal "1" and the controlled terminal CLK receives the control signal "0", the first transmission gate is opened, and the first signal in the first level state is output according to the input signal D, and when the controlled terminal CLKB receives the control signal "0" and the controlled terminal CLK receives the control signal "1", the first transmission gate is closed.

As shown in fig. 3, in one embodiment, the second transmission circuit 204 includes a second transmission gate 302 and an inverter 304, an input terminal of the second transmission gate 302 is configured to receive the input signal D, and a controlled terminal of the second transmission gate 302 is configured to receive the control signal; the input end of the inverter 304 is connected to the output end of the second transmission gate 302, and the output end of the inverter 304 is the second output end 2. The controlled terminals CLKB and CLK of the second transmission gate 302 are configured to receive the control signal, when the controlled terminal CLKB receives the control signal "1" and the controlled terminal CLK receives the control signal "0", the second transmission gate 302 is opened, a signal in a first level state is output to the inverter 304 according to the input signal D, the inverter 304 outputs a second signal in a second level state according to the received signal in the first level state, and when the controlled terminal CLKB receives the control signal "0" and the controlled terminal CLK receives the control signal "1", the second transmission gate 302 is turned off, wherein the first transmission gate and the second transmission gate receive the same control signal at the same time, that is, the first transmission gate and the second transmission gate are opened and turned off at the same time.

Fig. 4 is a schematic diagram of a latch circuit in embodiment 2. as shown in fig. 4, in one embodiment, the output module 104 includes: a first pull-up circuit 206 and a first pull-down circuit 208; a first terminal of the first pull-up circuit 206 is connected to the first output terminal 1, and a second terminal of the first pull-up circuit 206 is connected to the second output terminal 2; a first terminal of the first pull-down circuit 208 is connected to the first output terminal 1, a second terminal of the first pull-down circuit 208 is connected to the second output terminal 2, and a third terminal of the first pull-down circuit 208 is connected to a third terminal of the first pull-up circuit 206, so as to output the output signal Q in common.

Fig. 5 is a schematic diagram of the latch circuit in embodiment 3. as shown in fig. 5, in one embodiment, the first pull-up circuit 206 includes a first transistor 306 and a second transistor 308, and a first terminal of the first transistor 206 is connected to a power supply voltage V1, wherein the power supply voltage V1 is such that the output terminal Q is at a high level when both the first transistor 306 and the second transistor 308 are turned on, and at a low level when both the first transistor 306 and the second transistor 308 are turned off. The control terminal of the first transistor 306 is connected to the second output terminal 2; a first terminal of the second transistor 308 is connected to the second terminal of the first transistor 306, a control terminal of the second transistor 308 is connected to the first output terminal 1, and a second terminal of the second transistor 308 is the third terminal of the first pull-up circuit 206.

In one embodiment, the first transistor 306 is a first PMOS transistor, the second transistor 308 is a first NMOS transistor, and at this time, a source of the first PMOS transistor is a first end of the first transistor 306, a gate of the first PMOS transistor is a control end of the first transistor 306, and a drain of the first PMOS transistor is a second end of the first transistor 306; the drain of the first NMOS transistor is the first end of the second transistor 308, the gate of the first NMOS transistor is the control end of the second transistor 308, and the source of the first NMOS transistor is the second end of the second transistor 308.

As shown in fig. 5, in one embodiment, the first pull-down circuit 208 includes a third transistor 310 and a fourth transistor 312, a first terminal of the third transistor 310 is a third terminal of the first pull-down circuit 208, and a control terminal of the third transistor 310 is connected to the first output terminal 1; a first terminal of the fourth transistor 312 is connected to the second terminal of the third transistor 310, a control terminal of the fourth transistor 312 is connected to the second output terminal 2, and a second terminal of the fourth transistor 312 is grounded.

In one embodiment, the third transistor 310 is a second PMOS transistor, the fourth transistor 312 is a second NMOS transistor, and at this time, the source of the second PMOS transistor is the first end of the third transistor 310, the gate of the second PMOS transistor is the control end of the third transistor 310, and the drain of the second PMOS transistor is the second end of the third transistor 310; the drain of the second NMOS transistor is the first end of the fourth transistor 312, the gate of the second NMOS transistor is the control end of the fourth transistor 312, and the source of the second NMOS transistor is the second end of the fourth transistor 312.

Fig. 6 is a schematic diagram of a latch circuit in embodiment 4. as shown in fig. 6, in one embodiment, the feedback control module 106 includes: the first feedback circuit 210 is connected to the output terminal 3 of the output module 104, the second output terminal 2, and the first output terminal 1, and is configured to control a level state of the first output terminal 1 to be the first level state according to the output signal Q and the second signal; the second feedback circuit 212 is respectively connected to the output terminal 3 of the output module 104, the first output terminal 1, and the second output terminal 2, and is configured to control the level state of the second output terminal 2 to be the second level state according to the output signal Q and the first signal. That is, the first feedback circuit 210 locks the level state of the first output terminal 1 to the first level state according to the output signal Q and the second signal, and the second feedback circuit 212 locks the level state of the second output terminal 2 to the second level state according to the output signal Q and the second signal, so as to achieve the purpose of anti-single event upset.

Fig. 7 is a schematic diagram of a latch circuit in embodiment 5. as shown in fig. 7, in one embodiment, the first feedback circuit 210 includes: a second pull-up circuit 314 and a second pull-down circuit 316, wherein a first terminal of the second pull-up circuit 314 is connected to the second output terminal 2, a second terminal of the second pull-up circuit 314 is connected to the output terminal 3 of the output module 104, and a third terminal of the second pull-up circuit 314 is connected to the first output terminal 1; a first end of the second pull-down circuit 316 is connected to the second output terminal 2, a second end of the second pull-down circuit 316 is connected to the output terminal 3 of the output module 104, and a third end of the second pull-down circuit 316 is connected to the first output terminal 1.

As shown in fig. 7, in one embodiment, the second feedback circuit 212 includes: a third pull-up circuit 318 and a third pull-down circuit 320, wherein a first terminal of the third pull-up circuit 318 is connected to the first output terminal 1, a second terminal of the third pull-up circuit 318 is connected to the output terminal 3 of the output module 104, and a third terminal of the third pull-up circuit 318 is connected to the second output terminal 2; the first end of the third pull-down circuit 320 is connected to the first output terminal 1, the second end of the third pull-down circuit 320 is connected to the output terminal 3 of the output module 104, and the third end of the third pull-down circuit 320 is connected to the second output terminal 2.

Fig. 8 is a schematic diagram of a latch circuit in the embodiment 6. as shown in fig. 8, in one embodiment, the second pull-up circuit 314 includes a fifth transistor 402 and a sixth transistor 404, a first terminal of the fifth transistor 402 is connected to a power supply voltage V2, wherein the power supply voltage V2 is such that when the fifth transistor 402 and the sixth transistor 404 are both turned on, the first output terminal 1 is locked to a high state, and when the fifth transistor 402 and the sixth transistor 404 are turned off, the first output terminal 1 is locked to a low state. The control terminal of the fifth transistor 402 is connected to the second output terminal 2; a first terminal of the sixth transistor 404 is connected to the second terminal of the fifth transistor 402, a control terminal of the sixth transistor 404 is connected to the output terminal 3 of the output module 104, and a second terminal of the sixth transistor 404 is connected to the first output terminal 1.

In one embodiment, the fifth transistor 402 is a third PMOS transistor, the sixth transistor 404 is a third NMOS transistor, and at this time, a source of the third PMOS transistor is a first end of the fifth transistor 402, a gate of the third PMOS transistor is a control end of the fifth transistor 402, and a drain of the third PMOS transistor is a second end of the fifth transistor 402; the drain of the third NMOS transistor is the first end of the sixth transistor 404, the gate of the third NMOS transistor is the control end of the sixth transistor 404, and the source of the third NMOS transistor is the second end of the sixth transistor 404.

As shown in fig. 8, in one embodiment, the second pull-down circuit 316 includes a seventh transistor 406 and an eighth transistor 408, a first terminal of the seventh transistor 406 is connected to the first output terminal 1, and a control terminal of the seventh transistor 406 is connected to the output terminal 3 of the output module 104; a first terminal of the eighth transistor 408 is connected to the second terminal of the seventh transistor 406, a control terminal of the eighth transistor 408 is connected to the second output terminal 2, and a second terminal of the eighth transistor 408 is grounded.

In one embodiment, the seventh transistor 406 is a fourth PMOS transistor, the eighth transistor 408 is a fourth NMOS transistor, and at this time, the source of the fourth PMOS transistor is the first end of the seventh transistor 406, the gate of the fourth PMOS transistor is the control end of the seventh transistor 406, and the drain of the fourth PMOS transistor is the second end of the seventh transistor 406; the drain of the fourth NMOS transistor is the first end of the eighth transistor 408, the gate of the fourth NMOS transistor is the control end of the eighth transistor 408, and the source of the fourth NMOS transistor is the second end of the eighth transistor 408.

As shown in fig. 8, in one embodiment, the third pull-up circuit 318 includes a ninth transistor 410 and a tenth transistor 412, and the first terminal of the ninth transistor 410 is connected to a power voltage V3, wherein the power voltage V3 is such that the second output terminal 2 is locked to a high state when both the ninth transistor 410 and the tenth transistor 412 are turned on, and the second output terminal 2 is locked to a low state when both the ninth transistor 410 and the tenth transistor 412 are turned off. The control terminal of the ninth transistor 410 is connected to the output terminal 3 of the output module 104; a first terminal of the tenth transistor 412 is connected to the second terminal of the ninth transistor 410, a control terminal of the tenth transistor 412 is connected to the first output terminal 1, and a second terminal of the tenth transistor 412 is connected to the second output terminal 2.

In one embodiment, the ninth transistor 410 is a fourth PMOS transistor, the ninth transistor 410 is a fifth PMOS transistor, and at this time, a source of the fourth PMOS transistor is a first end of the ninth transistor 410, a gate of the fourth PMOS transistor is a control end of the ninth transistor 410, and a drain of the fourth PMOS transistor is a second end of the ninth transistor 410; the source of the fifth PMOS transistor is the first end of the tenth transistor 412, the gate of the fifth PMOS transistor is the control end of the tenth transistor 412, and the drain of the fifth PMOS transistor is the second end of the tenth transistor 412.

As shown in fig. 8, in one embodiment, the third pull-down circuit 320 includes an eleventh transistor 414 and a twelfth transistor 416, a first terminal of the eleventh transistor 414 is connected to the second output terminal 2, and a control terminal of the eleventh transistor 414 is connected to the first output terminal 1; a first end of the twelfth transistor 416 is connected to the second end of the eleventh transistor 414, a control end of the twelfth transistor 416 is connected to the output end 3 of the output module 104, and a second end of the twelfth transistor 416 is grounded.

In one embodiment, the eleventh transistor 414 is a fifth NMOS transistor, the twelfth transistor 416 is a sixth NMOS transistor, in which case, a drain of the fifth NMOS transistor is a first end of the eleventh transistor 414, a gate of the fifth NMOS transistor is a control end of the eleventh transistor 414, and a source of the fifth NMOS transistor is a second end of the eleventh transistor 414; the drain of the sixth NMOS transistor is the first end of the twelfth transistor 416, the gate of the sixth NMOS transistor is the control end of the twelfth transistor 416, and the source of the sixth NMOS transistor is the second end of the twelfth transistor 416.

Taking fig. 8 as an example, the operation of the latch circuit is described below, when CLK is equal to "1" and CLKB is equal to "0", the latch circuit of the present invention is in a transparent state, the first transmission gate and the second transmission gate 302 are in a conducting state, the logic values (level states) of the first signal at the first output terminal 1 and the second signal at the second output terminal 2 are a set of complementary signals (a high level state and a low level state, respectively), the first signal and the second signal directly act on the output module 104, and the input signal D is transmitted to the output terminal 3 of the output module 104, so as to obtain the output signal Q. At this time, only the pull-up circuit or the pull-down circuit of the first feedback circuit 210 and the second feedback circuit 212 is turned on, that is, one of the first feedback circuit 210 and the second feedback circuit 212 is turned on, and the other is turned on, so as to prevent the influence of the external environment on the first output terminal 1 and the second output terminal 2, there is no path from the power supply (V2, V3) to the ground, and the purpose of reducing the overall power consumption of the latch circuit can be achieved. When CLK is equal to "0" and CLKB is equal to "1", the latch circuit of the present invention is in a latch state, the first transmission gate and the second transmission gate 302 are turned off, the first output terminal 1 and the second output terminal 2 are disconnected from the input signal D, and since a cross feedback loop is formed between the output terminal 3 of the output module 104 and the first output terminal 1 and the second output terminal 2 through the first feedback circuit 210 and the second feedback circuit 212, the first output terminal 1 and the second output terminal 2 continue to maintain the previous level state, and the output signal Q at the output terminal 3 of the output module 104 is determined by the output module 104. The principle of the latch circuit for resisting single event upset is as follows:

when the logic value latched by the latch circuit is "1" (the input signal D is at a high level), that is, the logic value of the first output terminal 1 is "1" (the level state of the first output terminal 1 is at a high level state), and the logic value of the second output terminal 2 is "0" (the level state of the second output terminal 2 is at a low level state), the logic value of the output terminal 3 of the output module 104 is "1", if a single event upset occurs in the first output terminal 1, that is, the logic state of the first output terminal 1 changes from "1" to "0", due to the time delay of the logic state, the change in the logic state of the first output terminal 1 does not affect the logic state of the output terminal 3, the fifth transistor 402 and the sixth transistor 404 are turned on, the connection point of the first feedback circuit 210 and the first output terminal 1 is pulled up to be at the logic value "1", and therefore, the logic state of the first output terminal 1 is also restored to be "1", the effect of a single event upset on the first output 1 is eliminated.

Similarly, when the logic value latched by the latch circuit is "1", that is, the logic value of the first output terminal 1 is "1", and the logic value of the second output terminal 2 is "0", the logic value of the output terminal 3 of the output module 104 is "1", and if a single event upset occurs in the second output terminal 2, that is, the logic state of the second output terminal 2 is changed from "0" to "1", at this time, the logic value of the output terminal 3 is "1", the eleventh transistor 414 and the twelfth transistor 416 are turned on, and the connection point of the second feedback circuit 212 and the second output terminal 2 is pulled down to be a logic value "0", so that the logic state of the second output terminal 2 is also restored to "0", and the influence of the single event upset of the second output terminal 2 is eliminated.

When the logic value latched by the latch circuit is "0", that is, the logic value of the first output terminal 1 is "0", and the logic value of the second output terminal 2 is "1", the logic value of the output terminal 3 of the output module 104 is "0", and if a single event upset occurs in the first output terminal 1, that is, the logic state of the first output terminal 1 is changed from "0" to "1", at this time, the logic value of the output terminal 3 of the output module 104 is "0", the seventh transistor 406 and the eighth transistor 408 are turned on, and the connection point of the first feedback circuit 210 and the first output terminal 1 is pulled down to be "0", so that the logic state of the first output terminal 1 is also restored to "0".

When the logic value latched by the latch circuit is "0", that is, the logic value of the first output terminal 1 is "0", and the logic value of the second output terminal 2 is "1", the logic value of the output terminal 3 of the output module 104 is "0", and if a single event upset occurs at the second output terminal 2, that is, the logic state of the second output terminal 2 is changed from "1" to "0", at this time, the logic value of the output terminal 3 of the output module 104 is "0", the ninth transistor 410 and the tenth transistor 412 are turned on, and the connection point of the second feedback circuit 212 and the second output terminal 2 is pulled up to the logic value "1", so that the logic state of the second output terminal 2 is also restored to "1".

When the output terminal 3 of the output module 104 is subjected to a single event upset, since the logic states of the first output terminal 1 and the second output terminal 2 are determined, the logic value of the output terminal 3 is always kept in a correct state through the output module 104. The single event upset resistance function of each node in the latch circuit can be completely realized, the circuit structure is simple, and the power consumption, the time delay and the area overhead can be effectively reduced.

The present application also provides an electronic device including the latch circuit described in any one of the above.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A latch circuit, comprising:

the transmission module comprises a first output end and a second output end, wherein the first output end is used for outputting a first signal in a first level state according to an input signal, the second output end is used for outputting a second signal in a second level state according to the input signal, and the first level state and the second level state are different;

the output module is respectively connected with the first output end and the second output end and is used for generating an output signal according to the first signal and the second signal;

and the feedback control module is respectively connected with the output end of the output module, the first output end and the second output end and is used for controlling the level state of the first output end to be the first level state and controlling the level state of the second output end to be the second level state according to the output signal, the first signal and the second signal.

2. The latch circuit according to claim 1, wherein the transmission module comprises:

the input end of the first transmission circuit is used for receiving the input signal, and the output end of the first transmission circuit is the first output end and is used for outputting a first signal in a first level state according to the input signal under the control of a control signal;

and the input end of the second transmission circuit is used for receiving the input signal, and the output end of the second transmission circuit is the second output end and is used for outputting a second signal in a second level state according to the input signal under the control of the control signal.

3. The latch circuit according to claim 2, wherein the first transmission circuit comprises:

the input end of the first transmission gate is used for receiving the input signal, the controlled end of the first transmission gate is used for receiving the control signal, and the output end of the first transmission gate is the first output end.

4. The latch circuit according to claim 2, wherein the second transmission circuit comprises:

a second transmission gate, an input terminal of which is used for receiving the input signal, and a controlled terminal of which is used for receiving the control signal;

and the input end of the phase inverter is connected with the output end of the second transmission gate, and the output end of the phase inverter is the second output end.

5. The latch circuit according to claim 1, wherein the output module comprises:

a first pull-up circuit, a first end of the first pull-up circuit being connected to the first output terminal, a second end of the first pull-up circuit being connected to the second output terminal;

and a first end of the first pull-down circuit is connected with the first output end, a second end of the first pull-down circuit is connected with the second output end, and a third end of the first pull-down circuit is connected with a third end of the first pull-up circuit so as to output the output signal together.

6. The latch circuit according to claim 5, wherein the first pull-up circuit comprises:

a first transistor, a first end of which is connected to a power supply voltage, and a control end of which is connected to the second output end;

and a first end of the second transistor is connected with a second end of the first transistor, a control end of the second transistor is connected with the first output end, and a second end of the second transistor is a third end of the first pull-up circuit.

7. The latch circuit according to claim 5, wherein the first pull-down circuit comprises:

a third transistor, a first end of the third transistor being a third end of the first pull-down circuit, a control end of the third transistor being connected to the first output end;

a first end of the fourth transistor is connected to the second end of the third transistor, a control end of the fourth transistor is connected to the second output end, and a second end of the fourth transistor is grounded.

8. The latch circuit of claim 1, wherein the feedback control module comprises:

the first feedback circuit is respectively connected with the output end of the output module, the second output end and the first output end, and is used for controlling the level state of the first output end to be the first level state according to the output signal and the second signal;

and the second feedback circuit is respectively connected with the output end of the output module, the first output end and the second output end and is used for controlling the level state of the second output end to be the second level state according to the output signal and the first signal.

9. The latch circuit according to claim 8, wherein the first feedback circuit comprises:

a first end of the second pull-up circuit is connected with the second output end, a second end of the second pull-up circuit is connected with the output end of the output module, and a third end of the second pull-up circuit is connected with the first output end;

and the first end of the second pull-down circuit is connected with the second output end, the second end of the second pull-down circuit is connected with the output end of the output module, and the third end of the second pull-down circuit is connected with the first output end.

10. The latch circuit according to claim 8, wherein the second feedback circuit comprises:

a first end of the third pull-up circuit is connected with the first output end, a second end of the third pull-up circuit is connected with the output end of the output module, and a third end of the third pull-up circuit is connected with the second output end;

and the first end of the third pull-down circuit is connected with the first output end, the second end of the third pull-down circuit is connected with the output end of the output module, and the third end of the third pull-down circuit is connected with the second output end.

Images