CN112671392A - Single event transient resistant buffer for high-level reset circuit - Google Patents
Single event transient resistant buffer for high-level reset circuit Download PDFInfo
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- CN112671392A CN112671392A CN202011554305.9A CN202011554305A CN112671392A CN 112671392 A CN112671392 A CN 112671392A CN 202011554305 A CN202011554305 A CN 202011554305A CN 112671392 A CN112671392 A CN 112671392A
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- 239000000872 buffer Substances 0.000 title claims abstract description 76
- 230000001052 transient effect Effects 0.000 title claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000002245 particle Substances 0.000 abstract description 19
- 238000010586 diagram Methods 0.000 description 5
- 230000002787 reinforcement Effects 0.000 description 4
- 238000010849 ion bombardment Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- LPLLVINFLBSFRP-UHFFFAOYSA-N 2-methylamino-1-phenylpropan-1-one Chemical compound CNC(C)C(=O)C1=CC=CC=C1 LPLLVINFLBSFRP-UHFFFAOYSA-N 0.000 description 1
- 240000003023 Cosmos bipinnatus Species 0.000 description 1
- 235000005956 Cosmos caudatus Nutrition 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Abstract
The invention discloses a single-particle transient resistance buffer for a high-level reset circuit, which comprises a first-stage inverter circuit and a second-stage inverter circuit which are sequentially connected, wherein the first-stage inverter circuit comprises a first transistor and a first resistor, the second-stage inverter circuit comprises a second transistor and a second resistor, the grid electrode of the first transistor is connected with an input signal of the buffer, the drain electrode of the first transistor is respectively connected with the first resistor and the grid electrode of the second transistor, the drain electrode of the second transistor is connected with a power supply through the second resistor, and the drain electrode of the second transistor is also connected with an output signal end of the buffer. The invention can be used for a high-level reset circuit, improves the single-particle transient resistance of the reset circuit, and reduces the influence of the single-particle transient generated by the reset circuit on a functional circuit.
Description
Technical Field
The invention relates to the technical field of CMOS integrated circuit reset circuits, in particular to a single-event transient resistance buffer for a high-level reset circuit.
Background
In the cosmos space, there are a large number of energetic particles (protons, electrons, heavy ions, etc.). After being bombarded by the high-energy particles, the integrated circuit can generate single-particle transient pulses. For example, when the single-event transient pulse is transmitted to a reset port of the time sequence unit, the time sequence unit adopts an asynchronous reset mode, and the time sequence unit can be immediately reset only by meeting the minimum pulse width of a reset signal, so that the data value stored by the time sequence unit is changed. Because the reset signal is a global signal, if a single-event transient pulse is generated at the root node of the reset circuit, the whole integrated circuit is reset, thereby causing errors. As indicated by "Single Event transitions in Digital CMOS-A Review" published by L.W.Massengill et al in IEEE transaction on Nuclear Science (IEEE Nuclear Science journal) "(for A Review of Single-particle Transients in Digital CMOS circuits, vol.60, vol.3, p.2013, page 1767), Single-particle Transients have become A major source of soft errors. Therefore, it is necessary to perform single event transient resistance reinforcement for the reset circuit.
CMOS integrated circuit reset circuits are typically formed by a CMOS buffer formed by a plurality of transistors which must be turned off when the CMOS buffer is in operation, and such off transistors are sensitive to particle bombardment. When the high energy particles bombard the transistors in the off state in the CMOS buffer, a single event transient occurs, and thus the CMOS buffer is more sensitive to the single event transient. As shown in fig. 1, the CMOS buffer at least includes 2 PMOS transistors and 2 NMOS transistors, when the CMOS buffer is working, at least 1 PMOS transistor and 1 NMOS transistor are in off state, and the 2 transistors in off state are sensitive to the heavy ion bombardment, which is the sensitive node. As shown in fig. 2, for the high level reset circuit, for example, the high level reset circuit is formed by the CMOS buffer shown in fig. 1, the CMOS buffer is started to operate, when the input is at a low level, the transistor N1 and the transistor P2 are both in an off state, and when particles bombard the two transistors, a single particle transient is generated, that is, the transistor N1 and the transistor P2 are sensitive nodes, and the two sensitive nodes are sensitive to heavy ion bombardment, which affects the stability of the circuit. Therefore, it is desirable to provide a Single-Event Transient (SET) resistant buffer for a high-level reset circuit, so as to improve the Single-Event Transient (SET) resistant capability of the high-level reset circuit.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the single-event transient resistance buffer for the high-level reset circuit, which has a simple structure and low cost, can improve the single-event transient resistance of the reset circuit and reduce the influence of the single-event transient generated by the reset circuit on the functional circuit.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
the utility model provides an anti single event transient buffer for high level reset circuit, is including the first order inverter circuit, the second order inverter circuit that connect gradually, the first order inverter circuit includes first transistor P1, first resistance R1, the second order inverter circuit includes second transistor N2, second resistance R2, the gate access of first transistor P1 the input signal of buffer, the drain electrode of first transistor P1 is connected respectively first resistance R1, the gate of second transistor N2, the drain electrode of second transistor N2 passes through second resistance R2 connects the power, the drain electrode of second transistor N2 still is connected the output signal end of buffer.
Further, when the input signal is in a low state, the first transistor P1 and the second transistor N2 are both in an open state.
Further, the first resistor R1 and/or the second resistor R2 are polysilicon resistors.
Further, the first transistor P1 is a PMOS transistor, and the second transistor N2 is an NMOS transistor.
Furthermore, one end of the second resistor R2 is connected to the drain of the second transistor N2, the other end is connected to a power supply, and the source of the second transistor N2 is grounded.
Further, the buffer comprises more than two stages, and the buffers are connected in series.
A high-level reset circuit comprises more than two stages of buffers, wherein the buffers are sequentially connected in series.
Compared with the prior art, the invention has the advantages that:
1. the buffer for the high-level reset circuit is formed by using the resistor at the sensitive node position when the high-level reset is realized and keeping using the transistor at other nodes, so that the sensitive node of the buffer sensitive to heavy ion bombardment can be eliminated, the buffer does not have the sensitive node, and the single-particle transient-resistant reinforcement of the buffer of the high-level reset circuit is realized;
2. after the functional circuit works normally, the particle bombardment buffer circuit can not generate single-particle transient pulse, so that the normal work of the functional circuit can be ensured.
Drawings
Fig. 1 is a structure of a CMOS buffer in the prior art.
Fig. 2 is a schematic diagram of the sensitive node principle when the input is low in the CMOS buffer in the prior art.
Fig. 3 is a schematic structural diagram of the anti-single event transient buffer for the high-level reset circuit according to the present embodiment.
Fig. 4 is a schematic diagram of a reset circuit formed by connecting a plurality of buffers.
FIG. 5 is a diagram of a simulated waveform for testing particle bombardment using a high level reset circuit constructed with a conventional buffer in an embodiment of a specific application.
FIG. 6 is a diagram of simulated particle-bombarded waveforms obtained during testing of a high-level reset circuit constructed using the buffer of the present invention in an exemplary embodiment.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
As shown in fig. 3, the single event transient (spn) resistant buffer for the high-level reset circuit of the present embodiment includes a first-stage inverter circuit 1 and a second-stage inverter circuit 2 connected in sequence, where the first-stage inverter circuit 1 includes a first transistor P1 and a first resistor R1, the second-stage inverter circuit includes a second transistor N2 and a second resistor R2, a gate of the first transistor P1 is connected to an input signal of the buffer, a drain of the first transistor P1 is connected to gates of the first resistor R1 and the second transistor N2, a drain of the second transistor N2 is connected to a power supply through the second resistor R2, a drain of the second transistor N2 is further connected to an output signal terminal of the buffer, and when an input is in a low-level state, the first transistor P1 and the second transistor N2 are both in an on state.
Since the reset circuit gives the circuit reset signal only when the functional circuit starts to work normally and then keeps outputting normally, the sensitive node in the reset circuit is fixed after the functional circuit starts to work. In the present embodiment, a sensitive node in the buffer of the high-level reset circuit is determined, as shown in fig. 2, when the high-level reset circuit is formed by the CMOS buffer shown in fig. 1, the CMOS buffer is activated, and when the input is low, the transistor N1 and the transistor P2 are in an off state, and the transistor N1 and the transistor P2 are sensitive nodes. In the embodiment, after the sensitive node of the buffer for the high-level reset circuit is determined, the resistor is used at the sensitive node position, and the transistors are kept at other nodes to form the buffer for the high-level reset circuit.
As shown in fig. 3, where the input is a, the output is Y, the power supply is VDD, the ground is GND, the buffer in this embodiment is formed by cascading two stages of inverter circuits, the first transistor P1 is a PMOS transistor, the second transistor N2 is an NMOS transistor, the first stage inverter circuit 1 is composed of a first transistor P1 and a first resistor R1, the input is a, and the output is X0; the second-stage inverter circuit 2 is composed of a second resistor R2 and a second transistor N2, the input is X1, and the output is Y; the grid of the first transistor P1 is connected with the input signal of the buffer, the drain of the first transistor P1 is respectively connected with the grids of the first resistor R1 and the second transistor N2, the drain of the second transistor N2 is connected with the power supply through the second resistor R2, one end of the second resistor R2 is connected with the drain of the second transistor N2, and the other end is connected with the power supply; the drain of the second transistor N2 is also connected to the output signal terminal of the buffer, and the source of the second transistor N2 is grounded. In the buffer of the embodiment, when the input is in the low level state, the first transistor P1 and the second transistor N2 are both in the open state, and no single event transient sensitive node exists, so that the buffer can be used for a high level reset circuit to realize the reinforcement of the reset buffer against the single event transient.
In this embodiment, the first resistor R1 and the second resistor R2 specifically adopt polysilicon resistors. The polysilicon resistor has good stability and high precision, can further improve the single-particle transient resistance of the buffer by using the polysilicon resistor at the sensitive node of the buffer unit, and is more suitable for engineering application.
In order to construct the buffer, in a specific application embodiment, a first-stage inverter circuit can be constructed by using 1 PMOS transistor P1 and 1 polysilicon resistor R1, wherein a source of the PMOS transistor P1 is connected to a power supply, a drain is connected to an output, and a gate is connected to an input, one end of the polysilicon resistor R1 is grounded, and the other end is connected to the output; then, 1 NMOS transistor and 1 polysilicon resistor R2 are used for constructing a second-stage inverter, wherein the source electrode of the NMOS transistor N2 is grounded, the drain electrode of the NMOS transistor N2 is connected with an output, and the grid electrode of the NMOS transistor N2 is connected with an input, one end of the polysilicon resistor R2 is connected with a power supply, and the other end of the polysilicon resistor R2 is connected with an output; the output of the first-stage inverter circuit is connected to the input of the second-stage inverter circuit to form a required buffer, the input of the first-stage inverter circuit is the input of the buffer, and the output of the second-stage inverter circuit is the output of the buffer. The buffer has no single-event transient sensitive node, and can realize the single-event transient resistance reinforcement of the reset buffer.
In this embodiment, the reset circuit may further include more than two stages of buffers, and as shown in fig. 4, the reset circuit is formed by cascading 99 stages of buffers, where the input of the 1 st stage of buffer is a 1 node, and the output is a 2 node; the input of the 2 nd-level buffer is 2 nodes, and the output is 3 nodes; and so on.
To verify the effectiveness of the present invention, a reset circuit is constructed in the same connection manner as fig. 4 using a conventional buffer as shown in fig. 1 in a specific application embodiment, and the function of the reset circuit is verified. When the functional circuit works normally, the reset circuit inputs a low level and outputs the low level; the exponential current source simulates particles to bombard the P2 transistor of the reset circuit buffer1, a SET pulse of 10ns is injected, and the SET pulse continuously propagates, so that the functional circuit is reset, and further the functional circuit is in error. The SPICE simulation waveform obtained in the specific application embodiment is shown in fig. 5, wherein v (1) represents the voltage waveform of the input node 1 of the buffer1, v (2) represents the voltage waveform of the output node 2 of the buffer1, v (3) represents the voltage waveform of the output node 3 of the buffer2, and v (100) represents the voltage waveform of the output node 100 of the buffer 99.
This embodiment also adopts the buffer structure of the present invention as shown in fig. 3 and constitutes a reset circuit in a connection manner as shown in fig. 4, and verifies the function of the reset circuit. When the functional circuit works normally, the reset circuit inputs a low level and outputs the low level, and because the buffer of the invention inputs two transistors (the transistor P1 and the transistor N2) which are in an open state and no sensitive node exists, when the N2 transistor of the reset circuit buffer1 is bombarded by analog particles of an exponential current source, although the output voltage v (2) of the buffer1 is pulled down, the output voltage v (2) is still in the low level, the pulse of the v (2) cannot be continuously propagated, as shown in fig. 6, as can be seen from fig. 6, the buffer circuit of the invention has the property of resisting the single-event transient immunity and strengthening the single-event transient.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (7)
1. A buffer for resisting single event transient for high level reset circuit is characterized in that: including the first order inverter circuit (1), second order inverter circuit (2) that connect gradually, first order inverter circuit includes first transistor P1, first resistance R1, second order inverter circuit (2) include second transistor N2, second resistance R2, first transistor P1's gate access the input signal of buffer, first transistor P1's drain is connected respectively first resistance R1 the gate of second transistor N2, second transistor N2's drain passes through second resistance R2 connects the power, second transistor N2's drain still connects the output signal end of buffer.
2. The single event transient resistant buffer for a high level reset circuit of claim 1, wherein: when the input signal is in a low state, the first transistor P1 and the second transistor N2 are both in an open state.
3. The single event transient resistant buffer for a high level reset circuit of claim 1, wherein: the first resistor R1 and/or the second resistor R2 are polysilicon resistors.
4. The single event transient resistant buffer for a high level reset circuit of claim 1, wherein: the first transistor P1 is a PMOS transistor and the second transistor N2 is an NMOS transistor.
5. The single event transient resistant buffer for a high level reset circuit of claim 1, wherein: one end of the second resistor R2 is connected to the drain of the second transistor N2, the other end is connected to a power supply, and the source of the second transistor N2 is grounded.
6. The single event transient resistant buffer for the high level reset circuit according to any one of claims 1 to 5, wherein: the buffer comprises more than two stages, and the buffers at all stages are connected in series.
7. A high level reset circuit, comprising: the buffer of any one of claims 1 to 6 comprising more than two stages, the stages being connected in series in sequence.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011554305.9A CN112671392A (en) | 2020-12-24 | 2020-12-24 | Single event transient resistant buffer for high-level reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011554305.9A CN112671392A (en) | 2020-12-24 | 2020-12-24 | Single event transient resistant buffer for high-level reset circuit |
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| CN112671392A true CN112671392A (en) | 2021-04-16 |
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4532609A (en) * | 1982-06-15 | 1985-07-30 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory device |
| JPS63221711A (en) * | 1987-03-11 | 1988-09-14 | Nippon Denso Co Ltd | Reset circuit |
| US4791322A (en) * | 1987-05-19 | 1988-12-13 | Gazelle Microcircuits, Inc. | TTL compatible input buffer |
| US5517144A (en) * | 1993-06-25 | 1996-05-14 | Sony Corporation | Power-on reset circuit |
| US5539457A (en) * | 1993-12-08 | 1996-07-23 | Nec Corporation | Signal processing circuit for solid state image sensor having a structure for suppresing a reset noise |
| JPH1125685A (en) * | 1997-07-03 | 1999-01-29 | Mitsubishi Electric Corp | Semiconductor storage |
| US20030189450A1 (en) * | 2002-04-08 | 2003-10-09 | Yoshihiko Kamata | Power on reset circuit |
| US20040012267A1 (en) * | 2002-07-22 | 2004-01-22 | Kang Hee-Bok | Power-on reset circuit for use in semiconductor device |
| CN101622704A (en) * | 2008-02-06 | 2010-01-06 | 松下电器产业株式会社 | Semiconductor device and method for resetting the same |
| US8416007B1 (en) * | 2011-05-02 | 2013-04-09 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | N channel JFET based digital logic gate structure |
| JP2016082501A (en) * | 2014-10-21 | 2016-05-16 | 株式会社デンソー | Power-on reset circuit |
-
2020
- 2020-12-24 CN CN202011554305.9A patent/CN112671392A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4532609A (en) * | 1982-06-15 | 1985-07-30 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory device |
| JPS63221711A (en) * | 1987-03-11 | 1988-09-14 | Nippon Denso Co Ltd | Reset circuit |
| US4791322A (en) * | 1987-05-19 | 1988-12-13 | Gazelle Microcircuits, Inc. | TTL compatible input buffer |
| US5517144A (en) * | 1993-06-25 | 1996-05-14 | Sony Corporation | Power-on reset circuit |
| US5539457A (en) * | 1993-12-08 | 1996-07-23 | Nec Corporation | Signal processing circuit for solid state image sensor having a structure for suppresing a reset noise |
| JPH1125685A (en) * | 1997-07-03 | 1999-01-29 | Mitsubishi Electric Corp | Semiconductor storage |
| US20030189450A1 (en) * | 2002-04-08 | 2003-10-09 | Yoshihiko Kamata | Power on reset circuit |
| US20040012267A1 (en) * | 2002-07-22 | 2004-01-22 | Kang Hee-Bok | Power-on reset circuit for use in semiconductor device |
| CN101622704A (en) * | 2008-02-06 | 2010-01-06 | 松下电器产业株式会社 | Semiconductor device and method for resetting the same |
| US8416007B1 (en) * | 2011-05-02 | 2013-04-09 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | N channel JFET based digital logic gate structure |
| JP2016082501A (en) * | 2014-10-21 | 2016-05-16 | 株式会社デンソー | Power-on reset circuit |
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