JPS63221711A - Reset circuit - Google Patents

Abstract

PURPOSE:To surely generate a power-on reset signal by providing a grounded- source circuit stage provided with a resistive load element and an enhancement CMOS transistor(TR) and a CMOS inverter stage whose output stage connects to a capacitive load element. CONSTITUTION:The titled circuit consists of a 1st stage groundedsource circuit 51, a 2nd stage common source circuit 52 and a 3rd stage CMOS inverter 53. Drive transistors(TRs) 1, 2, 3, 4 of each stage are formed as the enhancement respectively. A drain voltage is fed back to the fate by connecting the drain and source of the TR 1 in the 1st stage grounded-source circuit 51 and the voltage at its output contact (a) is started after the power voltage exceeds a threshold voltage. Similarly, the 2nd stage grounded-source circuit 52 starts voltage rise, an output voltage of the 3rd stage inverter 53 is inputted to a Schmitt trigger 5, where the voltage is converted into binary information with a hysteresis.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a reset circuit for a semiconductor device, and in particular to a reset circuit for a semiconductor device.
The present invention relates to a reset circuit built into an integrated circuit. The invention is used, for example, in MO8 integrated circuit devices for driving display elements.

[Prior Art] Power-on reset circuits that prevent malfunctions of electronic circuits that occur when the power supply voltage rises are known. The above power-on reset circuit generates the III III signal with a delay from the rise of the power supply voltage, and the above 11i
The 1+ control signal connects the output stage of the display driver, etc. to &1lt.
ll to prevent erroneous display or malfunction.

As can be seen from the above description, the power-on reset circuit has a delay circuit function that delays the rising waveform of the power supply voltage by a predetermined time, and a non-linear circuit that converts the rising waveform into a binarized frill lit signal of a predetermined level. It has both functions.

In order to achieve the above circuit function, enhancement type M
A power-on reset circuit configured with a common source circuit using an OS transistor as a driver has already been proposed.

For example, JP-A 1986-208621@ proposes a MOS power-on reset circuit that uses a capacitor as a load element in the first-stage common source circuit.

The output contact of the first source-grounded circuit stage sends an output signal voltage to a CMOS inverter stage loaded with a second capacitor, and the output voltage of the CMOS inverter stage is further binarized by an inverter serving as a comparator, and output control wJW1 pressure.

In the prior art, the rise of the output voltage of the first-stage source-grounded circuit is delayed because it is limited by the time constant of the MOS transistor and its load capacitor.

The operation of the second stage CMOS inverter circuit having a capacitive load is basically the same as that of the first stage common source circuit. Therefore, it is understood that the MOS power-on reset circuit disclosed in the above-mentioned prior art is essentially a multistage source-grounded charging/discharging circuit comprising a load capacitor and a MOS transistor.

Other MOS power applications previously filed by the applicant
The first stage source common circuit of the on-reset circuit is the driving M
It consists of an OS transistor and its load resistance.

The M and OS transistors mentioned above are of the enhancement type, and furthermore, their gates and drains are connected. The second stage common source circuit similarly includes a driving MOS transistor and its load resistance.

The MOS transistor of the first stage common source circuit is of a conductivity type opposite to that of the MOS transistor of the second stage common source circuit. The output voltage of the second stage common source circuit is outputted via a binary circuit and becomes an output control voltage.

From the above description, it can be seen that the MOS power-on reset circuit previously proposed by the applicant is essentially a multi-stage common source circuit comprising a load resistor and a MoS transistor.

Descriptions of the above prior art are summarized below.

The first MOS power-on reset circuit includes multi-stage common source circuits each having a capacitive load. It is therefore abbreviated below as a capacitively loaded MOS power-on reset circuit.

The second MOS power-on reset circuits include multi-stage common source circuits each having a resistive load. It is therefore abbreviated below as a resistive load MOS power-on reset circuit.

[Problems to be Solved by the Invention] In the capacitive load type MOS power-on reset circuit, the output voltage rise characteristic depends on the CR time constant.
When the power supply voltage rises slowly, there is a risk that the control signal will be output before the power supply voltage is established.

The above problem can be prevented by increasing C (capacitance) and R (resistance). However, integrating large C and R inside an IC is not easy and results in a considerable increase in cost.

The method of externally attaching C and R also causes a considerable increase in mounting volume and cost. Furthermore, it is often necessary to generate a control signal from the power-on reset circuit to enable the circuit to output as soon as the power supply voltage is established quickly. However, the output voltage rise characteristic of the capacitive load type MOS power-on reset circuit is constant.

Since the resistive load type MOS power-on reset circuit does not use a capacitor, the output II-III voltage can sufficiently follow the rapid rise characteristics of the power supply voltage. However, the problem with this resistive load type MO, S power-on reset circuit is that it consumes a lot of power.

Therefore, the present invention aims to improve the above problems.

One of the specific objects of the present invention is to reduce malfunctions at the rise and fall of the power supply voltage.
This is the development of a set circuit. Another object of the invention is Mos!
'This is the development of a low-cost MOS power-on reset circuit that can be built into a product circuit.

Means and operation for solving problem E] The basic structure of the present invention is as follows: In a reset circuit having a common source circuit including an enhancement type MOS transistor, the common source circuit includes a resistive load element and an enhancement type MOS transistor. A reset circuit is characterized in that it has a circuit stage and a CMOS inverter stage with a capacitive load connected to its output.

The reset circuit of the present invention includes a resistive cylindrical source-grounded circuit membrane and a capacitively loaded source-grounded circuit stage. Therefore,
Utilizing the output voltage delay effect due to the threshold voltage of the MOS transistor in the former and the output voltage delay effect due to the OR characteristic in the latter, it is possible to
It is possible to create a reset circuit that is unlikely to malfunction. Furthermore,
Since the capacitive load type common source circuit of the present invention is constituted by a CMOS inverter stage, the output voltage is rapidly lowered when the power supply voltage drops, thereby preventing malfunction.

L Example 1 FIG. 1 is an equivalent circuit diagram representing one embodiment of the present invention.

The first-stage source common circuit 51 consists of a PMOS transistor 1 which is a driving element and its load resistor 6.

The source of the PMOS transistor 1 is the first power supply terminal Vd
d, and the drain is connected to the second power supply terminal Vs through the resistor 6.
connected to s.゛Also, the gate and drain are connected. The second stage common source circuit 52 is composed of an NMo5 transistor 3 and its load resistor 7. The source of the llNNMOS transistor 3 is connected to the second power supply terminal Vss, and the drain is connected via the resistor 7 to the first power supply terminal Vdd.

The third stage CMOS inverter 53 is constituted by a PMO8l-transistor 2, an NMOS transistor 4, and a capacitor 8 as its load element. The output contact C of the CMOS inverter 53 is connected to the second power supply terminal Vss via the capacitor 8.

Output contact aLt of the first stage common source circuit 51 is connected to the gate of the driving transistor 3 of the second stage common source circuit 52. Further, the output contact of the second stage common source circuit 52 is connected to the gates of the driving transistors 2 and 4 of the third stage CMOS inverter 53. The output contact C of the third stage CMOS inverter 53 is connected to the input terminal of the Schmitt trigger 5.

The driving transistors 1.2.3.4 in each stage are of the enhancement type and have threshold voltages.

By connecting the drain and source of transistor 1, the voltage at the drain is fed back to the gate.

As a result, the rise of the output contact voltage of this common source circuit is delayed compared to the rise of the power supply voltage Vdd. Also, since transistor 1 is of the enhancement type, its output contacts a4. After the tI source voltage exceeds the threshold voltage, the voltage begins to rise.

Similarly, the driving transistor 3 of the second stage common source circuit 52 starts conducting when the output voltage of the first stage common source circuit 51 exceeds the threshold voltage of the transistor 3. Therefore, at the output contact of the second stage common source circuit 52, the rise is delayed by the threshold voltage valves of transistors 1 and 3.

The third stage CMOS inverter 53 is an integrating circuit having the capacitor 8 as a load.

When transistor 3 is turned off, the power supply voltage V
If dd is greater than or equal to the threshold voltage of transistor 4, transistor 4 is turned on and capacitor 8 is discharged.
Transistor 2 is turned off. If Vdd increases further, transistor 3 turns on and the voltage vb at the output contact becomes lower than the threshold voltage of transistor 4.

As a result, transistor 4 is cut off and transistor 2
is turned on and capacitor 8 is charged.

Therefore, the output voltage Vc output from the output contact C is vd
d is delayed by the sum of the delays of the respective threshold voltages of the transistors 1 and 3 and the time constant of the integrating circuit made up of the transistor 2 and the capacitor 8.

The output voltage Vc of the third stage CMOS inverter 53 is input to the Schmitt trigger 5 and converted into binary information with hysteresis. Note that here, instead of the Schmitt trigger 5, a CMOS inverter or comparator 2f1 is used.
It is also possible to use one circuit.

The operation of the above circuit will be explained below.

However, each enhancement MOS transistor 1.2
．． The absolute values of the threshold m'Fi pressures of 3 are equal and lVt1, and the lower 1fll! ! It is assumed that VSs is OV. It is assumed that the resistor 6 and the left 7 are sufficiently large.

I) Under the condition that the source voltage Vdd rises, the output voltage va of the first stage common source circuit is: Va-Vss-0[
Vco (Vdd< l Vt I : Trl OFF> and Va absent Vdd - I V t 1 (Vdd> l Vt l ; Trl ON). Therefore, the potential vb at point b is vb#vdd (Vdd <21Vtl; Tr3 OFF> Also, VbL; Vss-0 [Vl (Vdd>21Vtl: Tr3 ON).

Therefore, the potential VC at point 0 is Vc=Vss-0[v] (Vdd<21Vtl; Tr2 OFF, Tr4
ON>. Therefore, at this time, Vo-0[Vl (Vo is the output voltage of the Schmitts trigger 5), that is, Vo is at a low level.

Further, Vd(l increases, Vdd>2 I V t I , Tr2 turns on, Tr4 turns off, and capacitor 8 is charged.

When Vc becomes vc>vp (Vρ is the input voltage of the Schmitt trigger 5 when the output voltage of the Schmitt trigger 5 changes to H level) due to this charging, V
o is inverted to high level.

After that, VC reaches Vdd, and the Schmitt 5 output voltage v
O maintains a high level.

Let RO be the conduction resistance of the transistor 2, and CO be the capacitance of the capacitor 8. RO is a function of the channel resistance determined from the well-known MoS transistor saturation and desaturation current equations.

FIG. 2 is a power supply voltage waveform diagram when the 88M voltage changes slowly, and FIG. 3 is a voltage waveform diagram when the power supply voltage rises rapidly.

Vdd is 2 l Vt l 2 RfiJeTo,
! :L, and the time when Vc reaches ■pk: is assumed to be T1.

T1 is expressed by the following formula.

Tl =To-Co-Ro-1n (1-Vl)/
Vdd) In reality, when the power supply voltage rises rapidly, TO can be almost ignored. That is, as can be seen from FIGS. 2 and 3, the output voltage Vc of the output contact C of the common source circuit 53 starts to rise after Vdd exceeds 21 Vtl.

Therefore, even if the rise characteristics of the power supply voltage are different, the output voltage 0 of the Schmitts trigger 5 is at least equal to the time TO1.
It can be seen that the frontage level of T1 can actually be maintained.

As a result, after Vdd is sufficiently established, the output signal voltage vO starts to be inverted, and the capacitance of the capacitor 8 can be reduced by the output voltage delay caused by the common source circuits 51 and 52.

■) When the power supply voltage Vdd falls, the third stage CMOS
The output voltage Vc of the inverter 53 falls as Vdd falls. Further, when Vdd<2IVtl, MOS transistor 2 is cut off and MOS transistor 4 is turned on. Therefore, the discharge time of the capacitor 8 can be freely changed by setting the channel resistance of the MOS transistor 4.

Due to the above discharge, the output voltage Vc becomes Vss-OV,
The output voltage vO of Schmitt 5 also becomes low level.

When the power supply voltage Vdd does not fall below 21 Vtl and rises again, the output voltage 0 continues to maintain a high level. That is, even if there is an instantaneous mm voltage fluctuation, Vo can be stably maintained at a high level.

FIG. 4 shows an example of changing the potential of output contact a.

In this case, a PMOS transistor 1' having the same structure as the MOS transistor 1 is added between the drain of the MOS transistor 1 and the output contact 8. In this case, the number of PMOS transistors can be increased by two, three, etc. as necessary. Furthermore, it is also possible to input the gate voltage of the PMOS transistor using a resistor division equiangular method to change the ON start voltage of the transistor.

Note that it is also possible to replace the resistor 6.7 with various MoS transistors for load.

In Figure 5, a MOS transistor 3-, which has the same structure as the Mo8 T-transistor 3, is added between the output contact and the MOS transistor 3 of the first-stage source-grounded circuit in Figure 1, and the same discussion as in Figure 4 can be made. It works.

FIG. 6 shows an example in which the connection positions of the PMOS transistor 1 and the NMo5 transistor 3 are changed.

Since the logic is reversed, an inverter 50 is added to match the logic. It is also possible to omit the inverter 50.

[Effects] Since the reset circuit of the present invention includes a resistive load type source installation circuit stage and a resistive load type CMOS inverter stage,
It becomes possible to reliably generate a power-on reset signal regardless of the rise and fall characteristics of the power supply voltage. In addition, by increasing the charging time constant,
No malfunction occurs even if there are instantaneous power supply voltage fluctuations.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of one embodiment of the MOS reset circuit of the present invention. Figures 2 and 3 show the power-on mode shown in Figure 1.
FIG. 3 is a rising waveform diagram of a reset circuit. Figure 4 is the first
FIG. 6 is an equivalent circuit diagram of a modified example of the first stage common source circuit shown in the figure. FIG. 5 is an equivalent circuit diagram of a modified embodiment of the first stage common source circuit shown in FIG. FIG. 6 is an equivalent circuit diagram of a modified embodiment of the MOS reset circuit of FIG. 1. 6...Load resistance 7...Load resistance 8...Load capacitor 5
1... First stage source grounding circuit 52... Second stage source grounding circuit 53... Third stage CMOS inverter Patent applicant Nippondenso Co., Ltd. Agent Patent attorney Hirodo Okawa Patent attorney Akio Maruyama Figure 1 51- 1--♂Ibiki color Akatsuki sauce Tsutomuguchi road 52----
Rito 2B and 汀ψui'' 1 God tjiso Aoi died 4 Koto 53--
--CMOS inverter Figure 2 Figure 3

Claims (1)

[Claims] (1) In a reset circuit having a source-grounded circuit stage including an enhancement-type MOS transistor, the source-grounded circuit stage includes a resistive load element and an enhancement-type MOS transistor, and a CMOS circuit having a capacitive load element connected to its output terminal. A reset circuit characterized by having an inverter stage.