JP2003330555A - Semiconductor integrated circuit and ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LSI for an IC card comprising a stabilized power supply circuit capable of suppressing an excessive inflow current in turning on a power supply, and suppressing the excessive fluctuation of an output voltage VDD1 even if a load of an external power supply or an internal circuit fluctuates rapidly. <P>SOLUTION: The stabilized power supply circuit 100 comprises an output control MOS QO4 to generate an internal power supply VDD1 by inputting the external power supply VDD, and an error amplifier 11 to control a gate of the output control MOS QO4 by comparing a feedback voltage Vret reflecting the internal power supply and a reference voltage Vref. Further, the circuit 100 is provided with a current limiting MOS QD3 connected to a path where the quantity of current is limited, a switch SW2 to connect the current limiting MOS QD3 with the output control MOS QO4 in current mirror connection, and a time constant circuit to turn the switch on for a certain period from turning on the power supply. A voltage clamp means is provided at an output node of the feedback voltage Vret to block that the feedback voltage fluctuates over a certain voltage range. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique useful when applied to a semiconductor integrated circuit provided with a stabilized power supply circuit which receives an external power supply voltage to obtain a predetermined internal power supply, and particularly to an IC.
The present invention relates to a particularly useful technique for use in a card LSI (large-scale integrated circuit).

[0002]

2. Description of the Related Art In a credit card, a prepaid card for a public telephone, etc., an IC card in which an IC (integrated circuit) chip is embedded may be used to record various information. There are two types of IC cards, a contact type and a non-contact type. In the contact type IC card, input / output of power supply voltage and information is performed via a terminal pad formed on the card surface. In the contact type IC card, it is necessary to widen the input external power source to 1.8 to 5 V in order to support a plurality of generations of reading devices, and the IC chip needs such an external power source for an internal circuit. It is common to have a stabilized power supply circuit that generates an internal power supply voltage.

As a stabilized power supply circuit for an IC card,
For example, as shown in FIG. 13, an input voltage V that is an external power source
An output control MOS transistor QO4 that receives DD at its source terminal and outputs a voltage VDD1 supplied as an internal power source to its drain terminal is compared with a feedback voltage Vret obtained by dividing the output voltage VDD1 and a reference voltage Vref. An error amplifier 11 for controlling the gate of the transistor QO4, and an N-source connected to the output terminal of the error amplifier 11 and having a source grounded to increase the control range of the output current.
Channel drive MOSFET (NMOS) QD
A circuit including an amplifier circuit 12 including 2 and a constant current source QI is used.

[0004]

However, in the above-described conventional stabilized power supply circuit, since the output control MOS transistor QO4 is in the ON state at the start of power supply, a steep rise and a large voltage is applied as the external power supply. In this case, the current flowing into the voltage-smoothing filter capacitor Cf1 becomes large, which may exceed the current specifications set in the reading device or the IC card. In particular, when the source-grounded N-channel type MOS QD2 is used in the drive stage, the gate voltage of the output control MOS transistor QO4 becomes almost 0V until the output voltage VDD1 stabilizes, and its drain current is kept at the maximum state. Will be done. Even when the filter capacitor Cf1 is not provided, various parasitic capacitances are generated in the internal circuit, and the same phenomenon occurs.

Further, in order to reduce the number of parts in the IC card, the voltage smoothing filter capacitor Cf1 must also be provided in the chip, so that the capacitance cannot be increased so much that the load of the internal circuit and the fluctuation of the input voltage VDD are changed. The filter capacitor Cf1 could not absorb much. Therefore, if the response of the entire feedback circuit including the error amplifier 11 and the drive circuit 12 is poor, the output voltage VDD1 drops sharply when the load of the internal circuit changes abruptly, as shown in FIG. The problem arises that it jumps up and down. In addition, as shown in FIG.
Even if the input voltage VDD fluctuates rapidly, the output voltage VDD
There was a problem that the jumping up of the. Such a drop in the output voltage VDD1 may cause an internal circuit to malfunction depending on its magnitude, while a jump in the output voltage VDD1 may cause element breakdown.

The output control MOS transistor QO4 needs to have a large element size in order to cope with the input voltage VDD having a wide allowable range. As a result, the gate capacitance increases, and therefore the driving force of the drive circuit must be increased to increase the response speed of the feedback operation. However, since there is a trade-off relationship that if the driving force is increased, the power consumption of the driving circuit and the power consumption of the entire IC chip are increased, the driving force cannot be increased so much and the responsiveness of the feedback operation is improved. There was a problem that it could not be raised sufficiently.

The driving force can be increased by applying a push-pull type drive circuit to the drive stage. However, when a push-pull type drive circuit is provided in the subsequent stage of the differential amplifier, the push side drive circuit The drive MOS can be driven by the positive-phase output of the differential amplifier, but in order to drive the pull-side drive MOS, it is necessary to level-shift and use the negative-phase output of the differential amplifier. It becomes complicated, and the response time decreases due to the circuit delay.

An object of the present invention is to provide an IC card LSI having a stabilized power supply circuit which can prevent an excessive current from flowing at the start of power supply. Another object of the present invention is to provide an IC card LSI provided with a stabilized power supply circuit capable of avoiding a sudden up and down movement of the output voltage VDD1 even when a load of an external power supply or an internal circuit suddenly changes. Especially. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the output control M for inputting the first power supply voltage (external power supply) and generating the second power supply voltage (internal power supply)
In a stabilized power supply circuit including an OSFET and a voltage comparator that controls a gate of the output control MOSFET by comparing a feedback voltage related to an internal power supply with a reference potential, a current connected to a path whose current amount is limited. Limiting MOSFET
And the current limiting MOSFET as the output control MOSF
A switch for connecting a current mirror to ET and a time constant circuit for turning on the switch for a certain period after the power is turned on are provided. This makes it possible to prevent an excessive current from flowing when the power is turned on (when the power supply is started).

Further, the switch transistor forcibly turning off the output control MOSFET is compared with the feedback voltage related to the internal power supply and the reference potential, and when the internal power supply exceeds a predetermined voltage higher than the standard voltage, the switch transistor. And a second voltage comparison circuit for turning on the. With this configuration, it is possible to compensate for the insufficient response speed of the feedback circuit and suppress a large jump of the internal power supply.

Further, the output node of the feedback voltage is provided with voltage clamp means for preventing the feedback voltage from swinging over a certain voltage width. In the conventional stabilized power supply circuit, for example, when the load of the external power supply or internal circuit deviates from the standard state and the feedback voltage drops extremely, and then the external power supply or internal load immediately returns to the standard state, the feedback circuit Due to the delay, the external power supply and internal load are in the standard state and the feedback voltage drops extremely, which may cause a recoil phenomenon such that the internal power supply jumps up to the opposite side. With the above configuration, this recoil phenomenon can be reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a circuit configuration diagram showing a stabilized power supply circuit according to a first embodiment of the present invention, and FIG. 2 is a more detailed circuit diagram of this circuit. This stabilized power supply circuit 100 is an IC
An output voltage as a second power supply voltage that is suitable for being built in a card LSI (large-scale integrated circuit) and that receives an input voltage VDD as an externally supplied first power supply voltage and supplies it to an internal circuit. Generate VDD1.

The circuit configuration is such that an output control MOS transistor QO4 which receives an input voltage VDD at its source terminal and outputs an output voltage VDD1 at its drain terminal, and an output voltage VDD1.
Is divided to generate a feedback voltage Vret.
R2 (feedback circuit), a filter capacitor Cf1 for voltage smoothing, an error amplifier 11 as a voltage comparison circuit for amplifying a difference voltage between the feedback voltage Vrt and the reference voltage Vref,
Constant current source QI and N channel type drive MOS QD2
The output control MOS that receives the output of the error amplifier 11
A single-ended drive stage that drives the gate of the transistor QO4, a current limiting circuit 20 for limiting the inflow current at the start of supply of the input voltage VDD, and a current limiting circuit 2
A time constant circuit 30 (see FIG. 2) for generating control signals for the 0 switches SW1 and SW2 is provided.

The current limiting circuit 20 is an NMOS of the driving stage.
NMOS QD1 and switch SW1 for limiting the current flowing in QD2, and current limiting MOSFET for limiting the current flowing in the output control MOS transistor QO4
Is formed of a PMOS QD3 and a switch SW2. These first NMOS QD1 and PMOS QD
3 works only when the switches SW1 and SW2 are in the on state, and has no effect on the circuit when the switches are in the off state.

The NMOS QD1 of the current limiting circuit 20 is
Source terminal is ground, drain terminal is switch SW
1 through the output terminal of the error amplifier 11 and the drive MOS Q
It is connected to the connection node n1 of D2, and is coupled between the gate and drain. When the switch SW1 is turned on, the output current IoE from the error amplifier 11 flows to the ground. In addition, since the switch SW1 is turned on and the drive MOS QD2 is connected to the current mirror,
The current of the drive MOS QD2 is limited to the value obtained by multiplying the output current IoE by the mirror ratio. Output current IoE
Is limited to the operating current supplied by the constant current MOS Q2 of the error amplifier 11 or less.

That is, the NMOS of the current limiting circuit 20
If the mirror ratio between the QD1 and the drive MOS QD2 is a: b, the drive MOS when the switch SW1 is in the ON state.
The drain current IQD2 of QD2 is expressed by the following equation (1). IQD2 = IoE × (b / a) ··· (1)

The PMOS QD3 of the current limiting circuit 20 is
The source terminal is an external power supply line to which the input voltage VDD is applied, and the drain terminal is a driving MOS via the switch SW2.
It is connected to a connection node n2 between the drain terminal of QD2 and the gate terminal of the output control MOS transistor QO4, and the gate and drain are coupled together. Then, by turning on the switch SW2, a limited current flows between the source and drain of the PMOS QD3. Further, when the switch SW1 is turned on, a current mirror connection is made with the output control MOS transistor QO4, and this output control M
The current flowing in the OS transistor QO4 is
The current flowing through D3 is limited to a value obtained by multiplying the mirror ratio.

Specifically, when the switches SW1 and SW2 are on, the current flowing through the PMOS QD3 is (IQ
D2-IoD), the PMO of the current limiting circuit 20
If the mirror ratio between SQD3 and output control MOS transistor QD4 is c: d, then output control MOS transistor Q
The current IQD4 flowing through O4 is limited by the following equation (2). IQD4 = {IoE × (b / a) −IoD} × (d / c) ... (2)

Switches SW1 and SW of the current limiting circuit 20
As shown in FIG. 2, 2 is composed of a MOS transistor, and the control signal from the time constant circuit 30 is input to the gate thereof. The time constant circuit 30 has a resistor R30 and a capacitor C3 from the start of application of the input voltage VDD.
The switches SW1 and SW2 are turned on only for a period determined by 0, and after the lapse of the above period, the switches SW1 and SW2 are turned off. The period during which the switches SW1 and SW2 are turned on is preferably set to such a length that the output voltage VDD1 is sufficiently stable when the filter capacitor Cf1 is charged with the limited current IQD4 flowing in the output control MOS transistor QO4. This time T is expressed by the following equation (3). T> (Cf1 × VDD1) / IQD4 (3) where VDD1 = Vref × {R2 / (R2 + R1)}

With the above configuration, the inflow current flowing into the internal circuit of the IC card LSI is limited when the supply of the input voltage VDD is started, so that the current specifications set for the IC card and its reader can be ensured. Can be met. Then, when the current stabilizes, the action of the current limiting circuit 20 is immediately released, and the normal stabilized power supply circuit 10
A motion of 0 is obtained.

[Second Embodiment] FIG. 3 shows a circuit diagram of a stabilized power supply circuit according to a second embodiment of the present invention. This stabilized power supply circuit 100 does not use the active load MOSs Q5 and Q6 as shown in FIG. 2 to generate the output of the error amplifier 11, but uses one load MOS Q6a to output its current mirror output. Is the output of the error amplifier 11. Therefore, the current of the drive MOS QD2 that receives the output of the error amplifier 11 is limited to the value obtained by multiplying the current of the load MOS Q6a by the mirror ratio.

Therefore, the current limiting circuit 20a of the second embodiment.
Compared to the circuit of the first embodiment shown in FIG.
The configuration for limiting the current of D2 is omitted, and only the configuration of the PMOS QD3 for limiting the current of the output control MOS transistor QO4 and the switch SW2 for operating it is provided.

Stabilized power supply circuit 10 according to the second embodiment
In the case of 0, the circuit configuration is simple and the number of circuit elements is small as compared with the circuit of the first embodiment, but the total gain of the error amplifier 11, the driving stage and the output control MOS transistor QO4 becomes low, so that the first embodiment. The example circuit is superior in terms of stable power supply performance.

[Third Embodiment] FIG. 4 shows a circuit configuration diagram of a stabilized power supply circuit according to a third embodiment of the present invention, and FIG. 5 shows a more detailed circuit diagram of this circuit. The stabilized power supply circuit 100 of the third embodiment uses the output voltage VD supplied to the internal circuit.
A configuration is added to prevent D1 from jumping up significantly. Therefore, even if the input voltage VDD and the load of the internal circuit change suddenly, the output voltage V
It is possible to avoid problems such as the DD1 exceeding the withstand voltage of the internal circuit.

The stabilized power supply circuit 100 has an output voltage V
As the jump-up prevention circuit 40 of the DD1, a voltage comparator 42 as a second voltage comparison circuit that detects that the output voltage VDD1 exceeds a predetermined limit voltage higher than the standard voltage,
A switch MOS transistor Q1 for connecting the gate terminal and the source terminal of the output control MOS transistor QO4
3 and 3. As shown in FIG. 5, since the voltage comparator 42 drives the PMOS Q13, it has a conductivity M opposite to that of each MOSFET constituting the error amplifier 11.
It is composed of an OSFET.

The voltage comparator 42 resistance-divides the output voltage VDD1 into a second feedback voltage Vret2 and a reference voltage Vref.
The above detection is performed by comparing and. Second feedback voltage V
The resistance division ratio of ret2 is set so that the voltage becomes lower than the feedback voltage Vret input to the error amplifier 11,
As a result, the operation start points of the error amplifier 11 and the voltage comparator 42 are shifted. Since the resistance ratio can be formed without variation in the semiconductor manufacturing process, the relationship between the operation starting point of the voltage comparator 42 and the operation starting point of the error amplifier 11 should not be influenced by the variation in the manufacturing process. I can.

According to the stabilized power supply circuit 100 having such a jump-up prevention circuit 40, the input voltage VDD and the load of the internal circuit change abruptly, and the output voltage VDD1 is likely to greatly exceed the jump-up limit voltage. In the case where the output control MOS transistor QO4 becomes short, the voltage comparator 42 detects it and quickly short-circuits the gate and source of the output control MOS transistor QO4.
It is possible to prevent the output control MOS transistor QO4 from turning off and the output voltage VDD1 from jumping greatly. It should be noted that in order to shift the operation start points of the error amplifier 11 and the voltage comparator 42, the same feedback voltage Vret is input to both of them, while two reference voltages are generated and different ones are input to each. You may.

[Fourth Embodiment] FIG. 6 shows a circuit diagram of a stabilized power supply circuit according to a fourth embodiment of the present invention. In the stabilized power supply circuit 100 of the fourth embodiment, in order to make the operation start point of the voltage comparator 42 different from that of the error amplifier 11, the voltage to be compared is not changed but differential input is performed by the voltage comparator 42. This is realized by making the element sizes of the two input MOS Q10a, Q11a different between positive and negative, and the same operation as in the case of the third embodiment can be obtained.

[Fifth Embodiment] FIG. 7 is a circuit configuration diagram of a stabilized power supply circuit according to a fifth embodiment of the present invention, and FIG. 8 is a more detailed circuit diagram of this circuit. In the stabilized power supply circuit 100 of the fifth embodiment, the clamp circuit 50 is added to the same configuration as the conventional stabilized power supply circuit so that the feedback voltage Vret does not become lower than the clamp voltage (first voltage) smaller than the standard time. It is the one.

The clamp circuit 50 is supplied to the N-channel type clamp MOS N1 connected between the output line of the feedback voltage Vret and the power supply line to which the input voltage VDD is applied, and the gate terminal of the clamp MOS N1. Reference voltage Vref2 and a resistor R that delays the transmission of the variation to the gate terminal when the variation occurs in the reference voltage Vref2.
50 and a capacitor C50.

The clamp MOS N1 has a feedback voltage Vre.
When t is the voltage at the standard time, it is turned off and has no effect, but when the feedback voltage Vret falls below a certain value (= gate potential Vg-threshold voltage Vth), it is turned on to exert a clamp action. That is, the input voltage V
Due to a sudden change in DD or internal load, output voltage VDD1
When the feedback voltage Vret drops temporarily, the clamp MOSN1 is turned on and the feedback voltage Vret
Is a predetermined voltage (reference voltage Vref2-threshold voltage Vth)
Clamp to.

Further, the sudden change of the input voltage VDD or the internal load for turning on the clamp MOS N1 is caused by the reference voltage V.
Although it may appear as a change in ref2, the change in the reference voltage Vref is not immediately transmitted to the gate of the clamp MOS N1 due to the time constant circuit of the resistor R50 and the capacitor C50, which causes a temporary drop in the feedback voltage Vret. On the other hand, it is possible to always clamp at a predetermined voltage.

According to the stabilized power supply circuit 100 to which such a clamp circuit 50 is added, when the input voltage VDD and the internal load temporarily fluctuate greatly and the fluctuation immediately returns to the original level. In addition, it is possible to suppress the fluctuation of the output voltage VDD1 by exerting the following effects.

In general, for example, when the input voltage VDD is once smaller than the standard voltage and immediately returns to the original standard voltage, a pulse-like fluctuation is generated. VDD1 decreases, and the feedback voltage Vret decreases accordingly. Then, the reduction of the feedback voltage Vret is fed back by the feedback circuit, and the gate of the output control MOS transistor QO4 is controlled to be opened further. However, since the feedback operation by the error amplifier 11 and the driving stage has a delay, when the control for opening the gate is performed, the input voltage V
A reaction phenomenon occurs in which the DD returns to the original standard voltage and the output voltage VDD1 conversely rises from the standard time.

In such a case, the above clamp circuit 5
If 0 does not exist, when the temporary decrease in the input voltage VDD is extremely large, the accompanying decrease in the feedback voltage Vret is also extremely large, and accordingly, the rebound of the output voltage VDD1 is also large.

On the other hand, if the above-mentioned clamp circuit 50 is added, even if the temporary decrease of the input voltage VDD is very large, the decrease of the feedback voltage Vret can be suppressed to a constant level. Output voltage VD
The bounce of D1 can also be suppressed below a certain value.

FIG. 9 shows another circuit example of the stabilized power supply circuit to which a clamp circuit is added. As shown in the figure, this embodiment uses the resistor R5 from the clamp circuit 50 of FIG.
Although 0 and the capacitor C50 are removed, the well 6 is effective in the case of a circuit configuration in which variations in the input voltage VDD and the internal load do not significantly affect the reference voltage Vref3.

[Sixth Embodiment] FIG. 10 shows the sixth embodiment of the present invention.
The circuit diagram of the stabilized power supply circuit which concerns on an Example is shown. In the stabilized power supply circuit 100 of the sixth embodiment, the clamp circuit 60 includes a P-channel type clamp MOS P1 connected between the output line of the feedback voltage Vret and the ground GD, and a gate terminal of the clamp MOS P1. It is provided with a reference voltage Vref3 to be supplied, and a resistor R60 and a capacitor C60 that delay the transmission of the variation to the gate terminal when the variation occurs in the reference voltage Vref3.

While the clamp circuit according to the fifth embodiment did not lower the feedback voltage Vret to a certain value or less, the clamp circuit according to the sixth embodiment has a feedback voltage Vret.
This is to prevent ret from rising above the clamp voltage (second voltage) higher than the standard time. Then, according to this clamp circuit, when the output voltage VDD1 jumps up in a pulsed manner due to the abrupt change of the input voltage VDD or the internal load, the output voltage VDD1 is prevented from being greatly lowered by the reaction thereof. You can do it.

FIG. 11 shows another circuit example of the stabilized power supply circuit to which the clamp circuit is added. As shown in the figure, this embodiment uses the resistor R from the clamp circuit 60 of FIG.
Although 60 and the capacitor C60 are removed, such a circuit is effective in the case of a circuit configuration in which variations in the input voltage VDD and the internal load do not significantly affect the reference voltage Vref3.

FIG. 12 is a block diagram showing the overall configuration of an IC card LSI incorporating the above-mentioned stabilized power supply circuit. The IC card LSI according to the embodiment of the present invention includes the above-described stabilized power supply circuit 100, a power-on reset circuit 110 that resets the microcomputer 100 when the application of the input voltage VDD is started, a CPU 121, a nonvolatile memory 122, a RAM 123, and ROM 124 and CPU
The output voltage generated by the stabilized power supply circuit 100 is provided with a microcomputer 120 having a coprocessor 125 for assisting the function of 121, a voltage conversion circuit 130 for performing voltage conversion between an external signal and an internal signal, and the like. V
DD1 (internal power supply voltage) is the microcomputer 120
Is supplied as the operating voltage.

This IC card LSI is different from a PCMCIA-standard PC card in which a plurality of LSIs and external components such as capacitors are allowed to be mounted inside, and is a credit card that does not require external components. It is suitable for being embedded in thin cards such as or prepaid cards for telephones. The IC card of the embodiment of FIG. 12 has a terminal electrode on the surface, and is configured as a contact type IC in which the terminal electrode and the external terminal of the IC card LSI are electrically connected.

As described above, according to the IC card LSI incorporating the stabilized power supply circuit 100 according to the first and second embodiments, the current specification is limited by limiting an excessive inflow current to the IC card LSI. The effect of being surely satisfied is obtained.
Further, according to the IC card LSI incorporating the stabilized power supply circuit 100 according to the third to sixth embodiments, the internal power supply voltage (output voltage VDD1) jumps up due to the delay of the feedback operation of the stabilized power supply circuit 100. It is possible to reduce the jump and reliably prevent the destruction of the circuit element and the malfunction of the circuit.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the current limiting circuit 20 of the first embodiment, the jump prevention circuit 40 of the third embodiment, the clamp circuit 50 of the fifth and sixth embodiments,
Since 60 respectively independently acts on the stabilized power supply circuit 100, one stabilized power supply circuit may be provided with all of them. Also, by replacing the P-channel type MOS and the N-channel type MOS with each other, it is possible to construct a stabilized power supply circuit with the polarities reversed.

In the above description, the invention made by the present inventor has been mainly described with respect to the IC card LSI which is a field of use which is the background of the invention. However, the present invention is not limited to this, and includes a stabilized power supply circuit. Various LS
It can be widely used for I.

[0046]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, even if the allowable voltage range of the first power supply voltage supplied from the outside is wide, an excessive inflow current can be always limited, and the current specification can be surely satisfied. .

Further, even when the first power supply voltage supplied from the outside or the internal load changes abruptly, the second power supply voltage can be suppressed from jumping up or down as much as possible. There is an effect that it is possible to avoid problems such as exceeding the withstand voltage of the circuit element and remarkably decreasing the second power supply voltage to cause malfunction of the internal circuit.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a stabilized power supply circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of the circuit of FIG.

FIG. 3 is a circuit diagram showing a stabilized power supply circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit configuration diagram showing a stabilized power supply circuit according to a third embodiment of the present invention.

5 is a circuit diagram showing details of the circuit of FIG.

FIG. 6 is a circuit diagram showing a stabilized power supply circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit configuration diagram showing a stabilized power supply circuit according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing details of the circuit of FIG.

9 is a circuit diagram showing a modified example of the stabilized power supply circuit of FIG.

FIG. 10 is a circuit diagram showing a stabilized power supply circuit according to a sixth embodiment of the present invention.

11 is a circuit diagram showing a modified example of the stabilized power supply circuit of FIG.

FIG. 12 is a block diagram showing an overall configuration of an IC card LSI according to an embodiment of the present invention.

FIG. 13 is a circuit diagram showing an example of a stabilized power supply circuit provided in a conventional IC card LSI.

FIG. 14 is a waveform diagram showing characteristics of a conventional stabilized power supply circuit.

[Explanation of symbols]

11 Error amplifier 20 Current limiting circuit 30 time constant circuit 40 jump prevention circuit 42 Voltage comparator 50 clamp circuit 60 clamp circuit 100 stabilized power supply circuit Cf1 filter capacitor N1 clamp MOS P1 clamp MOS QO4 output control MOS transistor QD1, QD3 Current limiting MOS R1, R2 division resistance SW1, SW2 switch VDD input voltage (first power supply voltage) VDD1 output voltage (second power supply voltage)

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03K 17/16 G06F 1/00 330E 5J056 19/00 G06K 19/00 J (72) Inventor Shigeru Kadokawa 5-22-1 Mizumotocho, Hitachi Super L.S.I. Systems Co., Ltd. (72) Inventor Satoshi Matsumura 5-22-1 Kamisuihoncho, Kodaira-shi, Tokyo Hitachi Super L.S. Co., Ltd.・ F-Terms in i-Systems (reference) 2C005 MA10 MA25 MB02 MB10 NA02 QA15 5B011 DB02 EA06 5B035 BB09 CA12 5H420 BB12 CC02 DD02 EA12 FF03 FF23 LL05 5J055 AX25 AX32 AX39 BX01 CX00 DX22 EZOZE DX21 DX56 EX07 DX73 DX73 DX07 DX07 DX01 DX73 DX07 DX07 DX01 DX02 EZ10 EZ14 EZ16 FX19 FX38 GX01 GX02 GX04 GX05 5J056 AA00 BB22 BB40 BB45 CC02 CC06 CC09 CC12 DD13 DD29 DD51 DD59 EE05 EE07 GG08 GG09 KK01

Claims (5)

[Claims] 1. An output control MOSFET that receives a first power supply voltage supplied from the outside at a source terminal and outputs a second power supply voltage at a drain terminal, and a feedback voltage that changes according to the magnitude of the second power supply voltage. And a voltage comparison circuit for controlling the gate of the output control MOSFET so that the second power supply voltage becomes a standard voltage by comparing the feedback voltage with a reference potential. The stabilized power supply circuit comprises a current limiting MOSFET in which a source / drain is connected to a path in which the amount of current is limited and a gate terminal and a drain terminal are coupled, and the current limiting MOSFET. Switch for connecting the output MOSFET with the output control MOSFET in a current mirror, and turning on the switch when the power is turned on for a predetermined time. The semiconductor integrated circuit characterized by comprising a time constant circuit to the OFF state after. 2. An output control MOSFET that receives a first power supply voltage supplied from the outside at a source terminal and outputs a second power supply voltage at a drain terminal, and a feedback voltage that changes according to the magnitude of the second power supply voltage. And a voltage comparison circuit for controlling the gate of the output control MOSFET so that the second power supply voltage becomes a standard voltage by comparing the feedback voltage with a reference potential. A semiconductor integrated circuit comprising: the stabilized power supply circuit, wherein the stabilized power supply circuit changes in accordance with a switch transistor connected between a gate terminal and a source terminal of the output control MOSFET and the magnitude of the second power supply voltage. The feedback voltage and the reference potential are compared, and the switch transistor is turned on when the second power supply voltage exceeds a predetermined voltage higher than the standard voltage. The semiconductor integrated circuit characterized by comprising a second voltage comparator circuit. 3. An output control MOSFET that receives a first power supply voltage supplied from the outside at its source terminal and outputs a second power supply voltage at its drain terminal, and a feedback voltage that changes according to the magnitude of the second power supply voltage. And a voltage comparison circuit for controlling the gate of the output control MOSFET so that the second power supply voltage becomes a standard voltage by comparing the feedback voltage with a reference potential. In the semiconductor integrated circuit, the stabilized power supply circuit includes a voltage clamp unit that is connected to the output node of the feedback voltage and prevents the feedback voltage from becoming equal to or lower than a first voltage smaller than a standard time. And a semiconductor integrated circuit. 4. An output control MOSFET that receives a first power supply voltage supplied from the outside at a source terminal and outputs a second power supply voltage at a drain terminal, and a feedback voltage that changes according to the magnitude of the second power supply voltage. And a voltage comparison circuit for controlling the gate of the output control MOSFET so that the second power supply voltage becomes a standard voltage by comparing the feedback voltage with a reference potential. In the semiconductor integrated circuit, the stabilized power supply circuit includes a voltage clamp unit that is connected to the output node of the feedback voltage and prevents the feedback voltage from becoming equal to or higher than a second voltage higher than the standard time. And a semiconductor integrated circuit. 5. The semiconductor integrated circuit according to any one of claims 1 to 4 is mounted, and predetermined terminals of the semiconductor integrated circuit are electrically connected to external connection terminals formed on a card surface. The IC card is configured so that the first power supply voltage is supplied from the external connection terminal to the semiconductor integrated circuit.