JP4156863B2 - Semiconductor integrated circuit and IC card - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique that is useful when applied to a semiconductor integrated circuit having a stabilized power supply circuit that receives an external power supply voltage and obtains a predetermined internal power supply, and is particularly used for an LSI (large scale integrated circuit) for an IC card. And particularly useful technology.
[0002]
[Prior art]
An IC card in which an IC (integrated circuit) chip is embedded may be used for recording various kinds of information in a credit card or a public telephone prepaid card. There are two types of IC cards, a contact type and a non-contact type. In the contact type IC card, input / output of power supply voltage and information is performed via terminal pads formed on the card surface.
In the contact type IC card, it is necessary to widen the input external power supply to 1.8 to 5 V in order to support a plurality of generation readers, and the IC chip is necessary for the internal circuit from such an external power supply. Generally, a stabilized power supply circuit that generates an internal power supply voltage is provided.
[0003]
As a stabilized power supply circuit for an IC card, for example, as shown in FIG. 13, an output control MOS transistor that receives an input voltage VDD as an external power supply at a source terminal and outputs a voltage VDD1 supplied as an internal power supply to a drain terminal. QO4 is compared with the feedback voltage Vret obtained by dividing the output voltage VDD1 and the reference voltage Vref to control the gate of the output control MOS transistor QO4, and is connected to the output terminal of the error amplifier 11 and its output In order to increase the current control range, a circuit including an amplifier circuit 12 including an N-channel drive MOSFET (hereinafter referred to as NMOS) QD2 having a common source and a constant current source QI is used.
[0004]
[Problems to be solved by the invention]
However, in the above-described conventional stabilized power supply circuit, the output control MOS transistor QO4 is in an ON state at the start of power supply. Therefore, when a large voltage is applied as an external power supply, the voltage smoothing filter capacitor Cf1 is applied. There is a risk that the current flowing into the IC increases and exceeds the current specifications set for the reading device and the IC card. In particular, when the source-grounded N-channel type MOS QD2 is used in the above driving stage, the gate voltage of the output control MOS transistor QO4 becomes almost 0V until the output voltage VDD1 is stabilized, and the drain current is in the maximum state. It will be retained. Even if the filter capacitor Cf1 is not provided, various parasitic capacitances are generated in the internal circuit, and the same phenomenon occurs.
[0005]
In addition, in order to reduce the number of components in the IC card, the voltage smoothing filter capacitor Cf1 must also be provided in the chip. Therefore, the capacity cannot be increased so much that the fluctuation of the internal circuit load and the input voltage VDD are affected by the filter capacitor Cf1. It was not able to absorb much. Therefore, if the response of the entire feedback circuit including the error amplifier 11 and the drive circuit 12 is poor, as shown in FIG. 14A, the output voltage VDD1 rapidly drops when the load of the internal circuit fluctuates rapidly. Or the problem of jumping up. In addition, as shown in FIG. 14B, there is a problem that the output voltage VDD jumps even when the input voltage VDD changes rapidly. Such a drop in the output voltage VDD1 may cause the internal circuit to malfunction depending on the magnitude of the drop, while a jump in the output voltage VDD1 may cause element destruction.
[0006]
The output control MOS transistor QO4 needs to have a large element size in order to cope with the input voltage VDD having a wide allowable range. As a result, since the gate capacitance increases, the driving force of the driving circuit must be increased to increase the response speed of the feedback operation. However, there is a trade-off relationship that increasing the driving force increases the power consumption of the driving circuit and thus the power consumption of the entire IC chip. Therefore, the driving force cannot be increased so much and the response of the feedback operation is reduced. There was a problem that it could not be raised sufficiently.
[0007]
In addition, the driving force can be increased by applying a push-pull type driving circuit to the driving stage, but when a push-pull type driving circuit is provided at the subsequent stage of the differential amplifier, the driving MOS on the push side is It can be driven by the positive phase output of the differential amplifier, but to drive the pull-side drive MOS, it is necessary to use the negative phase output of the differential amplifier with a level shift, and the circuit configuration becomes complicated by the level shift, The response speed decreases due to the circuit delay.
[0008]
An object of the present invention is to provide an IC card LSI having a stabilized power supply circuit capable of avoiding an excessive current flowing at the start of power supply.
Another object of the present invention is to provide an IC card LSI having a stabilized power supply circuit capable of avoiding a sudden up-and-down movement of the output voltage VDD1 even when the load of the external power supply or the internal circuit suddenly fluctuates. There is.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, the output control MOSFET that generates the second power supply voltage (internal power supply) by inputting the first power supply voltage (external power supply), and the gate of the output control MOSFET by comparing the feedback voltage related to the internal power supply with the reference potential. In a stabilized power circuit having a voltage comparator for controlling the current, a current limiting MOSFET connected to a path in which the amount of current is limited, a switch for connecting the current limiting MOSFET to the output control MOSFET in a current mirror, and And a time constant circuit for turning on the switch for a certain period from when the power is turned on. As a result, it is possible to prevent an excessive current from flowing when the power is turned on (at the start of power supply).
[0010]
Further, the switch transistor for forcibly turning off the output control MOSFET is compared with the feedback voltage related to the internal power supply and the reference potential, and the switch transistor is turned on when the internal power supply exceeds a predetermined voltage higher than the standard voltage. And a second voltage comparison circuit. With this configuration, it is possible to compensate for the insufficient response speed of the feedback circuit and suppress a large jump of the internal power supply.
[0011]
Further, voltage clamping means for preventing the feedback voltage from swinging beyond a certain voltage width is provided at the output node of the feedback voltage. In a conventional stabilized power supply circuit, for example, when the load of the external power supply or internal circuit deviates from the standard state, the feedback voltage drops extremely, and then immediately after the external power supply or internal load returns to the standard state, the feedback circuit Due to this delay, the external power supply and the internal load are in the standard state and the feedback voltage is extremely lowered, which may cause a reaction phenomenon in which the internal power supply is flipped up to the opposite side. With the above configuration, this reaction phenomenon can be reduced.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
FIG. 1 is a circuit configuration diagram showing a stabilized power supply circuit according to a first embodiment of the present invention, and FIG. 2 is a more detailed circuit diagram of this circuit.
The stabilized power supply circuit 100 is suitable for being built in an IC card LSI (large scale integrated circuit), and receives an input voltage VDD as a first power supply voltage supplied from the outside and supplies it to an internal circuit. The output voltage VDD1 as the second power supply voltage is generated.
[0013]
The circuit configuration includes an output control MOS transistor QO4 that receives the input voltage VDD at the source terminal and outputs the output voltage VDD1 to the drain terminal, and divided resistors R1 and R2 that divide the output voltage VDD1 to generate the feedback voltage Vret (feedback circuit). ), A voltage smoothing filter capacitor Cf1, an error amplifier 11 as a voltage comparison circuit for amplifying a difference voltage between the feedback voltage Vrt and the reference voltage Vref, a constant current source QI and an N-channel type driving MOS QD2. A single-ended drive stage that receives the output of the error amplifier 11 and drives the gate of the output control MOS transistor QO4, a current limiting circuit 20 for limiting the inflow current at the start of supply of the input voltage VDD, and a current limiting circuit A time constant circuit 30 (see FIG. 2) for generating control signals for the 20 switches SW1 and SW2 is provided. It is a thing.
[0014]
The current limiting circuit 20 includes an NMOS QD1 and a switch SW1 that limit the current flowing through the NMOS QD2 in the driving stage, and a PMOS QD3 and a switch SW2 as a current limiting MOSFET that limits the current flowing through the output control MOS transistor QO4. The These first NMOS QD1 and PMOS QD3 act only when the switches SW1 and SW2 are in the on state, and have no effect on the circuit when the switch is in the off state.
[0015]
The NMOS QD1 of the current limiting circuit 20 has a source terminal connected to the ground, a drain terminal connected to the output terminal of the error amplifier 11 and the connection node n1 of the driving MOS QD2 via the switch SW1, and the gate and drain are coupled. The When the switch SW1 is turned on, the output current IoE from the error amplifier 11 is caused to flow to the ground. Also, since the switch SW1 is turned on to make a current mirror connection with the driving MOS QD2, the current of the driving MOS QD2 is limited to a value obtained by multiplying the output current IoE by the mirror ratio. The output current IoE is limited to be equal to or less than the operating current supplied by the constant current MOS Q2 of the error amplifier 11.
[0016]
That is, if the mirror ratio between the NMOS QD1 and the driving MOS QD2 of the current limiting circuit 20 is a: b, the drain current IQD2 of the driving MOS QD2 when the switch SW1 is in the on state is expressed by the following equation (1). .
IQD2 = IoE × (b / a) (1)
[0017]
In the PMOS QD3 of the current limiting circuit 20, the source terminal is connected to the external power supply line to which the input voltage VDD is applied, and the drain terminal is connected to the drain terminal of the driving MOS QD2 and the gate terminal of the output control MOS transistor QO4 via the switch SW2. Connected to the node n2, and the gate and drain are coupled. When the switch SW2 is turned on, a limited current flows between the source and drain of the PMOS QD3. Further, when the switch SW1 is turned on, the output control MOS transistor QO4 is connected to the current mirror, and the current flowing through the output control MOS transistor QO4 is limited to a value obtained by multiplying the current flowing through the PMOS QD3 by the mirror ratio.
[0018]
More specifically, since the current flowing through the PMOS QD3 becomes (IQD2-IoD) when the switches SW1 and SW2 are on, the mirror ratio between the PMOS QD3 of the current limiting circuit 20 and the output control MOS transistor QD4 is c: If d, the current IQD4 flowing through the output control MOS transistor QO4 is limited as shown in the following equation (2).
IQD4 = {IoE × (b / a) −IoD} × (d / c) (2)
[0019]
As shown in FIG. 2, the switches SW1 and SW2 of the current limiting circuit 20 are composed of MOS transistors, and control signals from the time constant circuit 30 are input to the gates thereof. The time constant circuit 30 turns on the switches SW1 and SW2 only during a period determined by the resistor R30 and the capacitor C30 from the start of application of the input voltage VDD, and turns off the switches SW1 and SW2 after the above period has elapsed. The period during which the switches SW1 and SW2 are turned on is preferably set to such a length that the output voltage VDD1 is sufficiently stable when the filter capacitor Cf1 is charged with the limited current IQD4 flowing through the output control MOS transistor QO4. This time T is expressed by the following equation (3).
T> (Cf1 × VDD1) / IQD4 (3)
However, VDD1 = Vref × {R2 / (R2 + R1)}
[0020]
With the above configuration, since the inflow current that flows into the internal circuit of the IC card LSI when the supply of the input voltage VDD is started is limited, the current specifications set for the IC card and its reader are surely satisfied. I can do it. Then, when the current becomes stable, the action of the current limiting circuit 20 is quickly released, and the normal operation of the stabilized power supply circuit 100 is obtained.
[0021]
[Second Embodiment]
FIG. 3 is a circuit diagram of a stabilized power circuit according to the second embodiment of the present invention.
This stabilized power supply circuit 100 does not use the active load MOSs Q5 and Q6 as shown in FIG. 2 to generate the output of the error amplifier 11, but uses a single load MOS Q6a to output the current mirror output. Is the output of the error amplifier 11. Therefore, the current of the driving MOS QD2 that receives the output of the error amplifier 11 is limited to a value obtained by multiplying the current of the load MOS Q6a by the mirror ratio.
[0022]
Therefore, in the current limiting circuit 20a of the second embodiment, the configuration for limiting the current of the driving MOS QD2 is omitted as compared with the circuit of the first embodiment of FIG. 2, and the PMOS for limiting the current of the output control MOS transistor QO4 is omitted. Only the QD3 and the switch SW2 for operating the QD3 are configured.
[0023]
In the stabilized power supply circuit 100 according to the second embodiment, the circuit configuration is simple and the number of circuit elements is reduced as compared with the circuit of the first embodiment. However, the error amplifier 11, the drive stage, and the output control MOS transistor QO4 Since the total gain is low, the circuit of the first embodiment is superior in terms of stable power supply performance.
[0024]
[Third embodiment]
FIG. 4 shows a circuit configuration diagram of a stabilized power circuit according to the third embodiment of the present invention, and FIG. 5 shows a more detailed circuit diagram of this circuit.
The stabilized power supply circuit 100 according to the third embodiment is provided with a configuration for preventing the output voltage VDD1 supplied to the internal circuit from greatly jumping up. As a result, even when the input voltage VDD or the load on the internal circuit changes suddenly, problems such as the output voltage VDD1 exceeding the withstand voltage of the internal circuit can be avoided.
[0025]
The stabilized power supply circuit 100 is a voltage comparator 42 as a second voltage comparison circuit that detects that the output voltage VDD1 has exceeded a predetermined limit voltage that is higher than the standard voltage, as a jump prevention circuit 40 for the output voltage VDD1. And a switch MOS transistor Q13 for connecting the gate terminal and the source terminal of the output control MOS transistor QO4. As shown in FIG. 5, the voltage comparator 42 is composed of a conductive MOSFET opposite to each MOSFET constituting the error amplifier 11 in order to drive the PMOS Q13.
[0026]
The voltage comparator 42 performs the above detection by comparing the second feedback voltage Vret2 obtained by resistance-dividing the output voltage VDD1 with the reference voltage Vref. The resistance division ratio of the second feedback voltage Vret2 is set so that the voltage is lower than the feedback voltage Vret input to the error amplifier 11, so that the operation start points of the error amplifier 11 and the voltage comparator 42 are shifted. ing. Since the resistance ratio can be formed without variation in the semiconductor manufacturing process, the relationship between the operation start point of the voltage comparator 42 and the operation start point of the error amplifier 11 should not be affected by variations in the manufacturing process. I can do it.
[0027]
According to the stabilized power supply circuit 100 provided with such a jump prevention circuit 40, when the input voltage VDD or the load of the internal circuit fluctuates rapidly, the output voltage VDD1 is likely to greatly jump and exceed the limit voltage. In addition, since the voltage comparator 42 detects it and quickly short-circuits the gate and source of the output control MOS transistor QO4, the output control MOS transistor QO4 is turned off to prevent the output voltage VDD1 from jumping greatly. I can do it.
In order to shift the operation start points of the error amplifier 11 and the voltage comparator 42, the same feedback voltage Vret is input to both, while two types of reference voltages are generated and different ones are input to each. You may do it.
[0028]
[Fourth embodiment]
FIG. 6 shows a circuit diagram of a stabilized power circuit according to the fourth embodiment of the present invention.
In the stabilized power supply circuit 100 of the fourth embodiment, in order to make the operation start point of the voltage comparator 42 different from that of the error amplifier 11, instead of changing the voltage to be compared, the voltage comparator 42 performs differential input. This is realized by making the element sizes of the two input MOSs Q10a and Q11a different between positive and negative, and the same operation as in the third embodiment can be obtained.
[0029]
[Fifth embodiment]
FIG. 7 is a circuit configuration diagram of a stabilized power supply circuit according to the fifth embodiment of the present invention, and FIG. 8 is a more detailed circuit diagram of this circuit.
In the stabilized power supply circuit 100 of the fifth embodiment, the clamp circuit 50 is added to the same configuration as the conventional stabilized power supply circuit so that the feedback voltage Vret does not become lower than the clamp voltage (first voltage) smaller than the standard time. It is a thing.
[0030]
The clamp circuit 50 includes an N-channel clamp MOS N1 connected between the output line of the feedback voltage Vret and the power supply line to which the input voltage VDD is applied, and a reference voltage supplied to the gate terminal of the clamp MOS N1. The circuit includes a resistor R50, a capacitor C50, and the like that delay the transmission of the fluctuation to the gate terminal when the fluctuation occurs in the Vref2 and the reference voltage Vref2.
[0031]
The clamp MOS N1 is turned off and does not act when the feedback voltage Vret is a standard voltage, but is turned on and exerts a clamping action when the feedback voltage Vret falls below a certain value (= gate potential Vg−threshold voltage Vth). It is like that. That is, when the output voltage VDD1 and the feedback voltage Vret temporarily drop due to a sudden change in the input voltage VDD or the internal load, the clamp MOS N1 is turned on and the feedback voltage Vret is set to a predetermined voltage (reference voltage Vref2 -Clamp to threshold voltage Vth).
[0032]
In addition, an abrupt change in the input voltage VDD or the internal load for turning on the clamp MOS N1 may appear as a change in the reference voltage Vref2, but the change in the reference voltage Vref is a time constant circuit of the resistor R50 and the capacitor C50. Because of this, the signal is not immediately transmitted to the gate of the clamp MOS N1, so that it is always possible to clamp at a predetermined voltage against a temporary drop in the feedback voltage Vret.
[0033]
According to the stabilized power supply circuit 100 to which such a clamp circuit 50 is added, when the input voltage VDD or the internal load fluctuates temporarily temporarily and there is a fluctuation that immediately returns to the original level, As described above, the fluctuation of the output voltage VDD1 can be suppressed.
[0034]
In general, for example, when the input voltage VDD fluctuates like a pulse once such that it once becomes smaller than the standard voltage and immediately returns to the original standard voltage, first, the output voltage VDD1 becomes small because the input voltage VDD becomes small. Accordingly, the feedback voltage Vret decreases. The lowering of the feedback voltage Vret is fed back by the feedback circuit so that the gate of the output control MOS transistor QO4 is further opened. However, since there is a delay in the feedback operation by the error amplifier 11 and the drive stage, when the control for opening the gate is performed, the input voltage VDD has already returned to the original standard voltage, and the output voltage VDD1 is reversed from the standard time. The reaction phenomenon of rising will occur.
[0035]
In such a case, if the above-described clamp circuit 50 is not provided, if the temporary decrease in the input voltage VDD is very large, the accompanying decrease in the feedback voltage Vret also becomes very large. The bounce will also increase.
[0036]
On the other hand, when the clamp circuit 50 is added, even when the input voltage VDD temporarily decreases significantly, the decrease in the feedback voltage Vret can be suppressed to a constant level. The rebound of VDD1 can also be suppressed below a certain value.
[0037]
FIG. 9 shows another circuit example of the stabilized power supply circuit to which the clamp circuit is added. As shown in the figure, this embodiment is obtained by removing the resistor R50 and the capacitor C50 from the clamp circuit 50 of FIG. 8. However, the well 6 has a variation in the input voltage VDD and the internal load to the reference voltage Vref3. This is effective in the case of a circuit configuration that does not affect much.
[0038]
[Sixth embodiment]
FIG. 10 is a circuit diagram of a stabilized power circuit according to the sixth embodiment of the present invention.
The stabilized power supply circuit 100 according to the sixth embodiment includes, as a clamp circuit 60, a P-channel clamp MOS P1 connected between the output line of the feedback voltage Vret and the ground GD, and a gate terminal of the clamp MOS P1. A reference voltage Vref3 to be supplied, and a resistor R60 and a capacitor C60 that delay the transmission of the fluctuation to the gate terminal when the fluctuation occurs in the reference voltage Vref3 are provided.
[0039]
While the clamp circuit according to the fifth embodiment did not reduce the feedback voltage Vret below a certain value, the clamp circuit according to the sixth embodiment has a clamp voltage (second voltage) higher than the standard time. (Voltage) is not raised more than. According to this clamp circuit, when the output voltage VDD1 jumps up in a pulse due to a sudden change in the input voltage VDD or the internal load, the output voltage VDD1 is prevented from greatly decreasing due to the reaction next. I can do it.
[0040]
FIG. 11 shows another circuit example of the stabilized power supply circuit to which the clamp circuit is added. As shown in the figure, this embodiment is obtained by removing the resistor R60 and the capacitor C60 from the clamp circuit 60 of FIG. 10, but in this circuit, the fluctuation of the input voltage VDD and the internal load greatly affects the reference voltage Vref3. This is effective in the case of a circuit configuration that does not.
[0041]
FIG. 12 is a block diagram showing the overall configuration of an IC card LSI in which the stabilized power supply circuit is incorporated.
An IC card LSI according to an embodiment of the present invention includes the above-described stabilized power supply circuit 100, a power-on reset circuit 110 that resets the microcomputer 100 at the start of application of the input voltage VDD, a CPU 121, a nonvolatile memory 122, a RAM 123, A microcomputer 120 having a coprocessor 125 or the like that assists the functions of the ROM 124 and the CPU 121, and a voltage conversion circuit 130 that performs voltage conversion between an external signal and an internal signal are generated by the stabilized power supply circuit 100. The output voltage VDD1 (internal power supply voltage) is supplied as the operating voltage of the microcomputer 120.
[0042]
This IC card LSI is different from PCMCIA standard PC cards that allow multiple external components such as LSIs and capacitors to be mounted inside, and is not used for credit cards or telephones that do not require external components. Suitable for embedding in thin cards such as prepaid cards. The IC card of the embodiment of FIG. 12 has a terminal electrode on the surface, and is configured as a contact IC in which this terminal electrode and an external terminal of the IC card LSI are electrically connected.
[0043]
As described above, according to the IC card LSI incorporating the stabilized power supply circuit 100 according to the first and second embodiments, an excessive inflow current to the IC card LSI is limited and the current specification is reliably satisfied. The effect that it is said. Further, according to the IC card LSI incorporating the stabilized power supply circuit 100 according to the third to sixth embodiments, the internal power supply voltage (output voltage VDD1) jumps up based on the feedback operation delay of the stabilized power supply circuit 100. It is possible to reduce the jumping down and reliably prevent the destruction of the circuit element and the malfunction of the circuit.
[0044]
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
For example, the current limiting circuit 20 of the first embodiment, the jump prevention circuit 40 of the third embodiment, and the clamp circuits 50 and 60 of the fifth and sixth embodiments are independent of the stabilized power circuit 100, respectively. Therefore, a single stabilized power supply circuit may be provided with all of them.
Further, by replacing the P channel type MOS and the N channel type MOS, a stabilized power supply circuit having a reversed polarity can be configured.
[0045]
In the above description, the IC card LSI, which is the field of use behind the invention made by the present inventor, has been described. However, the present invention is not limited thereto, and various LSIs having a stabilized power supply circuit can be used. Can be widely used.
[0046]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, even if the allowable voltage range of the first power supply voltage supplied from the outside is wide, an excessive inflow current can always be limited and the current specification can be surely satisfied. .
[0047]
Even when the first power supply voltage supplied from the outside or the internal load suddenly fluctuates, the second power supply voltage supplied to the internal circuit is suppressed from jumping up or down as much as possible. There is an effect that it is possible to avoid problems such as exceeding the withstand voltage or causing a malfunction of the internal circuit due to a significant decrease in the second power supply voltage.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing a stabilized power circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing details of the circuit of FIG. 1;
FIG. 3 is a circuit diagram showing a stabilized power circuit according to a second embodiment of the present invention.
FIG. 4 is a circuit configuration diagram showing a stabilized power supply circuit according to a third embodiment of the present invention.
FIG. 5 is a circuit diagram showing details of the circuit of FIG. 4;
FIG. 6 is a circuit diagram showing a stabilized power circuit according to a fourth embodiment of the present invention.
FIG. 7 is a circuit configuration diagram showing a stabilized power circuit according to a fifth embodiment of the present invention.
FIG. 8 is a circuit diagram showing details of the circuit of FIG. 7;
9 is a circuit diagram showing a modification of the stabilized power supply circuit of FIG.
FIG. 10 is a circuit diagram showing a stabilized power circuit according to a sixth embodiment of the present invention.
11 is a circuit diagram showing a modification of the stabilized power supply circuit of FIG.
FIG. 12 is a block diagram illustrating an overall configuration of an IC card LSI according to an embodiment of the present invention.
FIG. 13 is a circuit diagram showing an example of a stabilized power supply circuit provided in a conventional IC card LSI.
FIG. 14 is a waveform diagram showing characteristics of a conventional stabilized power supply circuit.
[Explanation of symbols]
11 Error amplifier 20 Current limit circuit 30 Time constant circuit 40 Jump-up prevention circuit 42 Voltage comparator 50 Clamp circuit 60 Clamp circuit 100 Stabilized power supply circuit Cf1 Filter capacitor N1 Clamp MOS
P1 clamp MOS
QO4 output control MOS transistors QD1, QD3 Current limiting MOS
R1, R2 Dividing resistors SW1, SW2 Switch VDD Input voltage (first power supply voltage)
VDD1 output voltage (second power supply voltage)

Claims (2)

An output control MOSFET that receives the first power supply voltage supplied from the outside at the source terminal and outputs the second power supply voltage to the drain terminal, and a feedback circuit that generates a feedback voltage that changes according to the magnitude of the second power supply voltage. And a voltage comparison circuit that controls the gate of the output control MOSFET so that the second power supply voltage becomes a standard voltage by comparing the feedback voltage with a reference potential, and a semiconductor integrated circuit including a stabilized power supply circuit Because
The stabilized power supply circuit includes a current limiting MOSFET in which a source and a drain are connected to a path in which a current amount is limited and a gate terminal and a drain terminal are coupled, and the current limiting MOSFET is connected to the output control MOSFET and a current. A semiconductor integrated circuit comprising: a switch that can be mirror-connected; and a time constant circuit that turns on the switch when power is turned on and turns it off after a predetermined time has elapsed. The semiconductor integrated circuit according to claim 1 is mounted, a predetermined terminal of the semiconductor integrated circuit is electrically connected to an external connection terminal formed on the card surface, and the first power supply voltage is set to the external An IC card configured to be supplied from a connection terminal to the semiconductor integrated circuit .

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