JP2889706B2 - Power-on reset circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit which is mainly incorporated in an integrated circuit or the like and sends out a reset signal when a power supply voltage reaches a predetermined level when power is turned on.

[0002]

2. Description of the Related Art Conventionally, as this kind of power-on reset circuit, as shown in FIG. 4, a constant voltage circuit 3 which outputs a constant voltage when a power supply voltage is applied, and an output voltage of the constant voltage circuit 3 A first switch element Q9 that is turned on when a predetermined level is reached, a second switch element Q10 that is connected in series to the first switch element Q9 and is turned on when the power supply voltage reaches a predetermined level; And a Schmitt trigger 4 that sends out a reset pulse when the power supply voltage reaches a predetermined level when the power supply is turned on based on a change in the potential of the connection point with the switch element Q10.

The constant voltage circuit 3 is composed of a pair of n-channel MOS transistors Q7 and Q8 connected between the drain and the gate, and a resistor R2. MOS
Transistor Q7, Q8 is, the drain-to-source What happened are connected in series, the resistor R2 is connected to the drain of the MOS transistor Q7. A power supply voltage is applied to a series circuit of the MOS transistors Q7, Q8 and the resistor R2. Therefore, when the power supply voltage reaches a predetermined level after the power is turned on, the potential at the connection point between MOS transistor Q7 and resistor R2 becomes substantially constant regardless of the power supply voltage.

On the other hand, the first switch element Q9 is a p-channel MO to which the output of the constant voltage circuit 3 is applied to the gate.
The second switch element Q10 is an n-channel MOS transistor having a drain connected to the drain of the first switch element Q9. First
The series circuit of the switching element Q9 and the second switching element Q10 is connected between both ends of the power supply, and the gate of the second switching element Q10 is connected to the positive electrode of the power supply.

Therefore, immediately after the power is turned on , the power supply voltage becomes
It exceeds the threshold voltage of the second switching element Q10, a second switching element Q10 is turned on, at this point M
OS transistors Q7 and Q8 have not been turned on yet
From the gate voltage of the first switch element Q9 to the power supply voltage.
Become substantially equal, and the first switching element Q9 is kept off.
It is. Therefore, the input of Schmitt trigger 4 is L level.
It becomes Le. In addition, the power supply voltage rises and MOS transistors
When static Q7, Q8 are turned on so that the output from the constant-voltage circuit 3 is obtained, the voltage applied to the Gate of the first switching element Q 9 is substantially constant. Therefore, the first
I large gate-to-source voltage of the switch element Q9 is
Ri first switch element Q9 is ing on. The first switch
Channel between the switching element Q9 and the second switching element Q10.
By selecting appropriate values for width, channel length, etc.
When the power supply voltage exceeds a certain value, the Schmitt trigger 4
Input voltage gradually rises and Schmitt trigger input
Threshold voltage is exceeded. As a result, the output of the Schmitt trigger 4 is inverted and the reset signal is output.
Because That is, when the power supply voltage reaches a predetermined level after the power is turned on, the reset signal is output from the Schmitt trigger 4.

[0006]

In the above configuration, as shown in FIG. 5, the current Ic flowing through the constant voltage circuit 3 and the current Id flowing through the first switch element Q9 and the second switch element Q10 are: Both will change with the change of the power supply voltage. That is, when the power supply voltage increases, the currents Ic and Id increase, and when the power supply voltage is high, there is a problem that power consumption increases.

An object of the present invention is to provide a power-on reset circuit that consumes less power even when the power supply voltage is high.

[0008]

According to the present invention, a constant current circuit provided with a first MOS transistor whose drain current becomes constant when a power supply voltage reaches a predetermined level, and a current mirror together with the first MOS transistor are provided. a second MOS transistor constituting a third MOS transistor having a drain-source-drain-gate is connected to the series circuit connected in series with the drain-source of the second MOS transistor is connected to the power supply , The third MOS
A comparator that sends a reset signal when the power supply voltage reaches a predetermined level when the power is turned on, based on a magnitude relationship between a potential of a connection point between the transistor and the second MOS transistor and a gate voltage of the second MOS transistor. It is doing.

[0009]

According to the above arrangement, the constant current circuit having the first MOS transistor, the drain current of which becomes constant when the power supply voltage reaches the predetermined level, and the second current circuit, which forms a current mirror together with the first MOS transistor, are provided. Since the MOS transistor is provided, a constant current also flows through the second MOS transistor. Here, the third M of the drain-source between the drain and gate connected is series connected to the drain-source of the second MOS transistor
Since the potential of the connection point between the OS transistor and the second MOS transistor is compared with the gate voltage of the second MOS transistor to output a reset signal,
If the power supply voltage becomes higher than the voltage at which the reset signal can be output, the supplied current does not change even if the power supply voltage changes, and the power consumption does not increase.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, basically, a constant current circuit 1 having a first MOS transistor Q1 whose drain current becomes constant when a power supply voltage reaches a predetermined level;
A second MOS transistor Q2 forming a current mirror together with the second MOS transistor Q1;
A third MOS transistor Q3 connected in series with the drain-source of the transistor Q2, configured by a comparator 2 for comparing the gate voltage and the drain voltage of the second MOS transistor Q2.

The constant current circuit 1 has two n-channel M
It comprises OS transistors Q1 and Q4, two p-channel MOS transistors Q5 and Q6, and a resistor R1. Drain and the source of the MOS transistor Q1, Q5
They are connected in series. Also, the MOS transistors Q4, Q
6 the drain and the source of with are connected in series, MO
The resistor R1 is connected to the source of the S transistor Q4.
The gates of the MOS transistors Q1, Q4 and the MOS transistors Q5, Q6 are connected to each other.
The MOS transistors Q1 and Q6 are connected between the gate and the drain. Here, each M
The channel widths and the channel lengths of the OS transistors Q1, Q4, Q5, Q6 are W1, W4,.
.. L1, L4,..., The drain current Ia of the transistor Q4 is expressed by the following equation. That is, Ia = {(W5 / L5) / (W6 / L6) -1} / (kR1. (W1 / L1)). Here, k is a constant. As is apparent from this equation, the drain current of the MOS transistor Q4 becomes constant regardless of the power supply voltage. Further, since the connection relation is set so that the drain currents of the MOS transistors Q1, Q4, Q5, Q6 are equal, the drain current of the MOS transistor Q1 is also constant irrespective of the power supply voltage.

By the way, the MOS transistor Q2 has n
This is a channel and forms a current mirror together with the MOS transistor Q1. That is, the gate and the drain of the MOS transistor Q1 are connected as described above, and the gate and the source are commonly connected to the MOS transistor Q2. Therefore, in the steady state, the drain current Ib of the MOS transistor Q2 is given by Ib = Ia. (W2 / L2) / (W5 / L5) where the channel width of the MOS transistor Q2 is W2 and the channel length is L2. . Since the current Ia was independent of the power supply voltage,
The current Ib is also independent of the power supply voltage, and has a substantially constant value.

The drain of the MOS transistor Q2 has
A third p-channel MOS transistor is connected. The drain and source of the MOS transistor Q3 are connected, and if the threshold voltage of the MOS transistor Q3 is Vth, the gate-source voltage of the MOS transistor Q3 is 2 · Ib + Vth. That is, M
Assuming that the power supply voltage is Vdd, the drain voltage VD of the OS transistor Q2 is VD = Vdd−2 · Ib−Vth. On the other hand, the gate voltage V of the MOS transistor Q2
G becomes VG = 2 · Ia + Vth. As described above, since the currents Ia and Ib become substantially constant when the power supply voltage is in a steady state, they change as shown in FIG. Further, as shown in the above equation, the drain voltage VD of the MOS transistor Q2 rises with the power supply voltage, and the gate voltage VG does not depend on the power supply voltage, and thus changes as shown in FIG. That is, when the power is turned on and the power supply voltage rises, first, the gate voltage VG becomes constant, and then the drain voltage VD
Becomes higher than the gate voltage VG.

The comparator 2 has MO as a reference voltage.
The gate voltage VG of the S transistor Q2 is input, and the drain voltage VD of the MOS transistor Q2 is used as a comparison voltage.
Is entered. Therefore, when the power supply voltage reaches a predetermined level after power-on and the drain voltage VD becomes higher than the gate voltage VG, the output level of the comparator 2 is inverted and a reset pulse is transmitted. Here, since the currents Ia and Ib do not depend on the power supply voltage in the steady state, the currents become constant even when the power supply voltage increases, so that an increase in power consumption can be prevented.

[0015]

As described above, according to the present invention, the first MO in which the drain current becomes constant when the power supply voltage reaches a predetermined level is obtained.
A constant current circuit having an S transistor, and a second M that forms a current mirror together with the first MOS transistor.
Since the OS transistor is provided, a constant current also flows through the second MOS transistor. Here, the potential at the connection point between the third MOS transistor and a second MOS transistor having a drain-source-drain-gate connected is series connected to the drain-source of the second MOS transistor, the Since the reset signal is output in comparison with the gate voltage of the second MOS transistor, if the power supply voltage becomes higher than the voltage at which the reset signal can be output, the current that is supplied even if the power supply voltage changes Has the advantage that the power consumption does not increase.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment.

FIG. 2 is an operation explanatory diagram of the embodiment.

FIG. 3 is an operation explanatory diagram of the embodiment.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is an operation explanatory diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Constant current circuit 2 Comparator Q1 1st MOS transistor Q2 2nd MOS transistor Q3 3rd MOS transistor

Claims (1)

(57) [Claims] 1. A constant current circuit comprising a first MOS transistor having a constant drain current when a power supply voltage reaches a predetermined level; and a second MOS transistor forming a current mirror together with the first MOS transistor. a third MOS transistor connected in series the series circuit to the drain-source between the drain and gate is connected to the drain-source <br/> second MOS transistor is connected to the power supply, the third MOS transistor and second MO
A comparator for transmitting a reset signal when the power supply voltage reaches a predetermined level when the power supply is turned on, based on a magnitude relationship between a potential at a connection point with the S transistor and a gate voltage of the second MOS transistor. Characteristic power-on reset circuit.