JP2570523B2 - Current detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current detection circuit. More specifically, the present invention relates to a high-precision current detection circuit that uses a power MOSFET and detects that an output current exceeds a maximum allowable value and shuts off the MOSFET.

[0002]

2. Description of the Related Art Conventionally, there has been a circuit as shown in FIG. 1 as a power supply IC using a power MOSFET or a current detection circuit for a motor driver. As shown in the figure,
The current detection circuit 10 comprises two parallel n-channel MOSFET transistors M1, made in a monolithic device,
M2. MOS for detection which is the first transistor
The drain electrode of the FET transistor M1 is connected to the output terminal Po receiving the output current (load current) Io, the gate electrode is connected to the input signal terminal Vg, and the source electrode is connected to the ground via the monitor resistor Rm. Power MOSFET transistor M as a second transistor
2, the transistor M1 has a drain electrode connected to the output terminal Po and a gate electrode connected to the input signal terminal Vg, similarly to the transistor M1. The source electrode of transistor M2 is directly connected to ground. As described above, by dividing the output current Io into the power section and the detection section, the monitor resistor Rm can be inserted and used for detection. The current detection circuit 10 also has a voltage comparator COMP. The non-inverting input terminal of the voltage comparator COMP receives the voltage Vm from a node between the source electrode of the first transistor M1 and the monitor resistor Rm. Voltage comparator COM
The inverting input terminal of P inputs the reference voltage Vrf from the positive electrode of the reference voltage source whose negative electrode is grounded.

[0003] The operation of the current detection circuit 10 will be described below. Generally, MOSFET drain current Id
Is approximately expressed by the following equation in an operation region where Vds is extremely smaller than Vgs.

Id = K.W / L. (Vgs-Vth) Vds where K is a proportionality constant, W / L is the width versus length of the channel,
Vgs is a gate-source voltage, Vth is a threshold voltage, and Vds is a drain-source voltage.

Assuming that the value of the monitor resistor Rm is sufficiently small, the current I flowing when the transistor M1 is on is
The value of the voltage drop Vm (= I1.Rm) of Rm due to 1 is the drain-source ON voltage Vds of the transistor M1.
Can be ignored compared to. If this condition is satisfied, Vds and Vgs of both FET transistors M1 and M2 can be regarded as equal in the above equation. Since the threshold voltages Vth of the two transistors M1 and M2 can be considered to be substantially equal, the ratio I2 / I1 of the drain current I2 of the FET transistor M2 and the drain current I1 of the FET transistor M1 becomes I2 / I1 = (W2 / L2) / ( W1
/ L1) = n, which is constant. Therefore, if the mirror ratio n is known, by detecting the value of I1,
The value of I2 (= n.I1) and therefore Io (= (n + 1).
I1). For example, 1000 as the value of n
Is good.

Since Io and I1 can be regarded as being in a proportional relationship, the voltage drop Vm of the monitor resistor Rm due to I1 is Vm.
Is compared with the reference voltage Vrf (see FIG. 2), and by detecting that Vm has exceeded the reference voltage Vrf, it is possible to detect that Io has exceeded the predetermined value. In the current detection circuit 10 of FIG. 1, when Vm exceeds the reference voltage Vrf, the comparator COMP outputs a current limit signal Co (see FIG. 2). By outputting the current limit signal Co, it is possible to detect that the output current Io has exceeded a predetermined value. By inputting the current limiting signal Co into, for example, a current limiting circuit (not shown) for controlling the gate voltage Vg, the gate voltage Vg can be made zero and the MOSFET transistors M1 and M2 can be cut off.

As described above, since the divided current flowing between MOSFETs whose on-resistances are matched in a monolithic device has relatively good inherent accuracy, the power MO
The SFET current detection circuit 10 makes it possible to measure the load current of the power adjustment circuit and the like with some efficiency. If the monitor resistance Rm is less than 10% of the on-resistance of the detection unit transistor M1, then Rm can be neglected, and the current I1 to be detected becomes almost the output current / current mirror ratio, that is, I2 / n.

[0008]

However, actually, in order to keep the detection loss low, the detection unit transistor M
1 must be designed to be smaller (W1 << W2) than W2 of the transistor M2. In this case, if Rm is made negligibly smaller than the on-resistance of the transistor M1, the detection resistance becomes smaller. The detection voltage generated at Rm is usually insufficient to drive a current limiting circuit including a comparator and the like. Therefore, a relatively large value must be used for Rm, and Rm cannot be ignored. Then, there is a problem that the total resistance on the detection (mirror) side is considerably increased and the current mirror ratio is changed. That is, if Rm cannot be neglected, the drain-source voltages Vds of the transistors M1 and M2 will not be equal to each other, which will degrade the current mirror ratio and deteriorate the detection accuracy.

In view of the above problems, an object of the present invention is to provide a current detection circuit with high detection accuracy.

It is another object of the present invention to provide a current detection circuit which does not use an output current in a monitor circuit and has no detection loss.

[0011]

In order to achieve the above object, a current detecting circuit 30 using a plurality of FET transistors according to the present invention comprises: A drain electrode is connected to a first power supply Vdd, and a gate electrode is connected to both. First and second transistors M1, M2 connected to the input signal terminal Vg;
A constant current source Irf connected between the source electrode of the first transistor M1 and the second power supply (earth); one input is connected to the source electrode of the first transistor M1, and the other input is connected to the second transistor M2 A voltage comparator COMP connected to the source electrode and the output terminal of
It is characterized in that the potential of the source electrode of the second transistor M2 and the potential of the source electrode of the first transistor M1 are compared to detect a predetermined value exceeding the output current Io flowing through the output terminal.

[0012]

In the current detecting circuit of the present invention configured as described above, both source potentials V1 of both transistors M1 and M2 are used.
, V2 are exactly equal (V1 = V2), the drain current ratio I2 / I1 of both transistors becomes I2 / I
1 = (W2 / L2) / (W1 / L1) = n (mirror ratio)
It works to become. Since I1 takes a predetermined value by the constant current source Irf, when the output current Io = I2 exceeds the maximum allowable current value Imx, I2> I11n. Then, V2 decreases and V1> V2, and the comparator COMP that detects this outputs the current limit signal Co.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a configuration of a current detection circuit according to one embodiment of the present invention. As shown in the figure, the current detection circuit 30 includes two parallel n-channel MOSFET transistors M1 and M2 formed in a monolithic device. The transistors M1 and M2 may use a p-channel according to the circuit configuration shown in FIG.
It may be an OSFET. The drain electrode of the detection MOSFET transistor M1, which is the first transistor, is connected to the power supply voltage line Vdd, the gate electrode is connected to the input signal terminal Vg, and the source electrode is connected via the constant current source Irf to the ground, which is the second power supply. It is connected to the. Power MOSFET transistor M2 as the second transistor
Has a drain electrode connected to the power supply voltage line Vdd and a gate electrode connected to the input signal terminal Vs, similarly to the transistor M1.
Connected to g. The source electrode of the transistor M2 is connected to an output terminal Po for extracting an output current (load current) Io. As described above, in the present invention, the output current Io is not divided into the power section and the detection section. For this reason, the detection section does not affect the output side. The current detection circuit 30 also has a voltage comparator COMP. The non-inverting input terminal of the voltage comparator COMP receives the voltage V1 from a node between the source electrode of the first transistor M1 and the constant current source Irf. The inverting input terminal of the voltage comparator COMP receives the voltage V2 from the output terminal Po. When the inverted input value becomes smaller than the non-inverted input value, the voltage comparator COMP outputs the current limit output signal Co.

The operation of the current detection circuit 30 will be described below. For explanation of the operation, both transistors M1,
The two source potentials V1 and V2 of M2 are equal to each other (V1 =
V2). At this time, the voltage comparator COMP
Does not output the current limit signal Co. Generally MOSFET
In an operation region where Vds is extremely smaller than Vgs, the drain current Id is expressed by the following equation in the same manner as described above.

Id = K ・ W / L ・ (Vgs-Vth) Vds According to the above assumption (V1 = V2), both transistors M1,
The drain-source voltage Vds and the gate-source voltage Vgs of M2 are equal to each other. Since the threshold voltages Vth of both transistors M1 and M2 can be considered to be substantially equal, the drain current I2 of the FET transistor M2 and FE
Ratio I2 / I1 with drain current I1 of T transistor M1
Is I2 / I1 = (W2 / L2) / (W1 / L1) =
n. Assuming that the operation is performed in accordance with the mirror ratio n in this manner, knowing the value of
(= N ・ I1), hence Io (= I2 = n ・ I1)
You can know. For example, 1000 may be used as the value of n.

When the two source potentials V1 and V2 are equal, a proportional relationship between Io and I1 is established. However, actually, I1 takes a predetermined value by the constant current source Irf. The output current Io, that is, the maximum allowable current value of I2 is set to Imx, and the current value of the constant current source Irf is set to Imx / n. By doing so, when I2 flows past Imx, I1 remains Irf (= Imx / n), so that I2> I1n. Then, the proportional relationship of I2 = n.I1 breaks down, V2 decreases, and V1> V2. The comparator COMP detecting this outputs the current limit signal Co (see FIG. 4). Therefore, it can be detected that Io has exceeded Imx by outputting the current limit signal Co. By outputting the current limiting signal Co to, for example, a current limiting circuit (not shown) for controlling the gate voltage Vg, the gate voltage Vg is reduced to zero and the MOSFE
The T transistors M1 and M2 can be cut off.

[0017]

Since the present invention is configured as described above, it is possible to avoid a detection error due to the monitor resistor Rm as experienced in the prior art, and to detect and limit the load current with high accuracy and efficiency. Is obtained. Further, the detection current I1 in the monitor circuit is supplied from the constant current source Irf, and does not use a part of the output current Io.
There are many effects such as high accuracy, easy design of a suitable stabilizing circuit, and less influence from the use conditions of the circuit.

[Brief description of the drawings]

FIG. 1 shows a conventional current detection circuit.

FIG. 2 is a graph illustrating the operation of the circuit of FIG.

FIG. 3 shows a current detection circuit according to one embodiment of the present invention.

FIG. 4 is a graph illustrating the operation of the circuit of FIG. 3;

FIG. 5 shows a current detection circuit according to another embodiment of the present invention.

[Explanation of symbols]

 30 Current detection circuit Vdd Power supply voltage Vg Input signal voltage M1 First transistor M2 Second transistor Irf Constant current source Po Output terminal COMP Voltage comparator Io Output current

Claims (1)

(57) [Claims] 1. A current detection circuit using a plurality of FET transistors, wherein: a first transistor and a second transistor both having a drain electrode connected to a first power supply and a gate electrode both connected to an input signal terminal; A constant current source connected between the source electrode of one transistor and a second power supply; one input connected to the source electrode of the first transistor, and the other input connected to the source electrode and the output terminal of the second transistor A voltage comparator connected to the output terminal; comparing the potential of the source electrode of the second transistor with the potential of the source electrode of the first transistor to stabilize the output current flowing through the output terminal from exceeding a predetermined value. Target
Current detection circuit and detecting the.