CN102193576B - Reference voltage generation circuit - Google Patents
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- CN102193576B CN102193576B CN201010130270.6A CN201010130270A CN102193576B CN 102193576 B CN102193576 B CN 102193576B CN 201010130270 A CN201010130270 A CN 201010130270A CN 102193576 B CN102193576 B CN 102193576B
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Abstract
The invention provides a reference voltage generation circuit. The reference voltage generation circuit comprises a reference voltage circuit used for providing a reference voltage for an integrated circuit. The reference voltage generation circuit also comprises a clamping circuit and a selection circuit, wherein the clamping circuit works under a first working voltage and outputs a first input voltage; and the selection circuit provides the first input voltage for the reference voltage circuit to serve as a working voltage in a first time when the reference voltage circuit starts to work, and provides a stabilized voltage for the reference voltage circuit to serve as the working voltage after the first time when the reference voltage circuit starts to work, wherein the stabilized voltage is the working voltage of the integrated circuit. In the reference voltage generation circuit, the stabilized voltage serves as the working voltage of the reference voltage circuit, so that the precision of the generated reference voltage is increased, and the stability of the integrated circuit is improved.
Description
Technical field
The present invention relates to technical field of circuit design, particularly relate to a kind of reference voltage generating circuit.
Background technology
Along with the continuous increase of footprint, especially SOC (system on a chip) (system on chip, SOC) development of integrated technology, reference voltage stabilizing source becomes on a large scale, indispensable basic circuit module in VLSI (very large scale integrated circuit) and nearly all digital simulator system.In many integrated circuit and circuit unit, as digital to analog converter (DAC), analog to digital converter (ADC), linear voltage-stabilizing circuit and switch voltage-stabilizing circuit, all need accurate and stable voltage as systematic survey and school reference of reference, therefore, reference voltage stabilizing source occupies very consequence in Analogous Integrated Electronic Circuits, and it directly affects performance and the precision of electronic system.Fig. 1 is a kind of reference voltage circuit conventional in prior art and mu balanced circuit is the schematic diagram that integrated circuit (as SOC (system on a chip)) provides voltage, described outer power voltage VDDA is provided to mu balanced circuit 101 and reference voltage circuit 102 simultaneously, described reference voltage circuit 102 is started working after being unlocked, operating voltage is provided by outer power voltage VDDA, in order to generate reference voltage V REF, described reference voltage V REF is provided to SOC (system on a chip) 103 and mu balanced circuit 10; Described mu balanced circuit 101 provides operating voltage by outer power voltage VDDA and reference voltage V REF, and for generating burning voltage VDD, described burning voltage VDD is provided to SOC (system on a chip) 103, as the operating voltage of SOC (system on a chip) 103.
Wherein, reference voltage circuit 102 needs the situation working in Width funtion input (namely outer power voltage VDDA inputs) usually, if supply voltage when SIM card is applied is 2.7-5V.And be reliably working in Width funtion input condition, reference voltage circuit needs to use high voltage transistor, and during to make high input voltage, transistor is not breakdown.And according to transistor working principle, the corresponding high field intensity of high voltage, when voltage is increased to certain numerical value, two knots of transistor overlap under the effect of electric field, a large amount of charge carrier directly flows between two PN junctions, electric current is caused sharply to increase, transistor is breakdown, and for for the certain material of semiconductor and special process, its voltage breakdown increases with the thickness increase of grid oxic horizon, therefore need to use thicker material for obtaining high-breakdown-voltage, the thickness of general increase grid oxic horizon or channel length, the cutoff frequency of transistor must be reduced like this and increase the noise of transistor, the tracking velocity of reference voltage generating circuit is caused to reduce thus and noise voltage rising, very serious impact is produced on using other circuit of this reference voltage and even system.Therefore be necessary the technological means proposing to improve, solve this problem.
A kind of technical scheme is provided in the patented claim of application number 200910002345.X, to solve the problem, the reference voltage circuit of low-voltage tube is adopted to work in Width funtion, when especially can work in high input voltage: a clamping circuit is set between high input voltage and reference voltage circuit, first high input voltage is transferred to clamping circuit, make the voltage power supply after described clamper in the working range of low-voltage tube, then by the voltage transmission after clamper to reference voltage circuit.Inventor finds, technique scheme mainly exists following problem:
1, the voltage reduced by clamping circuit is often relatively more rough, and the reference voltage that described reference voltage circuit can be caused to generate not precisely, thus makes the unstable working condition of integrated circuit (as SOC (system on a chip));
2, usual, reference voltage circuit is except providing reference voltage, also provide corresponding reference current to SOC (system on a chip), SOC (system on a chip) can by reference current described in PMOS transistor mirror image, to produce working current, because the reference voltage that reference current is corresponding is produced by clamping circuit step-down, it is inconsistent with the burning voltage (operating voltage of SOC (system on a chip)) being connected PMOS transistor source electrode, SOC (system on a chip) internal current mirror image can be made not mate, cause the working current of generation not accurate, and then cause the unstable working condition of SOC (system on a chip);
3, clamping circuit is as a newly-installed circuit, in running order all the time, adds the power consumption of circuit.
Summary of the invention
What the present invention solved is that existing reference voltage circuit adopts low-voltage tube to generate the voltage being supplied to integrated circuit, can make the problem of the unstable working condition of integrated circuit.
For solving the problem, the invention provides a kind of reference voltage generating circuit, comprising: reference voltage circuit, for providing reference voltage to integrated circuit; Described reference voltage generating circuit also comprises:
Clamping circuit, works under the first operating voltage, exports the first input voltage;
Selection circuit, within the very first time that described reference voltage circuit is started working, described first input voltage is supplied to described reference voltage circuit as operating voltage, after the very first time that described reference voltage circuit is started working, burning voltage is supplied to described reference voltage circuit as operating voltage, described burning voltage is the operating voltage of described integrated circuit.
Optionally, described selection circuit comprises:
First phase inverter, input control signal, exports inverted control signal;
First PMOS transistor, grid inputs described inverted control signal, and source electrode inputs described burning voltage, and drain electrode connects the output terminal of described selection circuit;
Second PMOS transistor, grid inputs described control signal, described first input voltage of source electrode input, and drain electrode connects the output terminal of described selection circuit,
Described control signal opens described second PMOS transistor within the very first time that described reference voltage circuit is started working, and described inverted control signal opens described first PMOS transistor after the very first time that described reference voltage circuit is started working.
Optionally, described selection circuit comprises:
First phase inverter, input control signal, exports inverted control signal;
First nmos pass transistor, grid inputs described inverted control signal, and source electrode inputs described burning voltage, and drain electrode connects the output terminal of described selection circuit;
Second nmos pass transistor, grid inputs described control signal, described first input voltage of source electrode input, and drain electrode connects the output terminal of described selection circuit,
Described control signal opens described second nmos pass transistor within the very first time that described reference voltage circuit is started working, and described inverted control signal opens described first nmos pass transistor after the very first time that described reference voltage circuit is started working.
Optionally, described selection circuit comprises:
Nmos pass transistor, gate input control signal, source electrode inputs described burning voltage, and drain electrode connects the output terminal of described selection circuit;
PMOS transistor, gate input control signal, described first input voltage of source electrode input, drain electrode connects the output terminal of described selection circuit,
Described control signal opens described PMOS transistor within the very first time that described reference voltage circuit is started working, after the very first time that described reference voltage circuit is started working, open described nmos pass transistor.
Optionally, described reference voltage generating circuit also comprises the delay circuit providing described control signal, and described delay circuit comprises:
Oscillator, is controlled to open by enable signal, and by vibration clock signal, described enable signal is for opening described reference voltage circuit;
Counter, counts described clock signal, exports described control signal.
Optionally, described reference voltage generating circuit also comprises the comparator circuit providing described control signal, and the more described burning voltage of described comparator circuit and the first input voltage, export described control signal.
Optionally, described clamping circuit comprises:
First switching transistor, grid input switch signal, described first operating voltage of source electrode input, drain electrode exports described first input voltage;
Partial pressure unit, comprises first end and the second end, and described first end connects the drain electrode of described first switching transistor, described second end ground connection.
Optionally, described partial pressure unit comprises:
First clamp transistor, grid is connected the first end of described partial pressure unit with drain electrode;
Second clamp transistor, grid is connected the source electrode of described first clamp transistor with drain electrode, and source electrode connects the second end of described partial pressure unit.
Optionally, described reference voltage generating circuit also comprises the on-off circuit providing described switching signal.
Optionally, described on-off circuit comprises:
Second phase inverter, input control signal, exports inverted control signal;
And not circuit, input enable signal and described inverted control signal, export described switching signal, described enable signal is for opening described reference voltage circuit.
Optionally, described reference voltage generating circuit also comprises: mu balanced circuit, and described mu balanced circuit works under described first operating voltage and reference voltage, exports described burning voltage.
Compared with prior art, technique scheme has the following advantages:
1, clamping circuit works in the first operating voltage (high input voltage scope), within the very first time that described reference voltage circuit is started working, the first input voltage that described reference voltage circuit input clamping circuit produces, can make low-voltage tube work within the scope of high input voltage;
2, after the very first time that described reference voltage circuit is started working, described reference voltage circuit input burning voltage, improves the precision of the reference voltage that reference voltage circuit exports;
3, after the very first time that described reference voltage circuit is started working, described reference voltage circuit input burning voltage, the burning voltage that the reference voltage that reference voltage circuit is provided and mu balanced circuit provide is consistent, improves the accuracy of SOC (system on a chip) internal circuit mirror image;
4, after described reference voltage circuit input burning voltage, the clamping circuit of generation first input voltage can be closed, reduce the power consumption of circuit.
Accompanying drawing explanation
Fig. 1 is the reference voltage circuit of prior art and mu balanced circuit for SOC (system on a chip) provides the circuit diagram of voltage;
Fig. 2 for reference voltage generating circuit of the present invention and mu balanced circuit for integrated circuit provides the circuit diagram of voltage;
The embodiment circuit diagram that Fig. 3 is circuit shown in Fig. 2;
Another embodiment circuit diagram that Fig. 4 is circuit shown in Fig. 2.
Embodiment
For making above-mentioned purpose of the present invention, feature and advantage can become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 2 for reference voltage generating circuit of the present invention and mu balanced circuit for integrated circuit provides the circuit diagram of voltage, described reference voltage generating circuit comprises: reference voltage circuit 201, for providing reference voltage V REF to integrated circuit 205, what reference voltage circuit 201 described in the present embodiment adopted is low-voltage tube;
Described reference voltage generating circuit also comprises:
Clamping circuit 204, work under the first operating voltage VDDA, export the first input voltage VDD_TP, concrete: the first operating voltage VDDA is high input voltage (can be such as 2.7 ~ 5V), clamper is carried out to described first operating voltage VDDA, voltage after clamper reduces, and namely the first input voltage VDD_TP makes the reference voltage circuit 201 of described low-voltage tube normally to work;
Selection circuit 203, within the very first time that described reference voltage circuit 201 is started working, described first input voltage VDD_TP is supplied to described reference voltage circuit 201 as operating voltage, after the very first time that described reference voltage circuit 201 is started working, burning voltage VDD is supplied to described reference voltage circuit 201 as operating voltage, described burning voltage VDD is the operating voltage of described integrated circuit 205.
Burning voltage VDD can be produced by mu balanced circuit 202, and mu balanced circuit 202 works under the first operating voltage VDDA and reference voltage V REF.
Continue with reference to figure 2, what described reference voltage circuit 201 inputted is the voltage that selection circuit 203 exports, and namely the input end of reference voltage circuit 201 is connected with the output terminal of selection circuit 203, and described selection circuit 203 comprises:
First input end, inputs the first input voltage VDD_TP;
Second input end, input burning voltage VDD;
3rd input end, input control signal SEL;
Output terminal, under control signal SEL controls, after described reference voltage circuit 201 is unlocked (starting working) the very first time in export the first input voltage VDD_TP, stable output voltage VDD after the very first time after described reference voltage circuit 201 is unlocked.
The reference voltage generating circuit that Fig. 3 is an embodiment and mu balanced circuit provide the circuit diagram of voltage for integrated circuit, and described reference voltage generating circuit comprises: reference voltage circuit 201, selection circuit 203, clamping circuit 204, delay circuit 207 and on-off circuit 206.
Reference voltage circuit 201, output terminal output reference voltage VREF, be unlocked in the very first time at described reference voltage circuit 201, the input end of described reference voltage circuit 201 inputs the first input voltage VDD_TP, after described reference voltage circuit 201 is unlocked the very first time, the input end input burning voltage VDD of described reference voltage circuit 201.
Wherein, described burning voltage VDD is provided by mu balanced circuit 201, and described mu balanced circuit 201 inputs the first operating voltage VDDA and reference voltage V REF, exports described burning voltage VDD.In the present embodiment, reference voltage V REF and the burning voltage VDD of generation are also supplied to integrated circuit 205, and burning voltage VDD is as the operating voltage of integrated circuit 205.
Selection circuit 203, output terminal is connected to the input end of described reference voltage circuit 201, and to the input end input voltage of reference voltage circuit 201, described selection circuit 203 comprises:
First phase inverter 301, input end connects described 3rd input end, input control signal SEL, exports inverted control signal (i.e. the inversion signal of control signal SEL);
First PMOS transistor M1, grid connects the output terminal of phase inverter 301, inputs described inverted control signal; Source electrode connects the output terminal of mu balanced circuit 202, the burning voltage VDD exported with input stabilizing circuit 202; Drain electrode connects the output terminal (i.e. the input end of reference voltage circuit 201) of selection circuit 203;
Second PMOS transistor M2, grid inputs described control signal SEL, and source electrode connects the output terminal of clamping circuit 204, and to input the first input voltage VDD_TP that clamping circuit 204 exports, drain electrode connects the output terminal of selection circuit 203,
Described control signal SEL opens described second PMOS transistor M2 within the very first time that described reference voltage circuit 201 is started working, and described inverted control signal opens described first PMOS transistor M1 after the very first time that described reference voltage circuit 201 is started working.
The control signal SEL of described selection circuit 203 exports through delay circuit 207, and described delay circuit 207 comprises:
Oscillator, is controlled to open by enable signal EN, and by vibration clock signal, described enable signal EN is for opening described reference voltage circuit 201, and when enable signal EN is effective, reference voltage circuit 201 is started working;
Counter, counts described clock signal, exports described control signal SEL.
Setting delay time, the i.e. product in the count value of counter and the cycle of described clock signal.After described delay time arrives, change described control signal SEL.Described delay time be more than or equal to generate to burning voltage VDD after reference voltage circuit 201 is unlocked between required time, described delay time is the described very first time.
Continue with reference to figure 3, described first input voltage VDD_TP is the output voltage of clamping circuit 204, and described clamping circuit 204 works under the first operating voltage VDDA, and exports the first input voltage VDD_TP.
Described clamping circuit 204 comprises:
First switching transistor M3, grid input switch signal, source electrode inputs the first operating voltage VDDA, the output terminal of drain electrode electrical connection clamping circuit 204, and in the present embodiment, described first switching transistor M3 is PMOS transistor, for low level triggers;
Partial pressure unit 2041, comprises first end and the second end, the output terminal of described first end electrical connection clamping circuit 204, described second end ground connection.
In the present embodiment, described partial pressure unit 2041 comprises the first clamp transistor M4 and the second clamp transistor M5:
First clamp transistor M4, grid is electrically connected the first end of clamping circuit 204 with drain electrode, and source electrode is electrically connected the second clamp transistor M5;
Second clamp transistor M5, grid is electrically connected the source electrode of the first clamp transistor M4 with drain electrode, and source electrode connects the second end of described partial pressure unit 2041, source ground in the present embodiment.In the present embodiment, described first clamp transistor M4 and the second clamp transistor M5 is nmos pass transistor, for high level triggers.Further, the number of described clamp transistor also can other numbers beyond 2, carry out the decision of the voltage swing after clamper according to required, the output voltage i.e. first input voltage VDD_TP of described clamping circuit, equals the threshold voltage sum of the clamp transistor in partial pressure unit 2041.
In the present embodiment, what described partial pressure unit 2041 adopted is that transistor arrangement carries out dividing potential drop, in other embodiments, resistance can also be adopted to carry out dividing potential drop.
Continue with reference to figure 3, the switching signal that described clamping circuit 204 inputs is provided by on-off circuit 206, whether works in order to control clamping circuit 204.
Described on-off circuit 206 comprises:
Second phase inverter 302, input end connects the output terminal of delay circuit 207, and with input control signal SEL, output terminal connects and not circuit 303, exports inverted control signal;
And not circuit 303, input enable signal EN and described inverted control signal, export described switching signal, described enable signal EN is for opening described reference voltage circuit, and in the present embodiment, enable signal EN is that high level is effective.
Continue with reference to figure 3, the course of work of described reference voltage generating circuit is specially: provide the first operating voltage VDDA to the source electrode of the first switch P MOS transistor M3 of clamping circuit 204, and open and not circuit 303 and delay circuit 207 by enable signal EN;
Described enable signal EN is high level signal, is low level after described and not circuit 303, and after the grid of described first switch P MOS transistor M3 inputs described low level, clamping circuit 204 is opened.The dividing potential drop of the first clamper nmos pass transistor M4 in partial pressure unit 2041 and the second clamper nmos pass transistor M5, export the first input voltage VDD_TP, described first input voltage VDD_TP equals the threshold voltage sum of the first clamper nmos pass transistor M4 and the second clamper nmos pass transistor M5;
Described delay circuit 207 inputs after described enable signal EN is opened, clocking, and by described clock signal transmission to counter, described counter equal is: when setting delay time does not arrive before, it is low level that described counter exports control signal SEL, after setting delay time (very first time) arrives, it is high level that described counter exports control signal SEL, described delay time for after providing from enable signal EN to the time that burning voltage VDD generates, described delay time can set based on experience value, can be generally 3 microsecond ~ 9 microseconds,
Described burning voltage VDD and the first input voltage VDD_TP is corresponding is respectively provided to the first PMOS transistor M1 in selection circuit 203 and the second PMOS transistor M2.When delay time does not arrive before, when control signal SEL is low level, by being high level after phase inverter 303, the first PMOS transistor M1 closes, and the second PMOS transistor M2 opens, and the output voltage of selection circuit 203 is the first input voltage VDD_TP;
Described low level control signal SEL is also provided to on-off circuit 206, because control signal SEL is low level, enable signal is high level, so after and not circuit 204, described switching signal is still low level;
Reference voltage circuit 201 inputs described output voltage VDD_TP, produces reference voltage V REF.And described reference voltage V REF is provided to mu balanced circuit 202, described burning voltage VDD receives the first operating voltage VDDA simultaneously, produces burning voltage VDD;
After delay time arrives, the control signal SEL that described delay circuit 207 exports is high level, and the signal after anti-phase by phase inverter 303 is low level, and the first PMOS transistor M1 opens, second PMOS transistor M2 is closed, and the output voltage of selection circuit 203 is burning voltage VDD.
Reference voltage circuit 201 inputs described burning voltage VDD, produces reference voltage V REF.
Simultaneously, the control signal SEL of described high level also transfers to on-off circuit 302, because control signal SEL is high level, enable signal EN is high level, so after and not circuit 204, described switching signal is high level, and the first switch P MOS transistor M3 is closed, and then clamping circuit 204 is closed;
After this, the voltage that described selection circuit 203 exports is burning voltage VDD.
Fig. 4 for reference voltage generating circuit of the present invention and mu balanced circuit for SOC (system on a chip) provides another embodiment circuit diagram of voltage, the difference of the reference voltage generating circuit shown in the reference voltage generating circuit of the present embodiment and Fig. 3 is: the control signal SEL of described selection circuit 203 can be exported by comparator circuit 208, the anode input burning voltage VDD of described comparator circuit 208, negative terminal inputs the first input voltage VDD_TP, when burning voltage VDD is lower than the first input voltage VDD_TP, described control signal SEL is low level, second PMOS transistor M2 opens, selection circuit 203 exports the first input voltage VDD_TP, along with the rising of burning voltage VDD, when burning voltage VDD is equal to or higher than the first input voltage VDD_TP, described control signal SEL is high level, and the first PMOS transistor M1 opens, selection circuit 203 stable output voltage VDD.Therefore, in the present embodiment, the described very first time for start working after reference voltage circuit 201 is unlocked, until in comparator circuit 208 burning voltage VDD higher than the time span of the first input voltage VDD_TP.
It should be noted that, in above-described embodiment, described selection circuit 203 is formed by two PMOS transistor parallel connections, and described selection circuit 203 can also be formed by two nmos pass transistor parallel connections, specifically comprises:
First phase inverter, connects the 3rd input end, input control signal SEL;
First nmos pass transistor, the control signal of grid input after the first phase inverter is anti-phase, the burning voltage that drain electrode input stabilizing circuit exports, source electrode connects selection circuit output terminal;
Second nmos pass transistor, grid connects the 3rd input end, input control signal, and drain electrode input first input voltage, source electrode connects selection circuit output terminal.
When described control signal SEL is high level, described second nmos pass transistor is opened, and described first nmos pass transistor is closed, and what described selection circuit 203 exported is the first input voltage; When described control signal SEL is low level, described first nmos pass transistor is opened, and described second nmos pass transistor is closed, and what described selection circuit 203 exported is burning voltage.
Concrete: if described control signal SEL delay circuit 207 as shown in Figure 3 provides, then, before time delay arrives, described control signal SEL is high level, in order to open the second nmos pass transistor, after time delay arrives, described control signal SEL is low level, in order to open the first nmos pass transistor; If described control signal SEL comparator circuit 208 as shown in Figure 4 provides, the negative terminal input burning voltage VDD of described comparator circuit 208, anode inputs the first input voltage VDD_TP, when burning voltage VDD is lower than the first input voltage VDD_TP, described control signal SEL is high level, second nmos pass transistor is opened, and selection circuit 203 exports the first input voltage VDD_TP; Along with the rising of burning voltage VDD, when burning voltage VDD is equal to or higher than the first input voltage VDD_TP, described control signal SEL is low level, and the first nmos pass transistor is opened, selection circuit 203 stable output voltage VDD.
Described selection circuit 203 can also be formed by a PMOS and a NMOS tube parallel connection, specifically comprises:
Nmos pass transistor, grid connects the 3rd input end, with input control signal, the burning voltage that drain electrode input stabilizing circuit exports, source electrode connects selection circuit output terminal;
PMOS transistor, grid connects the 3rd input end, and with input control signal, drain electrode input first input voltage, source electrode connects selection circuit output terminal.
When described control signal SEL is low level, described PMOS transistor is opened, and described nmos pass transistor is closed, and what described selection circuit 203 exported is the first input voltage; When described control signal SEL is high level, described nmos pass transistor is opened, and described PMOS transistor is closed, and what described selection circuit 203 exported is burning voltage.
Concrete: if described control signal SEL delay circuit 207 as shown in Figure 3 provides, then, before time delay arrives, described control signal SEL is low level, in order to open PMOS transistor, after time delay arrives, described control signal SEL is high level, in order to open NMOS transistor; If described control signal SEL comparator circuit 208 as shown in Figure 4 provides, the anode input burning voltage VDD of described comparator circuit 208, negative terminal inputs the first input voltage VDD_TP, when burning voltage VDD is lower than the first input voltage VDD_TP, described control signal SEL is low level, PMOS transistor is opened, and selection circuit 203 exports the first input voltage VDD_TP; Along with the rising of burning voltage VDD, when burning voltage VDD is equal to or higher than the first input voltage VDD_TP, described control signal SEL is high level, and nmos pass transistor is opened, selection circuit 203 stable output voltage VDD.
Although the present invention discloses as above in a preferred embodiment thereof, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should with claim institute limited range.
Claims (10)
1. a reference voltage generating circuit, comprising: reference voltage circuit, for providing reference voltage to integrated circuit; It is characterized in that, what described reference voltage circuit adopted is low-voltage tube, to improve the cutoff frequency of transistor and to reduce the noise of transistor, also comprises:
Clamping circuit, works under the first operating voltage, exports the first input voltage, and wherein, described first operating voltage is high input voltage, and described first input voltage makes the reference voltage circuit of described low-voltage tube normally to work;
Selection circuit, within the very first time that described reference voltage circuit is started working, described first input voltage is supplied to described reference voltage circuit as operating voltage, low-voltage tube is made to work within the scope of high input voltage, after the very first time that described reference voltage circuit is started working, burning voltage is supplied to described reference voltage circuit as operating voltage, to improve the precision of the reference voltage that reference voltage circuit exports, described burning voltage is the operating voltage of described integrated circuit;
Mu balanced circuit, described mu balanced circuit works under described first operating voltage and reference voltage, exports described burning voltage.
2. reference voltage generating circuit according to claim 1, it is characterized in that, described selection circuit comprises:
First phase inverter, input control signal, exports inverted control signal;
First PMOS transistor, grid inputs described inverted control signal, and source electrode inputs described burning voltage, and drain electrode connects the output terminal of described selection circuit;
Second PMOS transistor, grid inputs described control signal, described first input voltage of source electrode input, and drain electrode connects the output terminal of described selection circuit,
Described control signal opens described second PMOS transistor within the very first time that described reference voltage circuit is started working, and described inverted control signal opens described first PMOS transistor after the very first time that described reference voltage circuit is started working.
3. reference voltage generating circuit according to claim 1, it is characterized in that, described selection circuit comprises:
First phase inverter, input control signal, exports inverted control signal;
First nmos pass transistor, grid inputs described inverted control signal, and source electrode inputs described burning voltage, and drain electrode connects the output terminal of described selection circuit;
Second nmos pass transistor, grid inputs described control signal, described first input voltage of source electrode input, and drain electrode connects the output terminal of described selection circuit,
Described control signal opens described second nmos pass transistor within the very first time that described reference voltage circuit is started working, and described inverted control signal opens described first nmos pass transistor after the very first time that described reference voltage circuit is started working.
4. reference voltage generating circuit according to claim 1, it is characterized in that, described selection circuit comprises:
Nmos pass transistor, gate input control signal, source electrode inputs described burning voltage, and drain electrode connects the output terminal of described selection circuit;
PMOS transistor, gate input control signal, described first input voltage of source electrode input, drain electrode connects the output terminal of described selection circuit,
Described control signal opens described PMOS transistor within the very first time that described reference voltage circuit is started working, after the very first time that described reference voltage circuit is started working, open described nmos pass transistor.
5. reference voltage generating circuit according to any one of claim 2 to 4, is characterized in that, also comprises the delay circuit providing described control signal, and described delay circuit comprises:
Oscillator, is controlled to open by enable signal, and by vibration clock signal, described enable signal is for opening described reference voltage circuit;
Counter, counts described clock signal, exports described control signal.
6. reference voltage generating circuit according to any one of claim 2 to 4, is characterized in that, also comprises the comparator circuit providing described control signal, and the more described burning voltage of described comparator circuit and the first input voltage, export described control signal.
7. reference voltage generating circuit according to any one of claim 2 to 4, is characterized in that, described clamping circuit comprises:
First switching transistor, grid input switch signal, described first operating voltage of source electrode input, drain electrode exports described first input voltage;
Partial pressure unit, comprises first end and the second end, and described first end connects the drain electrode of described first switching transistor, described second end ground connection.
8. reference voltage generating circuit according to claim 7, it is characterized in that, described partial pressure unit comprises:
First clamp transistor, grid is connected the first end of described partial pressure unit with drain electrode;
Second clamp transistor, grid is connected the source electrode of described first clamp transistor with drain electrode, and source electrode connects the second end of described partial pressure unit.
9. reference voltage generating circuit according to claim 7, is characterized in that, also comprise the on-off circuit providing described switching signal.
10. reference voltage generating circuit according to claim 9, it is characterized in that, described on-off circuit comprises:
Second phase inverter, input control signal, exports inverted control signal;
And not circuit, input enable signal and described inverted control signal, export described switching signal, described enable signal is for opening described reference voltage circuit.
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| CN112416046A (en) * | 2019-08-23 | 2021-02-26 | 半导体元件工业有限责任公司 | Voltage clamping circuit |
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| CN101488362A (en) * | 2008-01-08 | 2009-07-22 | 三美电机株式会社 | Semiconductor device |
| CN101566974A (en) * | 2009-05-25 | 2009-10-28 | 炬力集成电路设计有限公司 | System on a chip and starting method thereof |
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| CN102193576A (en) | 2011-09-21 |
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