CN112234957A - Analog oscillator circuit with negative feedback adjusting function - Google Patents
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Abstract
An analog oscillator circuit with a negative feedback regulation function utilizes a clock generation module to generate output clock signals which periodically change, if the output clock signals are in a first state, a first charging current is controlled to charge a first capacitor and discharge a second capacitor, when the voltage value of the first capacitor reaches a first threshold value, the output clock signals are converted from the first state to a second state, a second charging current is controlled to charge the second capacitor and discharge the first capacitor, and when the voltage value of the second capacitor reaches a second threshold value, the output clock signals are converted from the second state to the first state; the negative feedback adjusting module is used for generating a corresponding control signal according to the output clock signal, and when the period of the output clock signal is prolonged, the control signal controls the first charging current and the second charging current to increase, so that the period of the output clock signal is shortened; when the period of the output clock signal is shortened, the control signal is used for controlling the first charging current and the second charging current to be reduced, and the period of the output clock signal is prolonged.
Description
Technical Field
The invention belongs to the technical field of oscillators in analog integrated circuit design, relates to an on-chip RC relaxation oscillator, and particularly relates to a relaxation oscillator circuit with a negative feedback regulation function.
Background
The relaxation oscillator generates periodic clock signals through charging and discharging of a capacitor, and is influenced by different temperature characteristics of a circuit structure, a resistor, a capacitor and an MOS (metal oxide semiconductor) tube, process change, voltage change and the like, the relaxation oscillator can generate different output frequencies to influence the precision of the relaxation oscillator, and large deviation is generated between the clock frequency generated by the relaxation oscillator and an ideal value.
In order to solve the problem, various methods for improving the accuracy of the relaxation oscillator are proposed in the prior art, for example, in chinese patent with the patent name of relaxation oscillator and publication number CN105958943B, the bias current is divided into a plurality of trimming currents, and then the capacitor is charged based on the trimming currents. Also, for example, in chinese patent with publication number CN103595244B, the relaxation oscillator with frequency dithering function generates a set of logic signals through logic control for adjusting the capacitance of the charging capacitor, so as to adjust the frequency of the output clock. For another example, in chinese patent with publication No. CN103051286B, whose name is a trimmable high-precision relaxation oscillator, the frequency of the output clock is adjusted by trimming the threshold level; and chinese patent publication No. CN106062655B, entitled improved relaxation oscillator with low drift and local offset cancellation, in which two adjustable current sources are provided to supplement two comparison points, but both require additional design trimming structure, and the circuit design is complex and occupies a large area.
Disclosure of Invention
In order to solve the problems, the high-frequency output clock signal with better temperature characteristics and less influence of process variation and voltage variation is obtained by improving the traditional relaxation oscillator and introducing a negative feedback regulation module to generate a control signal which is changed along with the output clock signal and is used for controlling the charging current.
The technical scheme of the invention is as follows:
an analog oscillator circuit with negative feedback regulation function comprises a clock generation module and a negative feedback regulation module.
The clock generation module is used for generating an output clock signal of the analog oscillator circuit, and comprises a first capacitor and a second capacitor, if the output clock signal is in a first state, a first charging current is controlled to charge the first capacitor and control the second capacitor to discharge, when the voltage value of the first capacitor reaches a first threshold value, the output clock signal is converted from the first state to a second state, a second charging current is controlled to charge the second capacitor and control the first capacitor to discharge, and when the voltage value of the second capacitor reaches a second threshold value, the output clock signal is converted from the second state to the first state;
the negative feedback adjusting module is used for generating a corresponding control signal according to the output clock signal, and when the period of the output clock signal is prolonged, the control signal generated by the negative feedback adjusting module is used for controlling the first charging current and the second charging current to increase, and accelerating the time when the voltage value on the first capacitor reaches the first threshold value and the time when the voltage value on the second capacitor reaches the second threshold value, so that the period of the output clock signal is shortened; when the period of the output clock signal is shortened, the control signal generated by the negative feedback adjusting module is used for controlling the first charging current and the second charging current to be reduced, and slowing down the time when the voltage value on the first capacitor reaches the first threshold value and the time when the voltage value on the second capacitor reaches the second threshold value, so that the period of the output clock signal is prolonged.
Specifically, the clock generation module further comprises a first switch, a second switch, a first Schmitt trigger, a second Schmitt trigger, a first inverter, a second inverter and an SR trigger,
one end of the first capacitor is connected with the first charging current and the input end of the first Schmitt trigger, and is grounded after passing through the first switch, and the other end of the first capacitor is grounded;
the input end of the first phase inverter is connected with the output end of the first Schmitt trigger, and the output end of the first phase inverter is connected with the S input end of the SR trigger;
one end of the second capacitor is connected with the second charging current and the input end of the second Schmitt trigger, and is grounded after passing through the second switch, and the other end of the second capacitor is grounded;
the input end of the second inverter is connected with the output end of the second Schmitt trigger, and the output end of the second inverter is connected with the R input end of the SR trigger;
the output end of the SR trigger outputs the output clock signal, when the output clock signal is in a first state, the first switch is controlled to be switched off, the second switch is controlled to be switched on, and when the output clock signal is in a second state, the first switch is controlled to be switched on, and the second switch is controlled to be switched off.
Specifically, the clock generation module further comprises a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a first resistor,
the grid electrode of the first NMOS tube is connected with the control signal, the source electrode of the first NMOS tube is grounded after passing through the first resistor, and the drain electrode of the first NMOS tube is connected with the grid electrode and the drain electrode of the first PMOS tube and the grid electrodes of the second PMOS tube and the third PMOS tube;
the drain electrodes of the second PMOS tube and the third PMOS tube respectively output the first charging current and the second charging current, and the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with power supply voltage;
when the period of the output clock signal is longer, the voltage value of the control signal is increased; when the period of the output clock signal becomes shorter, the voltage value of the control signal decreases.
Specifically, the negative feedback adjusting module comprises a frequency divider, a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, a fourth capacitor, a first current source, a second resistor, a fifth capacitor, a sixth capacitor and an amplifier,
the frequency divider divides the frequency of the output clock signal to generate a first clock signal, controls the third switch and the sixth switch to be turned off and controls the fourth switch and the fifth switch to be turned on when the first clock signal is in a first state, and controls the third switch and the sixth switch to be turned on and controls the fourth switch and the fifth switch to be turned off when the first clock signal is in a second state;
one end of a third capacitor is connected with the first current source and one end of the fifth switch, is grounded after passing through the third switch, and the other end of the third capacitor is grounded;
one end of a fourth capacitor is connected with the second current source and one end of the sixth switch, is grounded after passing through the fourth switch, and the other end of the fourth capacitor is grounded;
one end of the second resistor is connected with the other end of the fifth switch and the other end of the sixth switch, and the other end of the second resistor is connected with the positive input end of the amplifier and is grounded after passing through the fifth capacitor;
the negative input end of the amplifier is connected with the reference voltage, and the output end of the amplifier outputs the control signal and is grounded after passing through the sixth capacitor.
Specifically, the first current source and the second current source are adjustable current sources.
In particular, the reference voltage may be adjustable.
The invention has the beneficial effects that: by introducing a negative feedback loop, the invention can adjust the charging time of the capacitor generating the output clock signal according to the change of the output clock signal, thereby realizing that the output clock signal has better stability to process change, voltage change and temperature change; in some embodiments, the trimmable current source and the reference voltage are provided, so that the precision of the output clock signal CLK _ M is improved.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a block diagram of an overall structure of an analog oscillator circuit with a negative feedback adjustment function according to the present invention.
Fig. 2 is an internal structural diagram of a negative feedback regulation module in an analog oscillator circuit with a negative feedback regulation function according to an embodiment of the present invention.
Fig. 3 is an internal structural diagram of a clock generation module in an analog oscillator circuit with negative feedback adjustment function according to an embodiment of the present invention.
Fig. 4 is a waveform diagram of a key node when the structure of fig. 3 is adopted by a clock generation module in the analog oscillator circuit with the negative feedback regulation function according to the present invention.
Fig. 5 is a schematic flow chart of a negative feedback adjustment module in an analog oscillator circuit with a negative feedback adjustment function according to the present invention.
Fig. 6 is an internal structural diagram of a negative feedback regulation module in an analog oscillator circuit with a negative feedback regulation function according to another embodiment of the present invention.
Fig. 7 is an internal implementation diagram of a clock generation module of an analog oscillator circuit with negative feedback adjustment function according to another embodiment of the present invention, which implements an SR flip-flop and generates an output clock signal CLK _ M and its inverse signal.
Fig. 8 is a waveform diagram of a key node when a clock generation module in an analog oscillator circuit with a negative feedback adjustment function according to the present invention adopts the structure of fig. 7.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments. Specific details of the embodiments described below, such as specific circuit configurations in the embodiments and specific parameters of these circuit elements, are provided to provide a better understanding of the embodiments of the present invention. It will be understood by those skilled in the art that embodiments of the present invention may be practiced without some of these details or with other methods, components, materials, etc.
Fig. 1 is a block diagram of an oscillator circuit according to the present invention, which includes a clock generating module and a negative feedback adjusting module, wherein the clock generating module is used for generating an output clock signal CLK _ M of the analog oscillator circuit, and includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is charged by a first charging current I1, the second capacitor C2 is charged by a second charging current I2, and the first capacitor C1 and the second capacitor C2 switch charging and discharging according to a state of the output clock signal CLK _ M. For example, when the output clock signal CLK _ M is in the first state, the first charging current I1 is controlled to charge the first capacitor C1 and control the second capacitor C2 to discharge, when the voltage value of the first capacitor C1 reaches the first threshold, the output clock signal CLK _ M is inverted from the first state to the second state, at this time, the second charging current I2 is controlled to charge the second capacitor C2 and control the first capacitor C1 to discharge, when the voltage value of the second capacitor C2 reaches the second threshold, the output clock signal CLK _ M is inverted from the second state to the first state, and thus, the cycle is repeated, and the stable output clock signal CLK _ M can be generated after the circuit is stabilized. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. For example, the first state may be a high level and the second state may be a low level, or the first state may be a low level and the second state may be a high level.
As shown in fig. 3, a specific implementation form of the clock generation module is given, in this embodiment, two schmitt triggers and SR triggers are used for logic control, and the clock generation module includes a first switch SW1, a second switch SW2, a first schmitt trigger, a second schmitt trigger, a first inverter, a second inverter, and an SR trigger, where the switching device in the present invention may be implemented by using a MOS transistor or other controllable switching structure. One end of the first capacitor C1 is connected with the first charging current I1 and the input end of the first schmitt trigger, and is grounded after passing through the first switch SW1, and the other end is grounded; the input end of the first phase inverter is connected with the output end of the first Schmitt trigger, and the output end of the first phase inverter is connected with the S input end of the SR trigger; one end of the second capacitor C2 is connected to the second charging current I2 and the input end of the second schmitt trigger, and is grounded after passing through the second switch SW2, and the other end is grounded; the input end of the second inverter is connected with the output end of the second Schmitt trigger, and the output end of the second inverter is connected with the R input end of the SR trigger; the output end of the SR flip-flop outputs an output clock signal CLK _ M, and when the output clock signal CLK _ M is in a first state, the first switch SW1 is controlled to be turned off, so that the first charging current I1 charges the first capacitor C1, and simultaneously the second switch SW2 is turned on to control the second capacitor C2 to discharge; when the output clock signal CLK _ M is in the second state, the first switch SW1 is controlled to be turned on so that the second charging current I2 charges the second capacitor C2, and the second switch SW2 is turned off to control the first capacitor C1 to discharge. The operation principle of the clock generation module will be described with reference to the waveform diagram of the key node in the clock generation module shown in fig. 4, in this embodiment, the first state of the output clock signal CLK _ M is a low level, the second state is a high level, the high level turns on the first switch SW1, and the low level turns off the first switch SW 1. The on-off of the controlled switches, namely the first switch SW1 and the second switch SW2, is controlled by the output clock signal CLK _ M, so that the charging and discharging time of the first capacitor C1 and the second capacitor C2 is controlled, and the output clock signal CLK _ M which changes periodically is generated.
When the output clock signal CLK _ M is at a low level, the inverted signal xCLK _ M of the output clock signal is at a high level, the output clock signal CLK _ M at the low level controls the first switch SW1 to be turned off, the inverted signal xCLK _ M of the output clock signal at the high level controls the second switch SW2 to be turned on, so that the first charging current I1 charges the first capacitor C1, the charge stored in the second capacitor C2 at the previous moment is quickly discharged to the ground through the second switch SW2, so that the R terminal of the SR flip-flop rapidly becomes at a low level, and since the first capacitor C1 is charged through the first charging current I1, the voltage VC1 on the first capacitor C1 linearly increases, and the S terminal of the SR flip-flop is always at a low level until the on threshold (i.e., the first threshold) of the first Schmitt1 is reached, so that the S terminal of the SR flip-flop is kept at a low level, and the R terminal of the SR flip-flop jumps from a high level to a low level, the output end of the SR trigger keeps a low level state at the last moment; until the voltage on the first capacitor C1 exceeds the turn-on threshold of the first Schmitt trigger Schmitt1, the S terminal of the SR flip-flop makes a transition from a low level to a high level, so that the output clock signal CLK _ M outputted from the SR flip-flop rapidly changes to a high level and the inverted signal xCLK _ M of the output clock signal rapidly changes to a low level.
The high-level output clock signal CLK _ M controls the first switch SW1 to be switched on rapidly, the inverted signal xCLK _ M of the low-level output clock signal controls the second switch SW2 to be switched off rapidly, the second charging current I2 starts to charge the second capacitor C2, before the voltage VC2 on the second capacitor C2 rises to the opening threshold (namely, the second threshold) of the second Schmitt2, the R end of the SR trigger is always at the low level, the S end of the SR trigger jumps from the high level to the low level immediately after the state of the output clock signal CLK _ M is switched, and the output end of the SR trigger keeps the high level state at the previous moment; and after the voltage on the second capacitor C2 exceeds the starting threshold of the second Schmitt trigger Schmitt2, the R end of the SR flip-flop jumps from the low level to the high level, so that the output clock signal CLK _ M output by the SR flip-flop is rapidly changed into the low level, the inverted signal xCLK _ M of the output clock signal is rapidly changed into the high level, and the stable output clock CLK _ M is obtained in a circulating way.
In this embodiment, the rollover threshold provided by the two Schmitt triggers Schmitt1 and Schmitt2 is used as the first threshold and the second threshold, and the threshold is selected as an important parameter for adjusting the frequency of the output clock signal, and the specific threshold can be adjusted according to the clock requirement. The first charging current I1 and the second charging current I2 in the clock generating module may be obtained by current mirror image, as shown in fig. 3, the clock generating module further includes a first NMOS transistor M1, a first PMOS transistor M2, a second PMOS transistor M3, a third PMOS transistor M4, and a first resistor R1, a gate of the first NMOS transistor M1 is connected to the control signal, a source thereof is grounded through a first resistor R1, a drain thereof is connected to a gate and a drain of the first PMOS transistor M2, and gates of the second PMOS transistor M3 and the third PMOS transistor M4; drains of the second PMOS transistor M3 and the third PMOS transistor M4 output a first charging current I1 and a second charging current I2, respectively, and sources of the first PMOS transistor M2, the second PMOS transistor M3 and the third PMOS transistor M4 are connected to a power supply voltage VDD; the second PMOS transistor M3 and the third PMOS transistor M4 respectively form a current mirror with the first PMOS transistor M2, and the mirrored currents are used as the first charging current I1 and the second charging current I2.
The current values of the first charging current I1 and the second charging current I2 can be adjusted by a negative feedback adjusting module, the negative feedback adjusting module generates corresponding control signals according to the output clock signal CLK _ M, and when the period of the output clock signal CLK _ M is prolonged, the control signals generated by the negative feedback adjusting module are used for controlling the first charging current I1 and the second charging current I2 to increase, and accelerating the time when the voltage value on the first capacitor C1 reaches a first threshold value and the time when the voltage value on the second capacitor C2 reaches a second threshold value, so that the period of the output clock signal CLK _ M is shortened; when the period of the output clock signal CLK _ M is shortened, the control signal generated by the negative feedback adjusting module is used to control the first charging current I1 and the second charging current I2 to decrease, and slow down the time when the voltage value of the first capacitor C1 reaches the first threshold and the time when the voltage value of the second capacitor C2 reaches the second threshold, so as to prolong the period of the output clock signal CLK _ M and stabilize the output clock signal CLK _ M.
As shown in fig. 7, another specific implementation form of the clock generation module is shown, and a waveform diagram corresponding to a key node is shown in fig. 8, compared with the structure of fig. 3, this embodiment shows an internal structure diagram of an SR flip-flop and an internal implementation diagram of an output clock signal CLK _ M and an inverted signal thereof, in this embodiment, the SR flip-flop is formed by two input NOR gates NOR2, an output signal of the SR flip-flop is shaped by two inverters to obtain the output clock signal CLK _ M, and an inverted signal xCLK _ M of the output clock signal is obtained by one inverter. And different from the structure shown in fig. 3, in the present embodiment, the output clock signal CLK _ M is used to control the second switch SW2, and the inverted signal xCLK _ M of the output clock signal is used to control the first switch SW1, it should be clear to those skilled in the art that the specific implementation structure of the SR flip-flop and the switching control interchange of the output clock signal CLK _ M and its inverted signal to the first switch SW1 and the second switch SW2 are all based on the design concept of the present invention, and are not used to limit the protection scope of the present invention.
The operation of the present embodiment will be described with reference to the waveform shown in fig. 8, in which the SR flip-flop is formed by a nor gate, when the X point (i.e., the S input terminal of the SR flip-flop) is at a low level and the Y point (i.e., the R input terminal of the SR flip-flop) is at a high level, the inverted signal xCLK _ M of the output clock signal is at a low level, the output clock signal CLK _ M is at a high level, the first switch SW1 controlled by the inverted signal xCLK _ M of the output clock signal is turned off, the first charging current I1 charges the first capacitor C1, the second switch SW2 controlled by the output clock signal CLK _ M is turned on, the charge stored in the second capacitor C2 at the previous time is rapidly discharged to the ground through the second switch SW2, the Y point potential rapidly changes from the high level to the low level, the I1 still charges the first capacitor C1, the voltage VC1 on the first capacitor C1 reaches the high threshold level of the first schmitt1, the potential at the point X keeps low level, at this time, the output state of the SR flip-flop keeps unchanged, the inverted signal xCLK _ M of the output clock signal keeps low level, the output clock signal CLK _ M keeps high level, and after the voltage VC1 on the first capacitor C1 reaches the high level threshold of the first schmitt1, the potential at the point X changes from low level to high level, so that the output state of the SR flip-flop changes, the inverted signal xCLK _ M of the output clock signal changes to high level, and the output clock signal CLK _ M changes to low level. At this time, the first switch SW1 is turned on, the second switch SW2 is turned off, the charge on the first capacitor C1 is rapidly discharged to the ground through the first switch SW1, the potential at the point X is rapidly changed from a high level to a low level, the second capacitor C2 starts to be charged through the second charging current I2, the potential at the point Y is kept at the low level until the high level threshold of the second Schmitt2 is reached, the output of the SR flip-flop is kept at the last moment, the inverted signal xCLK _ M of the output clock signal is still at the high level, and the output clock signal CLK _ M is still at the low level; when the voltage VC2 on the second capacitor C2 reaches the high level threshold of the second Schmitt2, the Y-point potential changes from low level to high level, so that the output state of the SR flip-flop changes, the inverted signal xCLK _ M of the output clock signal changes to low level, the output clock signal CLK _ M changes to high level, the first switch SW1 is controlled to be turned off, the second switch SW2 is turned on, so that the first charging current I1 starts to charge the first capacitor C1, and the voltage on the second capacitor C2 at the previous moment is quickly discharged to the ground through the second switch SW2, the X-point potential remains low level, the Y-point potential changes from high level to low level quickly, and the above steps are repeated to generate the output clock signal CLK _ M of the required frequency. As shown in fig. 2, an implementation form of the negative feedback adjusting module is provided, which includes a frequency divider DIV _ P, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a third capacitor C3, a fourth capacitor C4, a first current source I3, a second current source I4, a second resistor R2, a fifth capacitor C5, a sixth capacitor C6 and an amplifier Amp, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are charging and discharging capacitors, the fifth capacitor C5 and the sixth capacitor C6 are energy storage capacitors, the first switch SW1, the second switch SW2, the third switch SW2, the fourth switch SW2, the fifth switch 2 and the sixth switch SW2 are controlled switches, the first switch SW2 is controlled by a clock signal CLK _ M, the second switch SW2 is controlled by a clock signal xcsw 2, the second switch SW2 is controlled by a clock signal xcsw 36n 2, the fourth switch SW4 and the fifth switch SW5 are controlled by an inverted signal xCLK _ N of the first clock signal.
As shown in fig. 6, another implementation form of the negative feedback adjusting module is provided, and compared with the structure of fig. 2, the invention adds a third resistor R3, a third resistor R3 and a sixth capacitor C6 at the output end of the amplifier Amp for RC filtering.
The frequency divider DIV _ P divides the output clock signal CLK _ M to generate a first clock signal CLK _ N, controls the third switch SW3 and the sixth switch SW6 to turn off, the fourth switch SW4 and the fifth switch SW5 to turn on when the first clock signal CLK _ N is in a first state, and controls the third switch SW3 and the sixth switch SW6 to turn on, and the fourth switch SW4 and the fifth switch SW5 to turn off when the first clock signal CLK _ N is in a second state; one end of the third capacitor C3 is connected to one ends of the first current source I3 and the fifth switch SW5, and is grounded after passing through the third switch SW3, and the other end is grounded; one end of the fourth capacitor C4 is connected to the second current source I4 and one end of the sixth switch SW6, passes through the fourth switch SW4, and is grounded, and the other end is grounded; one end of the second resistor R2 is connected to the other end of the fifth switch SW5 and the other end of the sixth switch SW6, and the other end thereof is connected to the positive input end of the amplifier Amp and grounded through the fifth capacitor C5; the negative input end of the amplifier Amp is connected with the reference voltage, and the output end of the amplifier Amp outputs the control signal and is grounded after passing through the sixth capacitor C6. It can be seen that when the period of the output clock signal CLK _ M becomes longer, the voltage value of the control signal increases, and the current values of the mirrored first and second charging currents I1 and I2 also increase; when the period of the output clock signal CLK _ M becomes short, the voltage value of the control signal decreases, and the current values of the mirrored first and second charging currents I1 and I2 also decrease.
First, a divider DIV _ P is used to divide an output clock signal CLK _ M to obtain a first clock signal CLK _ N, where the division multiple is P, xCLK _ N is an inverted signal of the first clock signal, and the first clock signal CLK _ N and the inverted signal xCLK _ M have the same frequency and a phase difference of 180 °, and the output clock signal CLK _ M and the inverted signal xCLK _ M also have the same frequency and a phase difference of 180 °. The first clock signal CLK _ N and its inverted signal xCLK _ N control the on/off of the third switch SW3, the fourth switch SW4, the fifth switch SW5 and the sixth switch SW6, so that the change of the output clock signal CLK _ M is reflected to a point B (i.e., the positive input end of the amplifier Amp), a point B voltage (i.e., the voltage VC5 on the fifth capacitor in fig. 5) and the reference voltage VREF are operated by the amplifier Amp to generate a control signal for controlling the gate voltage of the first NMOS transistor M1, and further the change of the output clock signal CLK _ M is fed back to the first charging current I1 and the second charging current I2, and the magnitudes of the first charging current I1 and the second charging current I2 are adjusted, thereby realizing the adjustment of the frequency of the output clock signal CLK _ M.
Specifically, when the period of the output clock signal CLK _ M is affected and the period is longer, the period of the divided first clock signal CLK _ N and its inverse signal xCLK _ N is also longer, so that the charging time of the third capacitor C3 and the fourth capacitor C4 is longer, the average value of the voltage VC5 at the point B is larger, and exceeds the reference voltage VREF, a level VC6 higher than the previous time is obtained at the point C of the output terminal of the amplifier, i.e. the gate voltage Vgate _ M1 of the first NMOS transistor M1 is increased, since the first NMOS transistor M1 is a voltage control type device, the drain current increases with the increase of the gate voltage, when the voltage at the point C is increased, the current flowing through the first NMOS transistor M1 increases, the current flowing through the first NMOS transistor M1 is copied by the current mirror formed by the first PMOS transistor M2 and the second PMOS transistor M382 to obtain a first charging current I1 synchronously increased, and the current I68584 is also copied by the current mirror formed by the first PMOS transistor M633 and the third PMOS transistor M73742, so that the charging current of the first capacitor C1 and the second capacitor C2 at the charging time is increased, the charging time to reach the turn-on threshold of the corresponding schmitt trigger will be shortened, so that the period of the output clock signal CLK _ M is shortened.
Similarly, when the output clock signal CLK _ M is affected and the period becomes short, the period of the divided clock first clock signal CLK _ N and its inverted signal xCLK _ N also becomes short, the charging time of the third capacitor C3 and the fourth capacitor C4 becomes short, the average value of the voltage VC5 at the point B becomes small and smaller than the reference voltage VREF, a level VC6 lower than the previous moment is obtained at the point C of the output terminal of the amplifier Amp, that is, the gate voltage Vgate _ M1 of the first NMOS transistor M1 decreases, since the first NMOS transistor M1 is a voltage control type device, the drain current decreases with the decrease of the gate voltage, when the voltage at the point C decreases, the current flowing through the first NMOS transistor M1 decreases, the current flowing through the first NMOS transistor M1 also decreases the charging current I68584 and the charging current I73784 obtained by the current mirror formed by the first PMOS transistor M2 and the second PMOS transistor M462 and the first PMOS transistor M2 and the third PMOS transistor M4, respectively, the charging current of the first capacitor C1 and the second capacitor C2 at the charging time is reduced, the charging time reaching the corresponding schmitt trigger turn-on threshold is prolonged, the period of the output clock signal CLK _ M is prolonged, and thus, a stable output clock signal CLK _ M is obtained at the output end through a negative feedback loop.
In addition, in order to increase the precision, in some embodiments, the first current source I3 and the second current source I4 may be set as trimmable current sources, the reference voltage VREF may also be set as trimmable voltage, the trimming manner may be arbitrarily selected and combined, and the first current source I3, the second current source I4, and the reference voltage VREF are trimmed according to actual situations, so that the precision of the output clock signal CLK _ M is improved.
Based on the above consideration, the invention designs a relaxation oscillator with negative feedback regulation and adjustability, which adjusts the charging time of a first capacitor C1 and a second capacitor C2 generating an output clock signal CLK _ M by introducing a negative feedback loop, so that the output clock signal CLK _ M can have better stability on process change, voltage change and temperature change, and the adjustable current source and the reference voltage can increase the precision.
Although only the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist of the present invention within the knowledge of those skilled in the art, and the changes are included in the scope of the present invention. Various modifications and variations of the present invention, such as using other structures to charge the capacitor to obtain the output clock signal, or using other structures to generate the control signal that varies with the variation of the output clock signal, can be made by those skilled in the art, and the present invention is intended to cover such modifications and variations as fall within the scope of the appended claims and their equivalents without departing from the design concept of the present invention.
Claims (7)
1. An analog oscillator circuit with negative feedback regulation function is characterized by comprising a clock generation module and a negative feedback regulation module,
the clock generation module is used for generating an output clock signal of the analog oscillator circuit, and comprises a first capacitor and a second capacitor, if the output clock signal is in a first state, a first charging current is controlled to charge the first capacitor and control the second capacitor to discharge, when the voltage value of the first capacitor reaches a first threshold value, the output clock signal is converted from the first state to a second state, a second charging current is controlled to charge the second capacitor and control the first capacitor to discharge, and when the voltage value of the second capacitor reaches a second threshold value, the output clock signal is converted from the second state to the first state;
the negative feedback adjusting module is used for generating a corresponding control signal according to the output clock signal, and when the period of the output clock signal is prolonged, the control signal generated by the negative feedback adjusting module is used for controlling the first charging current and the second charging current to increase, and accelerating the time when the voltage value on the first capacitor reaches the first threshold value and the time when the voltage value on the second capacitor reaches the second threshold value, so that the period of the output clock signal is shortened; when the period of the output clock signal is shortened, the control signal generated by the negative feedback adjusting module is used for controlling the first charging current and the second charging current to be reduced, and slowing down the time when the voltage value on the first capacitor reaches the first threshold value and the time when the voltage value on the second capacitor reaches the second threshold value, so that the period of the output clock signal is prolonged.
2. The analog oscillator circuit with negative feedback adjustment function of claim 1, wherein the clock generation module further comprises a first switch, a second switch, a first Schmitt trigger, a second Schmitt trigger, a first inverter, a second inverter, and an SR flip-flop,
one end of the first capacitor is connected with the first charging current and the input end of the first Schmitt trigger, and is grounded after passing through the first switch, and the other end of the first capacitor is grounded;
the input end of the first phase inverter is connected with the output end of the first Schmitt trigger, and the output end of the first phase inverter is connected with the S input end of the SR trigger;
one end of the second capacitor is connected with the second charging current and the input end of the second Schmitt trigger, and is grounded after passing through the second switch, and the other end of the second capacitor is grounded;
the input end of the second inverter is connected with the output end of the second Schmitt trigger, and the output end of the second inverter is connected with the R input end of the SR trigger;
the output end of the SR trigger outputs the output clock signal, when the output clock signal is in a first state, the first switch is controlled to be switched off, the second switch is controlled to be switched on, and when the output clock signal is in a second state, the first switch is controlled to be switched on, and the second switch is controlled to be switched off.
3. The analog oscillator circuit with negative feedback adjustment function of claim 1 or2, wherein the clock generation module further comprises a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a first resistor,
the grid electrode of the first NMOS tube is connected with the control signal, the source electrode of the first NMOS tube is grounded after passing through the first resistor, and the drain electrode of the first NMOS tube is connected with the grid electrode and the drain electrode of the first PMOS tube and the grid electrodes of the second PMOS tube and the third PMOS tube;
the drain electrodes of the second PMOS tube and the third PMOS tube respectively output the first charging current and the second charging current, and the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with power supply voltage;
when the period of the output clock signal is longer, the voltage value of the control signal is increased; when the period of the output clock signal becomes shorter, the voltage value of the control signal decreases.
4. The analog oscillator circuit with negative feedback regulation function of claim 3, wherein the negative feedback regulation module comprises a frequency divider, a third switch, a fourth switch, a fifth switch, a sixth switch, a third capacitor, a fourth capacitor, a first current source, a second resistor, a fifth capacitor, a sixth capacitor and an amplifier,
the frequency divider divides the frequency of the output clock signal to generate a first clock signal, controls the third switch and the sixth switch to be turned off and controls the fourth switch and the fifth switch to be turned on when the first clock signal is in a first state, and controls the third switch and the sixth switch to be turned on and controls the fourth switch and the fifth switch to be turned off when the first clock signal is in a second state;
one end of a third capacitor is connected with the first current source and one end of the fifth switch, is grounded after passing through the third switch, and the other end of the third capacitor is grounded;
one end of a fourth capacitor is connected with the second current source and one end of the sixth switch, is grounded after passing through the fourth switch, and the other end of the fourth capacitor is grounded;
one end of the second resistor is connected with the other end of the fifth switch and the other end of the sixth switch, and the other end of the second resistor is connected with the positive input end of the amplifier and is grounded after passing through the fifth capacitor;
the negative input end of the amplifier is connected with the reference voltage, and the output end of the amplifier outputs the control signal and is grounded after passing through the sixth capacitor.
5. The analog oscillator circuit with negative feedback regulation function of claim 4, wherein the negative feedback regulation module further comprises a third resistor, the third resistor is connected between the output terminal of the amplifier and the sixth capacitor, and the connection point of the third resistor and the sixth capacitor outputs the control signal.
6. The analog oscillator circuit with negative feedback adjustment function of claim 4 or 5, wherein the first current source and the second current source are adjustable current sources.
7. An analog oscillator circuit with negative feedback adjustment function as claimed in claim 4 or 5, wherein the reference voltage is adjustable.
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