WO2024077818A1

WO2024077818A1 - Voltage-controlled frequency circuit and related products

Info

Publication number: WO2024077818A1
Application number: PCT/CN2023/074939
Authority: WO
Inventors: 张涛; 江力; 杜得喜
Original assignee: 深圳英集芯科技股份有限公司
Priority date: 2022-10-09
Filing date: 2023-02-08
Publication date: 2024-04-18
Also published as: CN115296651A; CN115296651B

Abstract

Provided in the embodiments of the present application are a voltage-controlled frequency circuit and related products. In the voltage-controlled frequency circuit, a clock generation circuit generates a clock oscillation signal according to a charging current, the charging current being generated by a charging current varying circuit; and then the charging current varying circuit receives a feedback voltage and, according to the present first voltage interval amongst a plurality of voltage intervals involved in the feedback voltage, controls a plurality of charging current control units, so as to adjust the charging current output to the clock generation circuit. In this way, according to a different voltage range in which the feedback voltage falls, the method for gradually increasing the switching frequency slope stage by stage is used, such that when the feedback voltage changes, the switching frequency will not jump greatly. Therefore, power supply systems are stabilized, and for chips in quasi-resonance control modes, the valley-skipping phenomena are ameliorated, thus making the loops of the power supply systems more stable, and further relieving the noise problems of transformers.

Description

Voltage controlled frequency circuits and related products

This application claims the priority of the Chinese patent application filed with the China Patent Office on October 9, 2022, with application number 202211228279X and application name “Voltage-controlled frequency circuits and related products”, the entire contents of which are incorporated by reference in this application.

Technical Field

The present application belongs to the field of electronic technology, and specifically relates to a voltage-controlled frequency circuit and related products.

Background technique

In the power control chip, voltage control frequency technology is a method of changing the frequency by changing the voltage. In the switching power control system, the changes in output load and input voltage are adjusted by the voltage regulator diode TL431, changing the size of the optocoupler current, which is reflected in the voltage detected by the control chip at the FB end. The control chip changes the switching frequency and Ipeak value of the chip through the voltage control module inside the chip according to the voltage size of the FB port, thereby achieving output stability.

Traditional designs usually set the voltage of the FB port to a very narrow range, which makes the switching frequency have a large range of variation. When the frequency change slope is too fast, a small change in the VFB voltage causes a large change in the switching frequency. This may directly lead to system instability, especially for chips with quasi-resonant control mode, causing valley jumping problems, and causing power control system loop instability and transformer noise problems.

Summary of the invention

The embodiments of the present application provide a voltage-controlled frequency circuit and related products, so that when the feedback voltage changes, the switching frequency will not have a large jump, thereby stabilizing the power supply system; improving the valley jumping phenomenon of the chip with a quasi-resonant control method, stabilizing the power supply system loop, and alleviating the noise problem of the transformer.

In a first aspect, an embodiment of the present application provides a voltage-controlled frequency circuit, characterized in that it includes a clock generation circuit and a charging current variation circuit, wherein the charging current variation circuit includes a plurality of charging current control units;

The clock generating circuit is used to generate a clock oscillation signal according to a charging current, the charging current is generated by the charging current varying circuit, and the frequency of the clock oscillation signal is proportional to the current of the charging current;

The charging current variation circuit is connected to the clock generation circuit, and is used to receive a feedback voltage, and control the plurality of charging current control units according to the first voltage interval in which the feedback voltage is currently located, so as to adjust the charging current output to the clock generation circuit.

The voltage range of the feedback voltage includes multiple voltage intervals, and the first voltage interval is any one of the multiple voltage intervals.

In a second aspect, an embodiment of the present application provides a control chip circuit, wherein the control chip circuit includes the driving circuit as described in the first aspect.

In a third aspect, an embodiment of the present application provides a power adapter, which includes the driving circuit as described in the first aspect, or the control chip circuit as described in the second aspect.

In a fourth aspect, an embodiment of the present application provides an electronic device, which includes the voltage-controlled frequency circuit as described in the first aspect, or the control chip circuit as described in the second aspect, or the power adapter as described in the third aspect.

It can be seen that in the embodiment of the present application, first, the clock generating circuit generates a clock oscillation signal according to the charging current, and the charging current is generated by the charging current changing circuit; then, the charging current changing circuit receives the feedback voltage, and controls the multiple charging currents according to the first voltage interval currently in the multiple voltage intervals included in the feedback voltage. A current control unit is used to adjust the charging current output to the clock generation circuit. In this way, according to the different voltage ranges of the feedback voltage, the method of gradually increasing the switching frequency slope is adopted, and when the feedback voltage changes, the switching frequency will not have a large jump. This not only stabilizes the power supply system, but also improves the valley jumping phenomenon for chips with quasi-resonant control mode, making the power supply system loop more stable and alleviating the noise problem of the transformer.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG. 1a is a circuit diagram of a conventional voltage-controlled frequency circuit;

FIG1b is a comparison diagram of the feedback voltage VFB and the charging current in a conventional voltage-controlled frequency circuit;

FIG1c is a comparison diagram of feedback voltage VFB and switching frequency in a conventional voltage-controlled frequency circuit;

FIG2a is a schematic diagram of the structure of an NMOS tube provided in an embodiment of the present application;

FIG2b is a schematic diagram of the structure of a PMOS tube provided in an embodiment of the present application;

FIG3 is a schematic diagram of the structure of a voltage-controlled frequency circuit provided in an embodiment of the present application;

FIG4 is a circuit diagram of a charging current control unit provided in an embodiment of the present application;

FIG5 is a comparison diagram of the feedback voltage VFB and the charging current ICARCE1 provided in an embodiment of the present application;

FIG6 is a comparison diagram of the feedback voltage VFB and the switching frequency Fre-CLK1 provided in an embodiment of the present application;

FIG. 7 is a comparison diagram of the feedback voltage VFB and the clock frequency FCLK1 provided in an embodiment of the present application;

FIG8 is a circuit diagram of another charging current variation circuit provided in an embodiment of the present application;

FIG. 9 is a circuit diagram of a clock generation circuit provided in an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, systems, products or devices.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

As shown in Figure 1a, Figure 1a is a circuit diagram of a traditional voltage-controlled frequency circuit. Op amps A1 and A2 form a subtractor. When VFB<Vref0, op amp A2 clamps the voltage at point V1 to VFB. Op amp A1 clamps the voltage at point V2 to Vref0. Current I = (Vref0-VFB)/R1. Mirror current IK = I*K is generated by mirror tube P2. At the same time, after this mirror current passes through NMOS tubes N7 and N8, the mirror current generated is IR = I*K*R. P tubes P12 and P11 form a current mirror. IS = S*IREF0 (where IREF0 is the reference bias current). The charging current ICHARGE0＝IS-IR, that is, ICHARGE0＝S*IREF0-{(Vref0-VFB)*K*R/R1}. The magnitude of the charging current increases linearly with the increase of the VFB voltage. Similarly, the voltage control frequency Fre_clk＝ICHARGE0/(C1*Vref5) increases linearly with the increase of the VFB voltage.

As shown in Figure 1b, Figure 1b is a comparison diagram of the feedback voltage VFB and the charging current in a traditional voltage-controlled frequency circuit. As shown in Figure 1b, the charging current ICARGE0 is proportional to the feedback voltage VFB. When the feedback voltage VFB changes faster, the charging current ICARGE0 will jump quickly.

As shown in Figure 1c, Figure 1c is a comparison diagram of the feedback voltage VFB and the switching frequency in a traditional voltage-controlled frequency circuit. As shown in Figure 1c, the switching frequency Frequency is proportional to the feedback voltage VFB. When the feedback voltage VFB changes faster, the switching frequency Frequency will jump quickly.

Capacitor C1, comparator A3, inverter INV1, inverter INV2 and capacitor C12 form an OSC circuit, and its specific working principle is shown in Figure 1a:

(1) Initially, the voltage of capacitor C1 is "0", and the output of comparator A3 is 0, so VCLK = 0, switch tube N0 is turned off, and charging current ICHARGE0 starts to charge capacitor C1;

(2) During the charging process of capacitor C1, when V3>Vref5, the output signal of comparator A3 is reversed. After the delay TDELAY generated by inverter INV1 and C12, VCLK=1, switch N0 is turned on, and capacitor C1 is discharged.

(3) When V3<Vref5, A3 flips again, the output signal VCLK=0, the switch tube N0 is turned off, the charging current ICHARGE0 starts to charge the capacitor CT, and V3 increases;

(4) Repeat the steps in (2).

It can be seen that the traditional design usually sets the voltage of the FB port to a very narrow range, which makes the switching frequency have a large range of variation. When the frequency change slope is too fast, a small change in the VFB voltage causes a large change in the switching frequency. This may directly lead to system instability, especially for chips with quasi-resonant control mode, causing valley jumping problems; resulting in power control system loop instability and transformer noise problems.

To solve the above problems, an embodiment of the present application provides a voltage-controlled frequency circuit, the voltage-controlled frequency circuit includes a clock generation circuit and a charging current change circuit, and the charging current change circuit includes multiple charging current control units. The voltage-controlled frequency circuit can be applied to the scenario where the switching frequency is reduced to cause a voltage jump when the feedback voltage changes. The clock generation circuit can generate a clock oscillation signal according to the charging current, and the charging current is generated by the charging current change circuit; the feedback voltage is then received by the charging current change circuit, and the multiple charging current control units are controlled according to the first voltage interval currently in the multiple voltage intervals included in the feedback voltage, so as to adjust the charging current output to the clock generation circuit. This solution can be applied to a variety of scenarios, including but not limited to the application scenarios mentioned above, for example, it can be applied to chips with quasi-resonant control mode to improve the valley jumping phenomenon; it can be applied to transformers to alleviate the noise problem of transformers.

In an embodiment of the present application, as shown in FIG. 2a, FIG. 2a is a schematic diagram of the structure of an NMOS tube provided in an embodiment of the present application. For an NMOS tube, the first end of the NMOS tube is a gate, the second end is a source, the third end is a drain, the fourth end is a substrate, and the fourth end is grounded. As shown in FIG. 2b, FIG. 2b is a schematic diagram of the structure of a PMOS tube provided in an embodiment of the present application. For a PMOS tube, the first end of the PMOS tube is a gate, the second end is a source, the third end is a drain, the fourth end is a substrate, and the fourth end is used to connect to a power supply, such as VCC and VDD.

The specific voltage-controlled frequency circuit is introduced in detail below.

Please refer to FIG3 , which is a schematic diagram of the structure of a voltage-controlled frequency circuit 30 provided in an embodiment of the present application. The voltage-controlled frequency circuit 30 includes a clock generating circuit 310 and a charging current changing circuit 320 , and the charging current changing circuit 320 includes a plurality of charging current control units 321 ;

The clock generating circuit 310 is used to generate a clock oscillation signal according to the charging current, the charging current is generated by the charging current changing circuit 320, and the frequency of the clock oscillation signal is proportional to the current of the charging current;

The charging current variation circuit 320 is connected to the clock generation circuit, and is used to receive the feedback voltage, and control the plurality of charging current control units 321 according to the first voltage interval in which the feedback voltage is currently located, so as to adjust the charging current output to the clock generation circuit 310.

In a specific implementation, the embodiment of the present application divides the voltage range of the feedback voltage into multiple voltage intervals, and at the same time sets multiple charging current control units 321 in the above-mentioned charging current change circuit 320; the charging current control unit 321 is used to adjust the charging current in different change stages according to the different voltage intervals in which the feedback voltage is located, so that the switching frequency will not have a large jump.

Specifically, the charging current changes in the current change stage. When the voltage interval of the feedback voltage changes, it is necessary to switch to a change stage corresponding to the current voltage interval through multiple charging current control units 321. Therefore, when the feedback voltage changes across the voltage interval, the voltage will not suddenly jump. In addition, in each change stage, the change rate of the charging current is different.

It can be seen that in this embodiment, first, the clock oscillation signal is generated by the clock generating circuit 310 according to the charging current, and the charging current is generated by the charging current changing circuit 320; then, the feedback voltage is received by the charging current changing circuit 320, and according to the first voltage interval currently in the multiple voltage intervals included in the feedback voltage, the multiple charging current control units 321 are controlled to adjust the charging current output to the clock generating circuit 310. In this way, according to the different voltage ranges in which the feedback voltage is located, the method of increasing the switching frequency slope in stages is adopted, and when the feedback voltage changes, the switching frequency will not have a large jump. It not only stabilizes the power supply system, but also improves the valley jumping phenomenon for chips with quasi-resonant control mode, the power supply system loop is more stable, and the noise problem of the transformer can be alleviated.

In a possible embodiment, referring to FIG. 4 or FIG. 8 , the charging current variation circuit further includes a first comparator A1 , a first NMOS transistor N1 , a second NMOS transistor N2 , a first PMOS transistor P1 , a second PMOS transistor P2 and a first current source IREF1 ;

The positive input terminal of the first comparator A1 is connected to the feedback voltage, and the negative input terminal of the first comparator A1 is connected to the output terminal of the first comparator A1 and the multiple charging current control units 321 to control the multiple charging current control units 321 to adjust the charging current output to the clock generating circuit;

The drain of the first NMOS tube N1 is connected to the gate of the first NMOS tube N1 and the gate of the second NMOS tube N2, and the source of the first NMOS tube N1 and the source of the second NMOS tube N2 are both grounded; the drain of the second NMOS tube N2 is connected to the drain of the first PMOS tube P1 and the clock generating circuit; the gate of the first PMOS tube P1 is connected to the gate of the second PMOS tube P2, the drain of the second PMOS tube P2 and the input end of the first current source IREF1; the source of the first PMOS tube P1, the source of the second PMOS tube P2 and the multiple charging current control units 321 are all connected to the first power supply VCC, and the output end of the first current source IREF1 is grounded.

In a specific implementation, the first PMOS tube P1 and the second PMOS tube P2 are used to generate an initial charging current. The first comparator A1 receives and outputs the feedback voltage, cooperates with the multiple charging current change circuits to switch between different circuit change stages, and then adjusts the conduction state of the first NMOS tube N1 and the second NMOS tube N2 to obtain the corresponding adjustment current; finally, the charging current is obtained by subtracting the adjustment current from the initial charging current. Therefore, when the adjustment current is zero, the charging current is the maximum and equal to the initial charging current; when the adjustment current is equal to the initial charging current, the charging current is the minimum and equal to zero.

It can be seen that in this embodiment, the staged control of the charging current is achieved through the cooperation of the internal devices and units of the charging current variation circuit.

The specific circuit of the single charging current control unit 321 is introduced below.

In a possible embodiment, please refer to FIG. 4, which is a charging current control unit provided in an embodiment of the present application. The circuit diagram of the charging current control unit 321. The charging current control unit 321 includes a third PMOS tube P3, a fourth PMOS tube P4, a third NMOS tube N3, a first resistor R1 and a second comparator A2;

The source of the third PMOS tube P3 and the source of the fourth PMOS tube P4 are both connected to the first power supply VCC, the source of the first PMOS tube and the source of the second PMOS tube;

The gate of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4, the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3;

The drain of the fourth PMOS transistor P4 is connected to the drain of the first NMOS transistor and the gate of the first NMOS transistor;

The gates of the three NMOS transistors are connected to the output end of the second comparator A2, and the source of the third NMOS transistor N3 is connected to the inverting input end of the second comparator A2 and one end of the first resistor R1;

The non-inverting input terminal of the second comparator A2 is connected to the first reference voltage;

The other end of the first resistor R1 is connected to the output end of the first comparator and the inverting input end of the first comparator.

It can be understood that the third PMOS tube P3, the fourth PMOS tube P4, the third NMOS tube N3, the first resistor R1 and the second comparator A2 can be components in any charging current control unit 321; the first reference voltage can be the reference voltage in any charging current control unit 321.

In a specific implementation, the third PMOS tube P3 and the fourth PMOS tube P4 form a current mirror. The first reference voltage in the second comparator A2 is compared with the feedback voltage output by the first comparator. If the feedback voltage is less than the first reference voltage, the third NMOS tube N3 is started, and then the current mirror formed by the third PMOS tube P3 and the fourth PMOS tube P4 starts to work, and the driving current output from the fourth PMOS tube P4 is K times the current of the third PMOS tube P3, that is, K*I1. Then, the conduction state of the first NMOS tube and the second NMOS tube is adjusted by the driving current to obtain the corresponding adjustment current. Finally, the size of the charging current is adjusted according to the adjustment current.

It can be seen that in this embodiment, the charging current control unit 321 compares the reference voltage with the feedback voltage, and when the feedback voltage is greater than the reference voltage, the charging current control unit 321 is started to adjust the charging current.

Please refer to Fig. 5, which is a comparison diagram of the feedback voltage VFB and the charging current ICARCE1 provided in an embodiment of the present application. It can be seen from the figure that as the feedback voltage VFB increases, the charging current ICARCE1 increases.

Please refer to Fig. 6, which is a comparison diagram of the feedback voltage VFB and the switching frequency Fre-CLK1 provided in an embodiment of the present application. It can be seen from the figure that as the feedback voltage VFB increases, the switching frequency Fre-CLK1 increases.

Please refer to Fig. 7, which is a comparison diagram of the feedback voltage VFB and the clock frequency FCLK1 provided in an embodiment of the present application. It can be seen from the figure that as the feedback voltage VFB increases, the clock frequency FCLK1 increases.

Please refer to FIG. 8 and FIG. 9 , and the solution of the present application will be described below through three frequency change phase solutions.

In a possible embodiment, FIG8 is a circuit diagram of another charging current variation circuit provided in an embodiment of the present application. The charging current variation circuit includes a first charging current control unit, a second charging current control unit, and a third charging current control unit;

The first charging current control unit includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, a fourth comparator A4 and a second resistor R2;

The second charging current control unit includes a seventh PMOS tube P7, an eighth PMOS tube P8, a sixth NMOS tube N6, a fifth comparator A5 and a third resistor R3;

The third charging current control unit includes a ninth PMOS transistor P9, a tenth PMOS transistor P10, a seventh NMOS transistor N7, a sixth comparator A6 and a fourth resistor R4;

The source of the fifth PMOS tube P5 is connected to the source of the sixth PMOS tube P6, the source of the seventh PMOS tube P7, the source of the eighth PMOS tube P8, the source of the ninth PMOS tube P9, the source of the tenth PMOS tube P10, The first power supply VCC, the source of the first PMOS tube and the source of the second PMOS tube;

The gate of the fifth PMOS tube P5 is connected to the gate of the sixth PMOS tube P6, the drain of the fifth PMOS tube P5 and the drain of the fifth NMOS tube N5; the drain of the sixth PMOS tube P6 is connected to the drain of the eighth PMOS tube P8, the drain of the tenth PMOS tube P10, the drain of the first NMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube;

The gate of the fifth NMOS transistor is connected to the output end of the fourth comparator A4, and the source of the fifth NMOS transistor N5 is connected to the inverting input end of the fourth comparator A4 and one end of the second resistor R2; the non-inverting input end of the fourth comparator A4 is connected to the third reference voltage Vref3; the other end of the second resistor R2 is connected to one end of the third resistor R3, one end of the fourth resistor R4, the output end of the first comparator and the inverting input end of the first comparator;

The gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8, the drain of the seventh PMOS transistor P7 and the drain of the sixth NMOS transistor N6; the gate of the sixth NMOS transistor N6 is connected to the output end of the fifth comparator A5, and the source of the sixth NMOS transistor N6 is connected to the inverting input end of the fifth comparator A5 and the other end of the third resistor R3; the non-inverting input end of the fifth comparator A5 is connected to the fourth reference voltage Vref4;

The gate of the ninth PMOS tube P9 is connected to the gate of the tenth PMOS tube P10, the drain of the ninth PMOS tube P9 and the drain of the seventh NMOS tube N7; the gate of the seventh NMOS tube N7 is connected to the output end of the sixth comparator A6, and the source of the seventh NMOS tube N7 is connected to the inverting input end of the sixth comparator A6 and the other end of the fourth resistor R4; the non-inverting input end of the sixth comparator A6 is connected to the fifth reference voltage Vref5.

For example, the first comparator and the fourth comparator A4, the fifth comparator A5 and the sixth comparator A6 respectively form a subtractor.

For example, the third reference voltage Vref3 is greater than the fourth reference voltage Vref4, and the fourth reference voltage Vref4 is greater than the fifth reference voltage Vref5.

In a specific implementation, when the feedback voltage is greater than the third reference voltage, the fourth comparator A4, the fifth comparator A5 and the sixth comparator A6 all output a low level, and the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7 are turned off respectively, so that the fifth PMOS tube P5, the seventh PMOS tube P7, the ninth PMOS tube P9, the sixth PMOS tube P6, the eighth PMOS tube P8 and the tenth PMOS tube P10 are also turned off, and the first NMOS tube and the second NMOS tube are all turned off, and the charging current reaches a maximum value, that is, the charging current ICHRGE1=L*IREF1; the clock frequency also reaches a maximum, the maximum clock frequency FCLK1=(L*IREF1)*Vref4/CT1 (ignoring the delay between CT1 and INV1); and thus the switching frequency reaches a maximum.

When the feedback voltage is greater than the fourth reference voltage and less than the third reference voltage, the fourth comparator A4 outputs a high level, turns on the fifth NMOS tube N5, and turns on the fifth PMOS tube P5 and the sixth PMOS tube P6; the first current output by the sixth PMOS tube P6 to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is K times the current of the fifth PMOS tube P5; the current of the fifth PMOS tube P5 is I1=(Vref3-VFB)/R2, and the first current IK=K*I1=K*(Vref1-VFB)/R2;

The second current of the second NMOS tube is J times of the first current, that is, the second current IJ=J*K*I1=J*K*(Vref1-VFB)/R2;

The third current of the first PMOS tube is L times of the first current source, and the current of the first current source is IREF1; the third current is the initial charging current, that is, L*IREF1;

The charging current is equal to the third current minus the second current, that is, the charging current ICHARGE1 = L*IREF1 - IJ = L*IREF1 - J*K*(Vref1 - VFB)/R2.

When the feedback voltage is greater than the fifth reference voltage and less than the fourth reference voltage, the fourth comparator A4 and the fifth comparator A5 both output a high level, turning on the fifth NMOS transistor N5 and the sixth NMOS transistor N6 respectively, so that the The fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are all turned on; the first current output by the sixth PMOS tube P6 to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is K times the current of the fifth PMOS tube P5, that is, the first current IK＝K*I1＝K*(Vref1-VFB)/R2. The fourth current output by the eighth PMOS tube P8 to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is N times the current of the seventh PMOS tube P7; the current I2 of the seventh PMOS tube P7＝(Vref4-VFB)/R2, and the fourth current IN＝N*I2＝N*(Vref4-VFB)/R3;

The second current of the second NMOS tube is equal to J times the sum of the first current and the fourth current, that is, the second current IJ=J*K*(Vref3-VFB)/R2+J*N*(Vref4-VFB)/R3;

The third current of the first PMOS tube is L times of the first current source, that is, the third current=L*IREF1;

The charging current is equal to the third current minus the second current, that is, the charging current ICHARGE1 = L*IREF1-J*K*(Vref3-VFB)-J*N*(Vref4-VFB)/R3.

When the feedback voltage is less than the fifth reference voltage, the fourth comparator A4, the fifth comparator A5 and the sixth comparator A6 all output a high level, and respectively turn on the fifth NMOS tube N5, the sixth NMOS tube N6 and the seventh NMOS tube N7, so that the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7, the eighth PMOS tube P8, the ninth PMOS tube P9 and the tenth PMOS tube P10 are all turned on; the first current output by the sixth PMOS tube P6 to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is K times the current of the fifth PMOS tube P5, that is, the first current IK=K*I1=K*(Vref3-VFB)/R2;

The fourth current outputted by the eighth PMOS transistor P8 to the drain and gate of the first NMOS transistor and the gate of the second NMOS transistor is N times the current of the seventh PMOS transistor P7, IN=N*I2=N*(Vref4-VFB)/R3;

The fifth current output by the tenth PMOS transistor P10 to the drain and gate of the first NMOS transistor and the gate of the second NMOS transistor is M times the current of the ninth PMOS transistor P9, and the current IM of the ninth PMOS transistor P9 is M*I3=M*(Vref5-VFB)/R4;

The second current of the second NMOS tube is equal to J times the sum of the first current, the fourth current and the fifth current, that is, the second current IJ=J*(IK+IN+IM);

The charging current is equal to the third current minus the second current, that is, the charging current ICHARGE1 = L*IREF1-J*(IK+IN+IM).

It can be seen that in this embodiment, the magnitude of the charging current gradually decreases in stages as the VFB voltage decreases. The change in the charging slope gradually increases according to the range of the VFB voltage (i.e., the FB voltage gradually increases), and the switching frequency change rate gradually increases, thereby avoiding the problem of excessive switching frequency jumps, resulting in system instability and noise.

In a possible embodiment, FIG9 is a circuit diagram of a clock generation circuit provided in an embodiment of the present application. The clock generation circuit includes a first capacitor CT1, a second capacitor CT2, a first inverter INV1, a second inverter INV2, a fourth NMOS transistor N4, and a third comparator A3;

The non-inverting input terminal of the third comparator A3 is connected to the drain of the fourth NMOS tube N4, one end of the first capacitor CT1, the drain of the second NMOS tube and the drain of the first PMOS tube; the inverting input terminal of the third comparator A3 is connected to the second reference voltage;

The output end of the third comparator A3 is connected to the input end of the first inverter INV1; the output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and one end of the second capacitor CT2; the output end of the second inverter INV2 outputs the clock oscillation signal and is connected to the gate of the fourth NMOS transistor N4;

The other end of the second capacitor CT2, the source of the fourth NMOS transistor N4 and the other end of the first capacitor CT1 are all grounded.

In a specific implementation, at the initial moment, the voltage of the first capacitor CT1 is zero, the output of the third comparator A3 is low level, so that the output of the second inverter INV2 is low level, the fourth NMOS tube N4 is turned off, and the charging current starts to charge the first capacitor CT1;

During the charging current charging the first capacitor CT1, if the voltage of the first capacitor CT1 is greater than the second reference voltage, the output of the third comparator A3 is high, so that the output of the second inverter INV2 is high, the fourth NMOS tube N4 is turned on, and the first capacitor CT1 starts to discharge;

When the voltage of the first capacitor CT1 is less than the second reference voltage, the output of the third comparator A3 is at a low level, so that the output of the second inverter INV2 is at a low level, the fourth NMOS tube N4 is turned off, the charging current starts to charge the first capacitor CT1, and the voltage of the first capacitor CT1 starts to increase.

In a specific implementation, the working process of the clock generation circuit of the present invention is as follows:

(1) Initially, the voltage of the first capacitor CT1 of the first capacitor CT1CT is "0", and the output of the third comparator A3 is 0, so VCLK1 = 0, the switch tube N5 is turned off, and the charging current ICHARGE1 starts to charge the capacitor C1;

(2) During the charging process of the CT capacitor, when V8>Vref4, the output signal of comparator A3 is reversed. After the delay TDELAY1 generated by the inverter INV1, CT1, VCLK1=1, the switch tube N5 is turned on, and the capacitor CT is discharged.

(3) When V8<Vref4, A3 flips again, the output signal VCLK1=0, the switch tube N5 is turned off, the charging current ICHARGE1 starts to charge the capacitor CT, and V8 increases;

(4) Repeat the steps in step (2).

It can be seen that, in this embodiment, by controlling the charging current, the clock generating circuit generates a clock oscillation signal to control the external device.

The embodiment of the present application provides a control chip circuit, the control chip circuit includes the above-mentioned voltage-controlled frequency circuit. The above-mentioned voltage-controlled frequency circuit can be applied to the control chip, so that the above-mentioned voltage-controlled frequency circuit is applied to corresponding scenarios to realize corresponding functions.

An embodiment of the present application provides a power adapter, and the above-mentioned voltage-controlled frequency circuit and the above-mentioned control chip circuit can be applied to the power adapter.

An embodiment of the present application provides an electronic device, which may include the voltage-controlled frequency circuit or chip control circuit or power adapter described above. For example, the electronic device may be a power bank, a charger, or any device that requires a voltage-controlled oscillator.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions without departing from the spirit and scope of the present invention, and can make various changes and modifications, including the combination of the above-mentioned different functions and implementation steps, including software and hardware implementation methods, all of which are within the scope of protection of the present invention.

Claims

A voltage-controlled frequency circuit, characterized in that it comprises a clock generating circuit and a charging current varying circuit, wherein the charging current varying circuit comprises a plurality of charging current controlling units;

The clock generating circuit is used to generate a clock oscillation signal according to a charging current, the charging current is generated by the charging current varying circuit, and the frequency of the clock oscillation signal is proportional to the current of the charging current;

The charging current variation circuit is connected to the clock generation circuit, and is used to receive a feedback voltage, and control the plurality of charging current control units according to the first voltage interval in which the feedback voltage is currently located, so as to adjust the charging current output to the clock generation circuit.

The voltage range of the feedback voltage includes multiple voltage intervals, and the first voltage interval is any one of the multiple voltage intervals;

The charging current changes in the current change phase. When the voltage range of the feedback voltage changes, the multiple charging current control units switch to the change phase corresponding to the current voltage range to avoid sudden jumps in the switching frequency when the feedback voltage changes across the voltage range.
The voltage-controlled frequency circuit according to claim 1, characterized in that the charging current variation circuit further comprises a first comparator, a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube and a first current source;

The positive input terminal of the first comparator is connected to the feedback voltage, and the inverting input terminal of the first comparator is connected to the output terminal of the first comparator and the multiple charging current control units to control the multiple charging current control units to adjust the charging current output to the clock generating circuit;

The drain of the first NMOS tube is connected to the gate of the first NMOS tube and the gate of the second NMOS tube, and the source of the first NMOS tube and the source of the second NMOS tube are both grounded; the drain of the second NMOS tube is connected to the drain of the first PMOS tube and the clock generating circuit; the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the second PMOS tube and the input end of the first current source; the source of the first PMOS tube, the source of the second PMOS tube and the multiple charging current control units are all connected to the first power supply VCC, and the output end of the first current source is grounded.
The voltage-controlled frequency circuit according to claim 2, characterized in that the clock generating circuit comprises a first capacitor, a second capacitor, a first inverter, a second inverter, a fourth NMOS tube and a third comparator;

The non-inverting input terminal of the third comparator is connected to the drain of the fourth NMOS tube, one end of the first capacitor, the drain of the second NMOS tube and the drain of the first PMOS tube; the inverting input terminal of the third comparator is connected to the second reference voltage;

The output end of the third comparator is connected to the input end of the first inverter; the output end of the first inverter is connected to the input end of the second inverter and one end of the second capacitor; the output end of the second inverter outputs the clock oscillation signal and is connected to the gate of the fourth NMOS tube;

The other end of the second capacitor, the source of the fourth NMOS transistor and the other end of the first capacitor are all grounded.
The voltage-controlled frequency circuit according to claim 2 or 3, characterized in that the charging current control unit comprises a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a first resistor and a second comparator;

The source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the first power supply VCC, the source of the first PMOS tube and the source of the second PMOS tube;

The gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, the drain of the third PMOS tube and the drain of the third NMOS tube;

The drain of the fourth PMOS tube is connected to the drain of the first NMOS tube and the gate of the first NMOS tube;

The gates of the three NMOS transistors are connected to the output end of the second comparator, and the source of the third NMOS transistor is connected to the an inverting input terminal of a second comparator and one end of the first resistor;

The non-inverting input terminal of the second comparator is connected to the first reference voltage;

The other end of the first resistor is connected to the output end of the first comparator and the inverting input end of the first comparator.
The voltage-controlled frequency circuit according to claim 3, characterized in that the charging current variation circuit comprises a first charging current control unit, a second charging current control unit and a third charging current control unit;

The first charging current control unit includes a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube, a fourth comparator and a second resistor;

The second charging current control unit includes a seventh PMOS tube, an eighth PMOS tube, a sixth NMOS tube, a fifth comparator and a third resistor;

The third charging current control unit includes a ninth PMOS tube, a tenth PMOS tube, a seventh NMOS tube, a sixth comparator and a fourth resistor;

The source of the fifth PMOS tube is connected to the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the eighth PMOS tube, the source of the ninth PMOS tube, the source of the tenth PMOS tube, the first power supply VCC, the source of the first PMOS tube and the source of the second PMOS tube;

The gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the drain of the fifth PMOS tube and the drain of the fifth NMOS tube; the drain of the sixth PMOS tube is connected to the drain of the eighth PMOS tube, the drain of the tenth PMOS tube, the drain of the first NMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube;

The gate of the fifth NMOS tube is connected to the output end of the fourth comparator, and the source of the fifth NMOS tube is connected to the inverting input end of the fourth comparator and one end of the second resistor; the non-inverting input end of the fourth comparator is connected to the third reference voltage; the other end of the second resistor is connected to one end of the third resistor, one end of the fourth resistor, the output end of the first comparator and the inverting input end of the first comparator;

The gate of the seventh PMOS tube is connected to the gate of the eighth PMOS tube, the drain of the seventh PMOS tube and the drain of the sixth NMOS tube; the gate of the sixth NMOS tube is connected to the output end of the fifth comparator, and the source of the sixth NMOS tube is connected to the inverting input end of the fifth comparator and the other end of the third resistor; the non-inverting input end of the fifth comparator is connected to the fourth reference voltage;

The gate of the ninth PMOS tube is connected to the gate of the tenth PMOS tube, the drain of the ninth PMOS tube and the drain of the seventh NMOS tube; the gate of the seventh NMOS tube is connected to the output end of the sixth comparator, and the source of the seventh NMOS tube is connected to the inverting input end of the sixth comparator and the other end of the fourth resistor; the non-inverting input end of the sixth comparator is connected to the fifth reference voltage.
The voltage-controlled frequency circuit according to claim 5, characterized in that:

When the feedback voltage is greater than the third reference voltage, the fourth comparator, the fifth comparator and the sixth comparator all output a low level, and the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube are turned off respectively, so that the fifth PMOS tube, the seventh PMOS tube, the ninth PMOS tube, the sixth PMOS tube, the eighth PMOS tube and the tenth PMOS tube are also turned off, and the first NMOS tube and the second NMOS tube are all turned off, and the charging current reaches a maximum value;

When the feedback voltage is greater than the fourth reference voltage and less than the third reference voltage, the fourth comparator outputs a high level, turns on the fifth NMOS tube, and turns on the fifth PMOS tube and the sixth PMOS tube; the first current output by the sixth PMOS tube to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is K times the current of the fifth PMOS tube, the second current of the second NMOS tube is J times the first current, the third current of the first PMOS tube is L times the first current source, and the charging current is equal to the third current minus the second current;

When the feedback voltage is greater than the fifth reference voltage and less than the fourth reference voltage, the fourth comparator and the fifth The comparators all output high level, and turn on the fifth NMOS tube and the sixth NMOS tube respectively, so that the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube and the eighth PMOS tube are all turned on; the first current output by the sixth PMOS tube to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is K times the current of the fifth PMOS tube, and the fourth current output by the eighth PMOS tube to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is N times the current of the seventh PMOS tube; the second current of the second NMOS tube is equal to J times the sum of the first current and the fourth current, the third current of the first PMOS tube is L times the first current source, and the charging current is equal to the third current minus the second current;

When the feedback voltage is less than the fifth reference voltage, the fourth comparator, the fifth comparator and the sixth comparator all output a high level, and respectively turn on the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube, so that the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are all turned on; the first current output by the sixth PMOS tube to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is K times the current of the fifth PMOS tube, the fourth current output by the eighth PMOS tube to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is N times the current of the seventh PMOS tube, and the fifth current output by the tenth PMOS tube to the drain and gate of the first NMOS tube and the gate of the second NMOS tube is M times the current of the ninth PMOS tube; the second current of the second NMOS tube is equal to J times the sum of the first current, the fourth current and the fifth current, the third current of the first PMOS tube is L times the first current source, and the charging current is equal to the third current minus the second current.
The voltage-controlled frequency circuit according to claim 5, characterized in that:

At the initial moment, the voltage of the first capacitor is zero, the output of the third comparator is at a low level, so that the output of the second inverter is at a low level, the fourth NMOS tube is turned off, and the charging current starts to charge the first capacitor;

In the process of charging the first capacitor by the charging current, when the voltage of the first capacitor is greater than the second reference voltage, the output of the third comparator is high level, so that the output of the second inverter is high level, the fourth NMOS tube is turned on, and the first capacitor starts to discharge;

When the voltage of the first capacitor is less than the second reference voltage, the output of the third comparator is low level, so that the output of the second inverter is low level, the fourth NMOS tube is turned off, the charging current starts to charge the first capacitor, and the voltage of the first capacitor starts to increase.
A control chip circuit, characterized in that the control chip circuit comprises the voltage-controlled frequency circuit as described in any one of claims 1-7.
A power adapter, characterized in that the power adapter comprises the voltage-controlled frequency circuit as described in any one of claims 1 to 7, or the control chip circuit as described in claim 8.
An electronic device, characterized in that the electronic device comprises the voltage-controlled frequency circuit as described in any one of claims 1 to 7, or the control chip circuit as described in claim 8, or the power adapter as described in claim 9.