CN206432966U

CN206432966U - RC oscillating circuits

Info

Publication number: CN206432966U
Application number: CN201720124960.8U
Authority: CN
Inventors: 虞峰; 张和平; 张奇
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2017-02-10
Filing date: 2017-02-10
Publication date: 2017-08-22
Anticipated expiration: 2027-02-10

Abstract

The utility model provides a kind of RC oscillating circuits, it is only necessary to a comparison module, simplifies circuit；Simultaneously, reference voltage and comparison voltage are related to a bias current, obtained and power supply and all incoherent output clock frequency of bias current so as to cancel out each other, so by reducing bias current to na rank with regard to the super low-power consumption of integrated circuit can be reached, while can guarantee that the high accuracy of output clock frequency again.

Description

RC oscillating circuits

Technical field

The utility model is related to technical field of integrated circuits, more particularly to a kind of RC oscillating circuits.

Background technology

Oscillator is prevalent in SOC, and clock signal is provided to Digital Logical Circuits.In different applications, The structure and performance parameters difference that it is required is very big.Oscillator is generally divided into RC oscillators (also referred to as relaxor), LC vibrations Device, quartz oscillator etc..RC oscillators be using the most universal a kind of oscillating circuit, the simple in construction of it, cost compared with Low, power consumption is also smaller.

The general structure of traditional relaxor is as shown in figure 1, main produced by charging current generation circuit 10, discharge current Raw circuit 11, generating circuit from reference voltage 12, bias current generating circuit 13, gate-controlled switch SW1 and gate-controlled switch SW2, a high position Comparator Comp1 and low level comparator Comp2 and the grade of logic control circuit 14 circuit composition.Generating circuit from reference voltage 12 is carried For high threshold reference voltage VH and Low threshold reference voltage VL, bias current generating circuit 13 provides bias current to high bit comparison Device Comp1 and low level comparator Comp2, charging current generation circuit 10 and discharge current generation circuit 11 provide charging current I1 With discharge current I2.

Its operation principle is：Just during upper electricity, electric capacity C voltage is low level, and the electric capacity C voltage is input to high position Comp1 and low level comparator Comp2 produces a logical signal, and then gate-controlled switch SW1 is turned on, gate-controlled switch SW2 shut-offs, i.e., Charging current I1 charges to electric capacity C, and at this moment the voltage on electric capacity C can constantly rise, until rising to high position High threshold reference voltage VH set by Comp1；At this moment saltus step occurs for output logic signal, and then turns off gate-controlled switch SW1, leads Logical gate-controlled switch SW2, i.e. discharge current I2 are discharged electric capacity C, and at this moment electric capacity C voltage can be reduced constantly, until being reduced to Low threshold reference voltage VL set by low level comparator Comp2 so that output logic signal saltus step again, now enters and fills again Electricity condition, so constantly can just export continuously waveform on the oscillator repeatedly.If the charging interval is t, and I1 =I2=I_C, then have：

As shown from the above formula, the output clock frequency of oscillator and high threshold reference voltage VH and Low threshold reference voltage VL difference (VH-VL), electric capacity C, capacitance current I_CCorrelation, therefore traditional relaxor output clock frequency is by power source temperature And process variations influence is larger.In addition, in addition it is also necessary to which extra circuit produces high threshold reference voltage VH, Low threshold reference voltage VL and charging current I1, discharge current I2, so that super low-power consumption (nA ranks) performance can not be realized.

Utility model content

The purpose of this utility model is to provide a kind of RC oscillating circuits, to realize super low-power consumption performance.

Based on above-mentioned purpose, the utility model provides a kind of RC oscillating circuits, and the RC oscillating circuits include：Voltage x current Generation module, charge-discharge modules, comparison module and Logic control module, wherein,

The voltage x current generation module produces reference voltage and bias current, and the reference voltage is supplied to the comparison Module, the bias current is supplied to the charge-discharge modules；

The charge-discharge modules produce comparison voltage, and the comparison voltage is supplied to the comparison module；

The comparison module produces comparison signal according to the reference voltage and the comparison voltage, and the comparison signal is carried Supply the Logic control module；

The Logic control module produces logical signal according to the comparison signal, and the logical signal is supplied to the electricity Current voltage generation module and the charge-discharge modules.

Optionally, in described RC oscillating circuits, the voltage x current generation module includes voltage x current generation circuit, The voltage x current generation circuit produces first threshold reference voltage and Second Threshold reference voltage, and the first threshold is with reference to electricity Second Threshold reference voltage described in pressure ratio is high, and the first threshold reference voltage and the Second Threshold reference voltage are provided respectively To the comparison module.

Optionally, in described RC oscillating circuits, the voltage x current generation module includes also including first choice electricity The first threshold reference voltage or the Second Threshold reference voltage are supplied to described by road, the first choice circuit selection Comparison module.

Optionally, in described RC oscillating circuits, the first choice circuit can including the first gate-controlled switch and second Control switch, first gate-controlled switch and second gate-controlled switch are with the voltage x current generation circuit and described being compared mould Block is connected, and the first threshold reference voltage is supplied to the comparison module, second threshold by first gate-controlled switch Value reference voltage is supplied to the comparison module by second gate-controlled switch.

Optionally, in described RC oscillating circuits, the logical signal includes first switch signal and second switch is believed Number, the first switch signal and the second switch signal are on the contrary, first switch signal control described first is controllable opens The connecting and disconnecting of pass, the second switch signal controls the connecting and disconnecting of second gate-controlled switch.

Optionally, in described RC oscillating circuits, the charge-discharge modules include charging and discharging currents generation circuit, first Electric capacity and the second selection circuit, second selection circuit control the charging and discharging currents generation circuit produce charging current or Discharge current, the charging current or discharge current are supplied to first electric capacity, to produce comparison voltage.

Optionally, in described RC oscillating circuits, second selection circuit can including the 3rd gate-controlled switch and the 4th Control switch, the charging and discharging currents generation circuit connects the first level, the charging and discharging currents by the 3rd gate-controlled switch Generation circuit connects second electrical level by the 4th gate-controlled switch, and first level is higher than the second electrical level.

Optionally, in described RC oscillating circuits, the first switch signal also controls the 3rd gate-controlled switch Connecting and disconnecting, the second switch signal also controls the connecting and disconnecting of the 4th gate-controlled switch.

Optionally, in described RC oscillating circuits, the positive pole of first electric capacity is connected with the comparison module, described The negative pole of first electric capacity is connected with the second electrical level.

Optionally, in described RC oscillating circuits, the comparison module is comparator circuit, and the reference voltage is provided To the normal phase input end of the comparator circuit, the comparison voltage is supplied to the inverting input of the comparator circuit.

Optionally, in described RC oscillating circuits, the comparator circuit includes positive input block, anti-phase input list Member, comparing unit and output unit；Wherein, the positive input block receives reference voltage, and the reference voltage of reception is carried Supply the comparing unit；The anti-phase input unit receives comparison voltage, and the comparison voltage of reception is supplied into the ratio Compared with unit；The comparing unit reference voltage and the comparison voltage, produce comparison signal, and compare letter by described Number it is supplied to the output unit；The output unit exports the comparison signal；

Wherein, the positive input block includes the first FET；The anti-phase input unit includes the second field-effect Pipe；The comparing unit includes the 3rd FET, the 4th FET, the 5th FET, the 6th FET and the 7th FET；The output unit includes the 8th FET and the 9th FET；

Wherein, the source electrode and the 7th FET of the source electrode of first FET and second FET Drain electrode connection；The drain electrode of first FET and the grid of the 5th FET, the 5th FET The grid connection of drain electrode and the 8th FET；

The drain electrode and the leakage of the grid and the 4th FET of the 3rd FET of second FET Pole is connected；

Drain electrode and the grid of nineth FET of the drain electrode of 3rd FET with the 6th FET Pole is connected；

The grid of 4th FET is connected with the grid of the 5th FET；

The grid of 6th FET is connected with the grid of the 7th FET；

The drain electrode of 8th FET is connected with the drain electrode of the 9th FET；

Source electrode, the source electrode of the 4th FET, the source electrode of the 5th FET of 3rd FET And the source electrode of the 8th FET is connected with first level；The source electrode of 6th FET, the described 7th The source electrode of the source electrode of FET and the 9th FET is connected with the second electrical level.

Optionally, in described RC oscillating circuits, first field-effect, second FET, the described 6th FET, the 7th FET and the 9th FET are N-type FET；3rd FET, institute The 4th FET, the 5th FET and the 8th FET are stated for p-type FET.

Optionally, in described RC oscillating circuits, the Logic control module includes multiple connected phase inverters.

Optionally, in described RC oscillating circuits, the voltage x current generation circuit includes the biased electrical being sequentially connected Road, first resistor, the tenth FET and the 11st FET；Wherein, the first resistor and the tenth FET Drain electrode connection, the source electrode of the tenth FET is connected with the drain electrode of the 11st FET, described 11st The source electrode of effect pipe is connected with the second electrical level.

Optionally, in described RC oscillating circuits, the tenth FET and the 11st FET are N-type FET.

Optionally, in described RC oscillating circuits, the biasing circuit includes second resistance.

Optionally, in described RC oscillating circuits, the biasing circuit includes start-up circuit, discharge circuit, pressure difference production Raw circuit, pressure stream change-over circuit, circuit mirror current and electric current draw circuit；Wherein,

The output of the start-up circuit is supplied to the discharge circuit；

The normal phase input end of the discharge circuit is connected with the pressure difference generation circuit, the anti-phase input of the discharge circuit End is connected with the pressure stream change-over circuit, and the output end of the discharge circuit is connected with the circuit mirror current；

The pressure difference generation circuit is also connected with the pressure stream change-over circuit；

The electric current is drawn circuit and is connected with the circuit mirror current.

Optionally, in described RC oscillating circuits, the start-up circuit includes the 12nd FET, the 13rd effect It should manage and the second electric capacity, wherein, the grid of the 12nd FET and the drain electrode of the 13rd FET and described The positive pole connection of second electric capacity；The source electrode of 12nd FET and the source electrode of the 13rd FET are with first Level is connected, and the negative pole of second electric capacity is connected with second electrical level；The drain electrode and the described tenth of 12nd FET The grid of three FETs is used as output end；

The discharge circuit includes the 14th FET and the 15th FET, wherein, the 14th field-effect The grid of pipe is connected with the drain electrode of the 14th FET and the grid of the 15th FET, wherein, described The source electrode of 14 FETs as the discharge circuit normal phase input end；The source electrode of 15th FET is used as institute State the inverting input of discharge circuit；The drain electrode and the drain electrode conduct of the 15th FET of 14th FET The output end of the discharge circuit；

The pressure difference generation circuit includes the first triode and the second triode, the base stage of first triode, described Uniform second electricity of the colelctor electrode of the colelctor electrode of first triode, the base stage of second triode and second triode The emitter stage of flushconnection, the emitter stage of first triode and second triode is used as the defeated of the pressure difference generation circuit Go out end；

The pressure stream change-over circuit includes 3rd resistor, the two ends of the 3rd resistor respectively with second triode The source electrode connection of emitter stage and the 15th FET；

The circuit mirror current includes the 16th FET and the 17th FET, the 16th FET Grid be connected with the grid of the 17th FET, the source electrode of the 16th FET and it is described 17th effect Should the source electrode of pipe be connected with first level, the drain electrode of the 16th FET and the 17th FET The input drained as the circuit mirror current；

The electric current, which draws circuit, includes the 18th FET, the source electrode and described first of the 18th FET Level is connected, the drain electrode of the 18th FET as the biasing circuit output end.

Optionally, in described RC oscillating circuits, the 12nd FET, the 13rd FET, institute The 16th FET, the 17th FET and the 18th FET are stated for p-type FET；Described tenth Four FETs and the 15th FET are N-type FET.

Optionally, in described RC oscillating circuits, the charging and discharging currents generation circuit includes charging current and produces electricity Road and discharge current generation circuit；The charging current generation circuit produces charging current, and the charging current is supplied to First electric capacity；The discharge current generation circuit produces discharge current, and the discharge current is supplied into described first Electric capacity.

Optionally, in described RC oscillating circuits, the charging current generation circuit include the 19th FET and 20th FET, the discharge current generation circuit includes the 21st FET and the 22nd FET；Its In, the grid of the 19th FET is connected with the grid of the 20th FET, the 19th FET Drain electrode be connected with the 21st the missing for FET, the source electrode of the 19th FET can by the described 3rd Control switch is connected with first level；The drain electrode of 20th FET and the grid of the 20th FET and The drain electrode connection of 22nd FET, the source electrode of the 20th FET is connected with first level；Institute The grid for stating the 21st FET is connected with the grid of the 22nd FET, the 21st FET Source electrode be connected by the 4th gate-controlled switch with the second electrical level；The source electrode of 22nd FET with it is described Second electrical level is connected；Wherein, the company of the grid of the grid of the 21st FET and the 22nd FET Contact as the charging and discharging currents generation circuit input；The drain electrode and the described 21st of 19th FET The tie point of the drain electrode of FET as the charging and discharging currents generation circuit output end.

Optionally, in described RC oscillating circuits, the 19th FET and the 20th FET are P Type FET, the 21st FET and the 22nd FET are N-type FET.

Optionally, in described RC oscillating circuits, the 3rd gate-controlled switch is a p-type FET, the described 4th Gate-controlled switch is a N-type FET.

In the RC oscillating circuits that the utility model is provided, it is only necessary to a comparison module, circuit is simplified；Meanwhile, ginseng Examine voltage and comparison voltage related to a bias current, obtain all uncorrelated to power supply and bias current so as to cancel out each other Output clock frequency, so by reducing bias current to na rank with regard to the super low-power consumption of integrated circuit can be reached, simultaneously The high accuracy of output clock frequency is can guarantee that again.

Brief description of the drawings

Fig. 1 is the general structure schematic diagram of traditional relaxor；

Fig. 2 is the structural representation of the RC oscillating circuits of the utility model embodiment one；

Fig. 3 is the circuit diagram of the RC oscillating circuits of the utility model embodiment one；

Fig. 4 is the comparison voltage VC and first threshold reference voltage VH of the utility model embodiment one, Second Threshold reference Voltage VL schematic diagram；

Fig. 5 is the output clock signal clk OUT of the utility model embodiment one schematic diagram；

Fig. 6 is the circuit diagram of the RC oscillating circuits of the utility model embodiment two；

Fig. 7 is the structural representation of the biasing circuit of the utility model embodiment two；

Fig. 8 is the circuit diagram of the biasing circuit of the utility model embodiment two.

Embodiment

Below in conjunction with the drawings and specific embodiments to the utility model proposes RC oscillating circuits be described in further detail. According to following explanation and claims, advantages and features of the present utility model will become apparent from.It should be noted that, accompanying drawing is used Very simplified form and use non-accurately ratio, only to it is convenient, lucidly aid in illustrating the utility model embodiment Purpose.Particularly, each accompanying drawing needs the emphasis shown different, often all employs different ratios.

【Embodiment one】

Fig. 2 is refer to, it is the structural representation of the RC oscillating circuits of the utility model embodiment one.As shown in Fig. 2 institute Stating RC oscillating circuits includes：Voltage x current generation module 20, charge-discharge modules 21, comparison module 22 and Logic control module 23, Wherein, the voltage x current generation module 20 produces reference voltage and bias current Ib, and the reference voltage is supplied to the ratio Compared with module 22, the bias current Ib is supplied to the charge-discharge modules 21；The charge-discharge modules 21 produce comparison voltage, institute State comparison voltage and be supplied to the comparison module 22；The comparison module 22 is produced according to the reference voltage and the comparison voltage Raw comparison signal, the comparison signal is supplied to the Logic control module 23；The Logic control module 23 is according to the ratio Logical signal is produced compared with signal, the logical signal is supplied to the voltage x current generation module 20 and the charge-discharge modules 21。

Please continue to refer to Fig. 2, specifically, the voltage x current generation module 20 includes voltage x current generation circuit 200, institute State voltage x current generation circuit 200 and produce first threshold reference voltage VH and Second Threshold reference voltage VL, the first threshold Reference voltage VH is higher than the Second Threshold reference voltage VL, first threshold reference voltage VH and the Second Threshold reference Voltage VL is respectively supplied to the comparison module 22 (i.e. in the embodiment of the present application, the first threshold reference voltage VH and institute Second Threshold reference voltage VL is stated not while being supplied to the comparison module 22).

Further, the voltage x current generation module 20 includes also including first choice circuit 201, the first choice Circuit 201 selects the first threshold reference voltage VH or described Second Threshold reference voltages VL being supplied to the comparison module 22.In the embodiment of the present application, the first choice circuit 201 includes the first gate-controlled switch SW1 and the second gate-controlled switch SW2, The first gate-controlled switch SW1 and the second gate-controlled switch SW2 are with the voltage x current generation circuit 200 and described being compared Module 22 is connected, and the first threshold reference voltage VH is supplied to the comparison module 22 by the first gate-controlled switch SW1, The Second Threshold reference voltage VL is supplied to the comparison module 22 by the second gate-controlled switch SW2.

In the embodiment of the present application, the logical signal includes first switch signal Q and second switch signal XQ, and described the The one switching signal Q and second switch signal XQ is on the contrary, the first switch signal Q controls the first gate-controlled switch SW1 Connecting and disconnecting (namely control the first threshold reference voltage VH whether be supplied to the comparison module 22), described second Switching signal XQ controls the connecting and disconnecting of the second gate-controlled switch SW2 (namely to control the Second Threshold reference voltage VL Whether it is supplied to the comparison module 22).

Further, the charge-discharge modules 21 include charging and discharging currents generation circuit 210, the choosings of the first electric capacity C1 and second Circuit (not indicated in Fig. 2) is selected, second selection circuit controls the charging and discharging currents generation circuit 210 to produce charging current Or discharge current, the charging current or discharge current are supplied to the first electric capacity C1, to produce comparison voltage.Specifically , second selection circuit includes the 3rd gate-controlled switch SW3 and the 4th gate-controlled switch SW4, and the charging and discharging currents produce electricity Road 210 passes through the first level of the 3rd gate-controlled switch SW3 connections (being herein supply voltage) VDD, the charging and discharging currents production Raw circuit 210 passes through the 4th gate-controlled switch SW4 connections second electrical level (the being herein ground voltage) GND, first level VDD is higher than the second electrical level GND.The positive pole of the first electric capacity C1 is connected with the comparison module 22, first electric capacity C1 negative pole is connected with the second electrical level GND.

Here, the first switch signal Q also control the 3rd gate-controlled switch SW3 connecting and disconnecting (namely control Produce charging current whether), the second switch signal XQ also control the 4th gate-controlled switch SW4 connecting and disconnecting ( I.e. whether control produces discharge current).

In the embodiment of the present application, the comparison module 22 is comparator circuit, and the reference voltage is (herein including first Threshold reference voltage VH and Second Threshold reference voltage VL) it is supplied to the normal phase input end of the comparator circuit 22, the ratio Compared with the inverting input that voltage is supplied to the comparator circuit 22.

In the embodiment of the present application, the comparator circuit 22 includes positive input block, anti-phase input unit, comparison list Member and output unit；Wherein, the positive input block receives reference voltage, and the reference voltage of reception is supplied into the ratio Compared with unit；The anti-phase input unit receives comparison voltage, and the comparison voltage of reception is supplied into the comparing unit；It is described The comparing unit reference voltage and the comparison voltage, produce comparison signal, and the comparison signal is supplied into institute State output unit；The output unit exports the comparison signal.

Specifically, refer to Fig. 3, it is the circuit diagram of the RC oscillating circuits of the utility model embodiment one.Such as Fig. 2 With shown in Fig. 3, in the embodiment of the present application, the positive input block includes the first FET M1；The anti-phase input list Member includes the second FET M2；The comparing unit includes the 3rd FET M3, the 4th FET M4, the 5th field-effect Pipe M5, the 6th FET M6 and the 7th FET M7；The output unit includes the 8th FET M8 and the 9th effect Should pipe M9.

Wherein, the source electrode and the 7th effect of the source electrode of the first FET M1 and the second FET M2 Should pipe M7 drain electrode connection；The drain electrode of the first FET M1 and the grid of the 5th FET M5, the described 5th FET M5 drain electrode and the 8th FET M8 grid connection；The drain electrode of the second FET M2 with it is described 3rd FET M3 grid and the 4th FET M4 drain electrode connection；The drain electrode of the 3rd FET M3 with The drain electrode of the 6th FET M6 and the grid connection of the 9th FET M9；The grid of the 4th FET M4 Pole is connected with the grid of the 5th FET M5；The grid of the 6th FET M6 and the 7th FET M7 Grid connection；The drain electrode of the 8th FET M8 is connected with the drain electrode of the 9th FET M9；Described 3rd Effect pipe M3 source electrode, the source electrode of the 4th FET M4, the source electrode of the 5th FET M5 and described 8th Effect pipe M8 source electrode is connected with the first level VDD；The source electrode of the 6th FET M6, the 7th field-effect Pipe M7 source electrode and the 9th FET M9 source electrode are connected with the second electrical level GND.

In the embodiment of the present application, the first field-effect M1, the second FET M2, the 6th FET M6, the 7th FET M7 and the 9th FET M9 are N-type FET；The 3rd FET M3, institute The 4th FET M4, the 5th FET M5 and the 8th FET M8 are stated for p-type FET.

Please continue to refer to Fig. 2 and Fig. 3, in the embodiment of the present application, the Logic control module 23 includes multiple connected Phase inverter, it is preferred that the quantity of the phase inverter is 3~5.Here, the quantity of the phase inverter is three, respectively the One phase inverter I1, the second phase inverter I2 and the 3rd phase inverter I3.

Further, the tunnel of voltage x current generation circuit 200 includes the biasing circuit being sequentially connected (here, described inclined Circuits include second resistance R2), first resistor R1, the tenth FET M10 and the 11st FET M11；Wherein, it is described First resistor R1 is connected with the drain electrode of the tenth FET M10, the source electrode and the described tenth of the tenth FET M10 One FET M11 drain electrode connection, the source electrode of the 11st FET M11 is connected with the second electrical level GND. This, the tenth FET M10 and the 11st FET M11 are N-type FET.

Here, obtaining first threshold reference voltage at the second resistance R2 and the first resistor R1 tie point VH, and it is supplied to the first gate-controlled switch SW1；In the first resistor R1 and the tie point of the tenth FET M10 Place obtains Second Threshold reference voltage VL, and is supplied to the second gate-controlled switch SW2.The first gate-controlled switch SW1 and institute Grids of the second gate-controlled switch SW2 with the first FET M1 is stated to be connected.The tenth FET M10 and described 11 FET M11 tie point output bias current.

Please continue to refer to Fig. 2 and Fig. 3, in the embodiment of the present application, the charging and discharging currents generation circuit includes charging electricity Flow generation circuit and discharge current generation circuit；The charging current generation circuit produces charging current, and the charging is electric Stream is supplied to the first electric capacity C1；The discharge current generation circuit produces discharge current, and the discharge current is provided To the first electric capacity C1.So as to produce the comparison voltage of height change in the positive pole of the first electric capacity C1.

Further, the charging current generation circuit includes the 19th FET M19 and the 20th FET M20, the discharge current generation circuit includes the 21st FET M21 and the 22nd FET M22；Wherein, institute The grid for stating the 19th FET M19 is connected with the grid of the 20th FET M20, the 19th FET M19 drain electrode is connected with the 21st the missing for FET M21, and the source electrode of the 19th FET M19 passes through The 3rd gate-controlled switch SW3 is connected with the first level VDD；The drain electrode of the 20th FET M20 and described the 20 FET M20 grid and the 22nd FET M22 drain electrode connection, the 20th FET M20 source electrode is connected with the first level VDD；The grid of the 21st FET M21 with described 22nd Effect pipe M22 grid connection, the source electrode of the 21st FET M21 passes through the 4th gate-controlled switch SW4 and institute State second electrical level GND connections；The source electrode of the 22nd FET M22 is connected with the second electrical level GND；Wherein, institute The tie point for stating the 21st FET M21 grid and the grid of the 22nd FET M22 fills as described The input of discharge current generation circuit 210；The drain electrode of the 19th FET M19 and the 21st FET The tie point of M21 drain electrode as the charging and discharging currents generation circuit 210 output end.

In the embodiment of the present application, the 19th FET M19 and the 20th FET M20 are p-type Effect pipe, the 21st FET M21 and the 22nd FET M22 are N-type FET.Further , the 3rd gate-controlled switch SW3 is a p-type FET (the 23rd FET M23), the 4th gate-controlled switch SW4 is a N-type FET (the 24th FET M24), i.e., pass through a p-type FET and a N-type respectively Effect pipe realizes the function of two gate-controlled switches.

In the embodiment of the present application, the grid and the 22nd FET of the 21st FET M21 The tie point input of reception bias current Ib of M22 grid；The drain electrode of the 19th FET M19 and described 21st effect Should the pipe M21 tie point of drain electrode be connected with the first electric capacity C1.

Accordingly, the present embodiment also provides a kind of method of work of the RC oscillating circuits, specifically includes：Voltage x current is produced Raw module 20 produces reference voltage and bias current, and the reference voltage is supplied to comparison module 22, and the bias current is provided To charge-discharge modules 21；The charge-discharge modules 21 produce comparison voltage, and the comparison voltage is supplied to the comparison module 22； The comparison module 22 produces comparison signal, and the comparison signal is supplied to Logic control module 23；The Logic control module 23 produce logical signal according to the comparison signal, and the logical signal is supplied to the voltage x current generation module 20 and described Charge-discharge modules 21.

The specific work process of the RC oscillating circuits is as follows：Power supply electrifying initial stage (namely the RC oscillating circuits start During work), the first electric capacity C1 cathode voltage VC (usual) is 0 level, and with the inverting input phase of comparator circuit 22 Even, now the normal phase input end of comparator circuit 22 either accesses first threshold reference voltage VH or Second Threshold with reference to electricity VL is pressed all to be higher than VC voltages, so that the output of comparator circuit 22 high level (i.e. described comparison signal is high level), by patrolling Collect first switch signal Q and low level second switch signal XQ (i.e. described logical signals that control module 23 produces high level First switch signal Q and low level second switch signal XQ including high level).The first switch signal Q of high level and low The second switch signal XQ of level controls the first gate-controlled switch SW1 closures, and the second gate-controlled switch SW2 disconnects, first threshold reference Voltage VH is transmitted to the normal phase input end of comparator circuit 22.Meanwhile, low level second switch signal XQ controls the 3rd are controllable to open SW3 closures are closed, the 4th gate-controlled switch SW4 disconnects, the 19th FET M19 outputs charging current starts to enter the first electric capacity C1 Row charging.

First electric capacity C1 cathode voltage VC raises (i.e. described comparison voltage start rise) gradually, when being charged to higher than the During one threshold reference voltage VH (when the comparison voltage is higher than first threshold reference voltage VH), comparator circuit 22 exports electricity Flat upset, output low level (i.e. described comparison signal is changed into low level) produces low level the by Logic control module 23 One switching signal Q and high level second switch signal XQ (i.e. described logical signal be changed into low level first switch signal Q and The second switch signal XQ of high level).Low level first switch signal Q and high level second switch signal XQ controls first Gate-controlled switch SW1 disconnects, and the second gate-controlled switch SW2 closures, Second Threshold reference voltage VL is transmitted to the positive of comparator circuit 22 Input.The second switch signal XQ of high level controls the 3rd gate-controlled switch SW3 to disconnect simultaneously, the 4th gate-controlled switch SW4 closures, 21st FET M21 output discharge currents start to discharge to the first electric capacity C1.

First electric capacity C1 cathode voltage VC slowly step-downs (i.e. described comparison voltage start reduction), when discharging into less than the During two threshold reference voltage VL (when the comparison voltage is less than Second Threshold reference voltage VL), comparator circuit 22 exports electricity Flat to overturn again, output high level (i.e. described comparison signal is changed into high level) produces high level by Logic control module 23 First switch signal Q and low level second switch signal XQ (i.e. described logical signal be changed into high level first switch letter Number and low level second switch signal).The first switch signal Q of high level and low level second switch signal XQ controls the One gate-controlled switch SW1 is closed, and the second gate-controlled switch SW2 disconnects, and first threshold reference voltage VH is being transmitted to comparator circuit 22 just Phase input.Low level second switch signal XQ controls the 3rd gate-controlled switch SW3 closures, and the 4th gate-controlled switch SW4 disconnects, the 19 FET M19 outputs charging current starts to charge to the first electric capacity C1 again.

Go round and begin again, height, which constantly occurs, for the comparison voltage VC of the first electric capacity C1 positive poles changes, specific as shown in Figure 4； The output level punctuated turning over of comparator circuit 22, just being produced after the shaping of Logic control module 23 has certain driving force Output clock signal clk OUT, it is specific as shown in Figure 5.Output clock signal clk OUT frequency can be calculated as follows：

V_H-V_L=I_R1·R₁

I_{C discharges}=I_{C charges}

I_M11=I_R1

From result, because the 11st FET M11 and the 21st FET M21 breadth length ratio is given , so output clock signal clk OUT frequency is only related to first resistor R1 with the first electric capacity C1, therefore by selecting to close The first suitable electric capacity C1 and first resistor R1, just can preferably be obtained by the less output of supply voltage, temperature and technogenic influence Clock signal clk OUT.In addition, output clock signal clk OUT frequency is with bias current Ib (namely I_R1) unrelated, therefore, the One electric capacity C1 and first resistor R1 resistance are constant, increase second resistance R2, it is possible to so that bias current Ib (namely I_R1) always NA ranks are reduced to, so that wastage in bulk or weight electric current reaches nA ranks, and now clock signal clk OUT frequency are exported still It is old constant.

During above, different phase is being charged and discharged, is passing through the first gate-controlled switch SW1 and the second gate-controlled switch SW2 Alternate conduction, the normal phase input end of comparator circuit 22 is equal to first threshold reference voltage VH in charging, in electric discharge etc. In Second Threshold reference voltage VL, so as to reach that a comparator circuit 22 is multiplexed the effect for making two comparators.

【Embodiment two】

The present embodiment two and the difference of embodiment one are that the biasing circuit includes start-up circuit, discharge circuit, pressure difference Generation circuit, pressure stream change-over circuit, circuit mirror current and electric current draw circuit.Specifically, Fig. 6 and Fig. 7 are refer to, wherein, The circuit diagram of the RC oscillating circuits of Fig. 6 the utility model embodiment two；Fig. 7 is the biased electrical of the utility model embodiment two The structural representation on road.As shown in Figure 6 and Figure 7, the biasing circuit 24 includes：Start-up circuit 240, discharge circuit 241, pressure difference Generation circuit 242, pressure stream change-over circuit 243, circuit mirror current 244 and electric current draw circuit 245；Wherein, it is described to start electricity The output on road 240 is supplied to the discharge circuit 241；The normal phase input end of the discharge circuit 241 produces electricity with the pressure difference Road 242 is connected, and the inverting input of the discharge circuit 241 is connected with the pressure stream change-over circuit 243, the discharge circuit 241 output end is connected with the circuit mirror current 244；The pressure difference generation circuit 242 also flows change-over circuit with the pressure 243 connections；The electric current is drawn circuit 245 and is connected with the circuit mirror current 244.

Although here, farthest reducing current branch, Er Qieli in view of the RC oscillating circuits in embodiment one By can above reach the requirement of super low-power consumption (nA ranks) performance.But, calculate bias current as follows：

For 3.3V system, V_GS(M10)≈ 0.7V, V_GS(M11)≈ 0.7V, will reach the bias current of 100nA sizes I_R1, then the resistance of about 20M ohm of size is needed, and the precision of this resistance directly influences output clock signal clk OUT's Frequency accuracy, therefore the width of resistance can not obtain too small again, realize 20M Ohmic resistances to waste the version of very large area Figure, that is, chip manufacturing cost.

Base this, form the technical scheme of the present embodiment two.

Further, Fig. 8 is referred to, it is the circuit diagram of the biasing circuit of the utility model embodiment two.Such as Fig. 7 With shown in Fig. 8, the start-up circuit 240 includes the 12nd FET M12, the 13rd FET M13 and the second electric capacity C2, Wherein, the grid of the 12nd FET M12 and the drain electrode of the 13rd FET M13 and the second electric capacity C2 Positive pole connection；The source electrode of the 12nd FET M12 and the source electrode of the 13rd FET M13 are electric with first Flat VDD connections, the negative pole of the second electric capacity C2 is connected with second electrical level GND；The drain electrode of the 12nd FET M12 and The grid of the 13rd FET M13 is used as output end.Wherein, the 12nd FET M12 and the described 13rd FET M13 is p-type FET.

The discharge circuit 241 includes the 14th FET M14 and the 15th FET M15, wherein, the described tenth Drain electrode and the grid of the ten five FET M15 of the four FET M14 grid with the 14th FET M14 Connection, wherein, the source electrode of the 14th FET M14 as the discharge circuit normal phase input end；Described 15th FET M15 source electrode as the discharge circuit inverting input；The drain electrode of the 14th FET M14 and institute The drain electrode for stating the 15th FET M15 is used as the output end of the discharge circuit.The 14th FET M14 and described 15th FET M15 is N-type FET.

The pressure difference generation circuit 242 includes the first triode Q1 and the second triode Q2, the first triode Q1's Base stage, the colelctor electrode of the first triode Q1, the base stage of the second triode Q2 and the second triode Q2 current collection The extremely uniform second electrical level GND connections, the emitter stage of the first triode Q1 and the second triode Q2 emitter stage It is used as the output end of the pressure difference generation circuit 242.

The two ends of the pressure stream change-over circuit 243 including 3rd resistor R3, the 3rd resistor R3 are respectively with described second Triode Q2 emitter stage and the 15th FET M15 source electrode connection.

The circuit mirror current 244 includes the 16th FET M16 and the 17th FET M17, the described tenth Six FET M16 grid is connected with the grid of the 17th FET M17, the 16th FET M16's Source electrode and the 17th FET M17 source electrode are connected with the first level VDD, the 16th FET M16 drain electrode and the drain electrode of the 17th FET M17 as the circuit mirror current 244 input.Described 16 FET M16 and the 17th FET M17 are p-type FET.

The electric current, which draws circuit 245, includes the 18th FET M18, the source electrode of the 18th FET M18 Be connected with the first level VDD, the drain electrode of the 18th FET M18 as the biasing circuit 24 output end. The 18th FET M18 is p-type FET.

In the embodiment of the present application, electric initial stage provides initial current on start-up circuit 240, helps circuit away from zero offset It is turned off after point, start completion and does not consume electric current；16th FET M16 and the 17th effect in circuit mirror current 244 Should pipe M17 breadth length ratios it is equal, it is ensured that two branch currents are equal；14th FET M14 and the 15th in discharge circuit 241 FET M15 breadth length ratios are equal, ensure that VA and VB point current potentials are equal by feedback principle；Pressure difference generation circuit 242 is by individual Number difference obtains different VBE and produces pressure difference；Pressure stream change-over circuit 243 is by the voltage difference that produces pressure difference generation circuit 242 Electric current is converted to, so that flowing through the second triode Q2 branch currents can be calculated as follows：

V_T≈27mV

From above formula, 30nA electric current is obtained, 3rd resistor R3 values are about 1M ohm.In the present embodiment, it is described First resistor R1 resistance is probably at 2 megohms~3 megohms, and the resistance of the 3rd resistor R3 is probably 0.5 megohm~2 Megohm.Except 3rd resistor R3, in the super low-power consumption current biasing circuit that the utility model is realized remaining FET and Area shared by electric capacity is less than the area shared by 500K Ohmic resistances, so while a part of circuit is added, as long as The resistance of big resistance is reduced, the area of domain can be still greatly reduced.

The use super low-power consumption current biasing circuit proposed in the utility model substitutes the inclined of big resistance (second resistance R2) This method of circuits, is not limited solely to this specific implementation that the present embodiment two is proposed, real according to other manner Existing super low-power consumption current biasing circuit, substitutes the biasing circuit of big resistance (second resistance R2), falls within this patent protection Scope.

As fully visible, on the one hand the utility model realizes two by a comparator circuit and two gate-controlled switch switchings The function of individual comparator, simplifies circuit, on the other hand the generation of reference voltage and is filled by ingenious simple circuit realiration The generation of discharge current, and all related to a bias current, is obtained with power supply and bias current not so as to cancel out each other Related output clock frequency, so by reducing bias current to na rank with regard to the super low-power consumption of overall circuit can be reached, It can guarantee that the high accuracy of output clock frequency again simultaneously.In addition, the utility model is further with a super low-power consumption current offset Circuit replaces the biasing circuit of more than ten M big resistance, substantially reduces the chip area of chip.

Such as design takes first threshold reference voltage VH Second Threshold reference voltages VL value to be 100mV, then first resistor R1 values are 2.5M ohm, add 3rd resistor R3 1M Ohmic resistances.20M resistance is compared before relatively, and area is reduced nearly 80%.

If we, which will design, obtains the more commonly used 32K output clock frequencies, the first electric capacity C1=1.56PF only need to be taken again, Operating current 200nA can be just realized, clock accuracy error is less than 5%, and chip area is less than 0.05mm²RC oscillating circuits. Certainly, this utility model line construction is not limited to produce this 32K output clock frequency, and design takes different first resistor R1 With the first electric capacity C1 values, it is possible to different output clock frequencies are obtained, with very wide application.

Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the utility model scope Calmly, the those of ordinary skill in the utility model field does according to the disclosure above content any change, modification, belonging to right will Seek the protection domain of book.

Claims

1. a kind of RC oscillating circuits, it is characterised in that the RC oscillating circuits include：Voltage x current generation module, discharge and recharge mould Block, comparison module and Logic control module, wherein,

The voltage x current generation module produces reference voltage and bias current, and the reference voltage, which is supplied to, described compares mould Block, the bias current is supplied to the charge-discharge modules；

The comparison module produces comparison signal according to the reference voltage and the comparison voltage, and the comparison signal is supplied to The Logic control module；

The Logic control module produces logical signal according to the comparison signal, and the logical signal is supplied to the voltage electricity Flow generation module and the charge-discharge modules.

2. RC oscillating circuits as claimed in claim 1, it is characterised in that the voltage x current generation module includes voltage x current Generation circuit, the voltage x current generation circuit produces first threshold reference voltage and Second Threshold reference voltage, described first Threshold reference voltage is higher than the Second Threshold reference voltage, and the first threshold reference voltage and the Second Threshold are with reference to electricity Pressure is respectively supplied to the comparison module.

3. RC oscillating circuits as claimed in claim 2, it is characterised in that the voltage x current generation module also includes the first choosing Circuit is selected, the first threshold reference voltage or the Second Threshold reference voltage are supplied to by the first choice circuit selection The comparison module.

4. RC oscillating circuits as claimed in claim 3, it is characterised in that the first choice circuit includes the first gate-controlled switch And second gate-controlled switch, first gate-controlled switch and second gate-controlled switch with the voltage x current generation circuit and institute Comparison module connection is stated, the first threshold reference voltage is supplied to the comparison module, institute by first gate-controlled switch State Second Threshold reference voltage and the comparison module is supplied to by second gate-controlled switch.

5. RC oscillating circuits as claimed in claim 4, it is characterised in that the logical signal includes first switch signal and the Two switching signals, the first switch signal and the second switch signal are on the contrary, first switch signal control described the The connecting and disconnecting of one gate-controlled switch, the second switch signal controls the connecting and disconnecting of second gate-controlled switch.

6. RC oscillating circuits as claimed in claim 5, it is characterised in that the charge-discharge modules are produced including charging and discharging currents Circuit, the first electric capacity and the second selection circuit, second selection circuit control the charging and discharging currents generation circuit generation to fill Electric current or discharge current, the charging current or discharge current are supplied to first electric capacity, to produce comparison voltage.

7. RC oscillating circuits as claimed in claim 6, it is characterised in that second selection circuit includes the 3rd gate-controlled switch And the 4th gate-controlled switch, the charging and discharging currents generation circuit connects the first level by the 3rd gate-controlled switch, described to fill Discharge current generation circuit connects second electrical level by the 4th gate-controlled switch, and first level is than the second electrical level It is high.

8. RC oscillating circuits as claimed in claim 7, it is characterised in that the first switch signal is also controlled the described 3rd can The connecting and disconnecting of switch are controlled, the second switch signal also controls the connecting and disconnecting of the 4th gate-controlled switch.

9. RC oscillating circuits as claimed in claim 8, it is characterised in that the positive pole of first electric capacity and the comparison module Connection, the negative pole of first electric capacity is connected with the second electrical level.

10. RC oscillating circuits as claimed in claim 9, it is characterised in that the comparison module is comparator circuit, the ginseng The normal phase input end that voltage is supplied to the comparator circuit is examined, the comparison voltage is supplied to the anti-phase of the comparator circuit Input.

11. RC oscillating circuits as claimed in claim 10, it is characterised in that the comparator circuit includes positive and inputs list Member, anti-phase input unit, comparing unit and output unit；Wherein, the positive input block receives reference voltage, and will receive Reference voltage be supplied to the comparing unit；The anti-phase input unit receives comparison voltage, and by the comparison voltage of reception It is supplied to the comparing unit；The comparing unit reference voltage and the comparison voltage, produce comparison signal, and The comparison signal is supplied to the output unit；The output unit exports the comparison signal；

Wherein, the positive input block includes the first FET；The anti-phase input unit includes the second FET；Institute Stating comparing unit includes the 3rd FET, the 4th FET, the 5th FET, the 6th FET and the 7th field-effect Pipe；The output unit includes the 8th FET and the 9th FET；

Wherein, the leakage of the source electrode of first FET and the source electrode and the 7th FET of second FET Pole is connected；The drain electrode of first FET and grid, the drain electrode of the 5th FET of the 5th FET And the grid connection of the 8th FET；

The drain electrode of second FET and the drain electrode of the grid and the 4th FET of the 3rd FET connect Connect；

The grid of the drain electrode of 3rd FET and the drain electrode of the 6th FET and the 9th FET connects Connect；

The grid of 4th FET is connected with the grid of the 5th FET；

The grid of 6th FET is connected with the grid of the 7th FET；

Source electrode, the source electrode of the 4th FET, the source electrode of the 5th FET and the institute of 3rd FET The source electrode for stating the 8th FET is connected with first level；The source electrode of 6th FET, the 7th effect Should the source electrode of pipe and the source electrode of the 9th FET be connected with the second electrical level.

12. RC oscillating circuits as claimed in claim 11, it is characterised in that first field-effect, second field-effect Pipe, the 6th FET, the 7th FET and the 9th FET are N-type FET；Described 3rd FET, the 4th FET, the 5th FET and the 8th FET are p-type FET.

13. RC oscillating circuits as claimed in claim 9, it is characterised in that the Logic control module includes multiple connected Phase inverter.

14. RC oscillating circuits as claimed in claim 9, it is characterised in that the voltage x current generation circuit includes connecting successively Biasing circuit, first resistor, the tenth FET and the 11st FET connect；Wherein, the first resistor and described the The drain electrode connection of ten FETs, the source electrode of the tenth FET is connected with the drain electrode of the 11st FET, institute The source electrode for stating the 11st FET is connected with the second electrical level.

15. RC oscillating circuits as claimed in claim 14, it is characterised in that the tenth FET and described 11st Effect pipe is N-type FET.

16. RC oscillating circuits as claimed in claim 14, it is characterised in that the biasing circuit includes second resistance.

17. RC oscillating circuits as claimed in claim 14, it is characterised in that the biasing circuit includes start-up circuit, amplifier Circuit, pressure difference generation circuit, pressure stream change-over circuit, circuit mirror current and electric current draw circuit；Wherein,

The output of the start-up circuit is supplied to the discharge circuit；

The normal phase input end of the discharge circuit is connected with the pressure difference generation circuit, the inverting input of the discharge circuit with The pressure stream change-over circuit connection, the output end of the discharge circuit is connected with the circuit mirror current；

18. RC oscillating circuits as claimed in claim 17, it is characterised in that

The start-up circuit includes the 12nd FET, the 13rd FET and the second electric capacity, wherein, described 12nd The grid of effect pipe is connected with the drain electrode of the 13rd FET and the positive pole of second electric capacity；12nd effect Should the source electrode of pipe and the source electrode of the 13rd FET be connected with the first level, the negative pole and second of second electric capacity Level is connected；The drain electrode of 12nd FET and the grid of the 13rd FET are used as output end；

The discharge circuit includes the 14th FET and the 15th FET, wherein, the 14th FET Grid is connected with the drain electrode of the 14th FET and the grid of the 15th FET, wherein, the described 14th The source electrode of FET as the discharge circuit normal phase input end；The source electrode of 15th FET is used as the fortune The inverting input on electric discharge road；The drain electrode of 14th FET and the drain electrode of the 15th FET are as described The output end of discharge circuit；

The pressure difference generation circuit includes the first triode and the second triode, the base stage of first triode, described first The uniform second electrical level of the colelctor electrode of the colelctor electrode of triode, the base stage of second triode and second triode connects Connect, the emitter stage of the emitter stage of first triode and second triode as the pressure difference generation circuit output End；

The pressure stream change-over circuit includes 3rd resistor, the transmitting of the two ends of the 3rd resistor respectively with second triode The source electrode connection of pole and the 15th FET；

The circuit mirror current includes the 16th FET and the 17th FET, the grid of the 16th FET Pole is connected with the grid of the 17th FET, the source electrode and the 17th FET of the 16th FET Source electrode be connected with first level, the drain electrode of the 16th FET and the drain electrode of the 17th FET It is used as the input of the circuit mirror current；

The electric current, which draws circuit, includes the 18th FET, source electrode and first level of the 18th FET Connection, the drain electrode of the 18th FET as the biasing circuit output end.

19. RC oscillating circuits as claimed in claim 18, it is characterised in that the 12nd FET, the described 13rd FET, the 16th FET, the 17th FET and the 18th FET are p-type field-effect Pipe；14th FET and the 15th FET are N-type FET.

20. RC oscillating circuits as claimed in claim 9, it is characterised in that the charging and discharging currents generation circuit includes charging Current generating circuit and discharge current generation circuit；The charging current generation circuit produces charging current, and by the charging Electric current is supplied to first electric capacity；The discharge current generation circuit produces discharge current, and the discharge current is provided To first electric capacity.

21. RC oscillating circuits as claimed in claim 20, it is characterised in that the charging current generation circuit includes the 19th FET and the 20th FET, the discharge current generation circuit include the 21st FET and the 22nd Effect pipe；Wherein, the grid of the 19th FET is connected with the grid of the 20th FET, and the described 19th The drain electrode of FET is connected with the 21st the missing for FET, and the source electrode of the 19th FET passes through institute The 3rd gate-controlled switch is stated to be connected with first level；The drain electrode of 20th FET and the 20th FET Grid and the 22nd FET drain electrode connection, the source electrode of the 20th FET and first level Connection；The grid of 21st FET is connected with the grid of the 22nd FET, and the described 21st The source electrode of FET is connected by the 4th gate-controlled switch with the second electrical level；The source of 22nd FET Pole is connected with the second electrical level；Wherein, the grid of the 21st FET and the 22nd FET The tie point of grid as the charging and discharging currents generation circuit input；The drain electrode of 19th FET with it is described The tie point of the drain electrode of 21st FET as the charging and discharging currents generation circuit output end.

22. RC oscillating circuits as claimed in claim 21, it is characterised in that the 19th FET and the described 20th FET is p-type FET, and the 21st FET and the 22nd FET are N-type field-effect Pipe.

23. RC oscillating circuits as claimed in claim 22, it is characterised in that the 3rd gate-controlled switch is a p-type field-effect Pipe, the 4th gate-controlled switch is a N-type FET.