CN117318473B

CN117318473B - Adjustable frequency-jittering oscillator

Info

Publication number: CN117318473B
Application number: CN202311594870.1A
Authority: CN
Inventors: 罗寅; 涂才根; 谭在超; 丁国华
Original assignee: Suzhou Covette Semiconductor Co ltd
Current assignee: Suzhou Covette Semiconductor Co ltd
Priority date: 2023-11-28
Filing date: 2023-11-28
Publication date: 2024-01-30
Anticipated expiration: 2043-11-28
Also published as: CN117318473A

Abstract

The invention relates to the technical field of oscillators of switching power supplies, and discloses an adjustable frequency-jittering oscillator, which comprises a first charging current generating unit, a first energy storage unit, a first discharging branch, a first comparing unit, a trigger DFF1, a signal processing unit, a trigger DFF2 and a frequency-jittering unit; in actual use, the invention controls the trigger DFF1 to generate a pulse signal on the basis of comparing the voltage of the first energy storage unit through the first comparison unit, and changes the charging current of the first energy storage unit through setting the frequency-shaking unit on the basis of controlling the trigger DFF2 to output a frequency signal through the pulse signal, thereby changing the pulse generation time of the trigger DFF1, realizing the adjustment of frequency and finally realizing the frequency-shaking control of the switching power supply.

Description

Adjustable frequency-jittering oscillator

Technical Field

The invention relates to the technical field of oscillators of switching power supplies, in particular to an adjustable jitter frequency oscillator.

Background

The switching power supply is widely applied to various electronic devices due to the characteristics of small size, light weight and high efficiency, however, the switching power supply system has the technical problems that the electromagnetic interference caused by larger voltage change rate (dv/dt) and current change rate (di/dt) and parasitic inductance and capacitance is difficult to eliminate and the like when the power tube of the switching power supply system is switched. With the development of communication and control technologies in recent years, various high frequency digital circuits have more stringent requirements on electromagnetic compatibility (EMC) of switching power supplies, so EMC design of switching power supplies is increasingly important for switching power supplies.

When testing electromagnetic interference (EMI) of a switching power supply, it was found that the switching power supply is prone to exceeding EMI limits at switching frequency moments, with larger margins at other frequency points. Therefore, to solve the electromagnetic interference problem of the switching power supply, the conventional means such as reducing leakage inductance and distributed capacitance, or adding some filtering devices can be changed into: by setting the fixed switching frequency to a frequency that is dithered within a certain range, the radiation frequency concentrated at the fixed frequency is dispersed to the set frequency band range, so as to meet the requirement of electromagnetic compatibility. The working frequency of the switching power supply is not fixed and is changed periodically, so that concentrated frequency spectrum energy is dispersed, and the EMC requirement is met.

Disclosure of Invention

In view of the shortcomings of the background art, the present invention provides an adjustable jitter frequency oscillator for providing a jitter frequency signal for a switching power supply.

In order to solve the technical problems, the invention provides the following technical scheme: an adjustable frequency-jittering oscillator comprises a first charging current generating unit, a first energy storage unit, a first discharging branch, a first comparing unit, a trigger DFF1, a signal processing unit, a trigger DFF2 and a frequency-jittering unit;

the first charging current generation unit comprises a load connection end, the load connection end is used for being connected with a load resistor, the first charging current generation unit provides first charging current for a first connection end of the first energy storage unit based on the size of the load resistor, the first connection end of the first energy storage unit is further electrically connected with the first comparison unit and the first discharging branch, and a second connection end of the first energy storage unit is grounded;

the frequency shaking unit is electrically connected with the first charging current generating unit and is used for changing the magnitude of the charging current;

the first comparison unit outputs a comparison signal based on the size of a first connection end of the first energy storage unit, the comparison signal is input to a clock end of the trigger DFF1, a Q output end of the trigger DFF1 is respectively and electrically connected with an input end of the signal processing unit and a first discharging branch circuit, the first discharging branch circuit provides a discharging path for the first energy storage unit based on the level state of the Q output end of the trigger DFF1, the signal processing unit performs even-number reverse processing on an input signal, an output end of the signal processing unit is respectively and electrically connected with an R end of the trigger DFF1 and a clock end of the trigger DFF2, a D end of the trigger DFF2 is electrically connected with a Q non-output end of the trigger DFF2, and a Q output end of the trigger DFF2 outputs a frequency signal.

In a certain embodiment, the first charging current generating unit includes an operational amplifier AMP1, an NMOS tube N1 and a first current mirror, where a positive input end of the operational amplifier AMP1 is used for inputting a first reference voltage, a negative input end of the operational amplifier AMP1 is electrically connected with a source electrode of the NMOS tube N1, a source electrode of the NMOS tube N1 is the load connection end, an output end of the operational amplifier AMP1 is electrically connected with a gate electrode of the NMOS tube N1, and the first current mirror is electrically connected with a drain electrode of the NMOS tube N1, and is used for copying a magnitude of a current flowing through a load resistor and outputting a first charging current;

the frequency jitter unit is electrically connected with the drain electrode of the NMOS transistor N1, and is configured to input current to the drain electrode of the NMOS transistor N1 or make the drain electrode of the NMOS transistor N1 flow out of current.

In an embodiment, the first discharging branch provides a discharging path for the first energy storage unit when the Q output terminal of the flip-flop DFF1 outputs a high level signal.

In a certain embodiment, the signal processing unit includes an inverter INV1 and an inverter INV2, wherein an input end of the inverter INV1 is an input end of the signal processing unit, an output end of the inverter INV1 is electrically connected with an input end of the inverter INV2, and an output end of the inverter INV2 is an output end of the signal processing unit.

In a certain embodiment, the frequency dithering unit comprises a first voltage-to-current unit, a charge-discharge unit, a second voltage-to-current unit and a logic control unit;

the first voltage-to-current unit comprises a second load connecting end, the second load connecting end is used for connecting a second load resistor, and the first voltage-to-current unit generates a reference current IA, a reference current IB and a first output current based on the size of the second load resistor;

the voltage input end of the second voltage-to-current unit is used for being connected with the second energy storage unit, and a comparison current IC, a comparison current ID and a second output current are generated based on the voltage of the second energy storage unit;

the first output current output end of the first voltage-to-current unit and the second output current output end of the second voltage-to-current unit are respectively and electrically connected with the drain electrode of the NMOS tube N1;

the logic control unit compares the reference current IA with the comparison current IC and compares the reference current IB with the comparison current ID, and inputs a charge-discharge control signal to the charge-discharge unit based on the comparison result, and the charge-discharge unit responds to the charge-discharge control signal and provides a charge path or a discharge path for the second energy storage unit based on the level state of the charge-discharge signal.

In a certain embodiment, the first voltage-to-current unit includes an operational amplifier AMP2, an NMOS transistor N3, a second current mirror, a third current mirror, and a fourth current mirror;

the positive input end of the operational amplifier AMP2 is used for inputting a second reference voltage, the output end of the operational amplifier AMP2 is electrically connected with the grid electrode of the NMOS tube N3, the negative input end of the operational amplifier AMP2 is electrically connected with the source electrode of the NMOS tube N3, the source electrode of the NMOS tube N3 is the second load connecting end, the drain electrode of the NMOS tube N3 is electrically connected with the main branch of the second current mirror, the secondary branch of the second current mirror is electrically connected with the main branch of the third current mirror, the first secondary branch and the second secondary branch of the third current mirror are used for outputting the reference current IA and the reference current IB, the third secondary branch of the third current mirror is electrically connected with the main branch of the fourth current mirror, and the secondary branch of the fourth current mirror outputs the first output current.

In an embodiment, the second voltage-to-current unit includes an operational amplifier AMP3, an NMOS transistor N12, a resistor R4, a fifth current mirror, and a sixth current mirror;

the positive input end of the operational amplifier AMP3 is used for being connected with a second energy storage unit, the negative input end of the operational amplifier AMP3 is respectively and electrically connected with a source electrode of the NMOS tube N12 and one end of the resistor R4, the other end of the resistor R4 is grounded, the output end of the operational amplifier AMP3 is electrically connected with a grid electrode of the NMOS tube N12, a drain electrode of the NMOS tube N12 is electrically connected with a main branch of the fifth current mirror, a slave branch of the fifth current mirror is electrically connected with a main branch of the sixth current mirror, a first slave branch and a second slave branch of the sixth current mirror are used for outputting a comparison current IC and a comparison current ID, and a third slave branch of the sixth current mirror outputs a second output current.

In a certain embodiment, the charge-discharge unit includes a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, an NMOS transistor N8, an NMOS transistor N9, an NMOS transistor N10, and an NMOS transistor N11;

the source electrode of the PMOS tube P7 is electrically connected with the source electrode of the PMOS tube P8 and used for being connected with a power supply, the grid electrode of the PMOS tube P7 is electrically connected with the grid electrode of the PMOS tube P8, the drain electrode of the PMOS tube P7 and the drain electrode of the NMOS tube N9 respectively, the drain electrode of the PMOS tube P8 is electrically connected with the positive input end of the operational amplifier AMP3 and the drain electrode of the NMOS tube N11 respectively, the grid electrode of the NMOS tube N11 is electrically connected with the grid electrode of the PMOS tube P9 and used for inputting charge and discharge control signals, the source electrode of the NMOS tube N11 is electrically connected with the drain electrode of the NMOS tube N10, the grid electrode of the NMOS tube N10 is electrically connected with the grid electrode of the NMOS tube N8, the grid electrode of the NMOS tube N9 and the drain electrode of the NMOS tube N8 respectively and used for being connected with the current source Ib, and the source electrode of the NMOS tube N8 and the source electrode of the NMOS tube N10 are grounded.

In an embodiment, the logic control unit includes a first comparison unit, a second comparison unit, a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3, an inverter INV3, and an inverter INV4;

the first comparing unit inputs a first comparison signal to a first input end of the NOR gate NOR1 based on the magnitudes of the reference current IB and the comparison current ID, the second comparing unit inputs a second comparison signal to an input end of the inverter INV3 based on the magnitudes of the reference current IA and the comparison current IC, an output end of the inverter INV3 is electrically connected to a second input end of the NOR gate NOR1 and a first input end of the NOR gate NOR3, a second input end of the NOR gate NOR3 is electrically connected to an output end of the NOR gate NOR2 and an input end of the inverter INV4, an output end of the NOR gate NOR3 is electrically connected to a second input end of the NOR gate NOR2, and an output end of the inverter INV4 outputs a charge/discharge control signal.

In an embodiment, the first comparing unit includes a PMOS transistor P12, a PMOS transistor P13, a PMOS transistor P14, a PMOS transistor P15, a PMOS transistor P16, an NMOS transistor N17, an NMOS transistor N18, and an NMOS transistor N19;

the source electrode of the PMOS tube P12 is respectively and electrically connected with the source electrode of the PMOS tube P13, the source electrode of the PMOS tube P14, the source electrode of the PMOS tube P15 and the source electrode of the PMOS tube P16 for accessing a power supply, the grid electrode of the PMOS tube P12 is respectively and electrically connected with the grid electrode of the PMOS tube P13 and the drain electrode of the PMOS tube P12 for accessing a reference current IB, the drain electrode of the PMOS tube P13 is respectively and electrically connected with the drain electrode of the NMOS tube N17, the grid electrode of the NMOS tube N17 and the grid electrode of the NMOS tube N18, the source electrode of the NMOS tube N17 and the source electrode of the NMOS tube N19 are grounded, the drain electrode of the NMOS tube N18 is respectively and electrically connected with the grid electrode of the NMOS tube N19 and the drain electrode of the PMOS tube P14, the grid electrode of the PMOS tube P14 is respectively and electrically connected with the grid electrode of the PMOS tube P15 and the drain electrode of the PMOS tube P16 for inputting a comparison current ID, and the drain electrode of the PMOS tube P16 is respectively and the first input end of the NOR gate 1;

the second comparison unit comprises a PMOS tube P17, a PMOS tube P18, a PMOS tube P19, a PMOS tube P20, a PMOS tube P21, an NMOS tube N20, an NMOS tube N21 and an NMOS tube N22;

the source of the PMOS tube P17 is electrically connected with the source of the PMOS tube P18, the source of the PMOS tube P19, the source of the PMOS tube P20 and the source of the PMOS tube P21 respectively for accessing a power supply, the grid of the PMOS tube P17 is electrically connected with the grid of the PMOS tube P18 and the grid of the PMOS tube P17 respectively for accessing a comparison current IC, the drain of the PMOS tube P18 is electrically connected with the drain of the NMOS tube N20, the grid of the NMOS tube N20 and the grid of the NMOS tube N21 respectively, the source of the NMOS tube N20, the source of the NMOS tube N21 and the source of the NMOS tube N22 are grounded, the drain of the NMOS tube N21 is electrically connected with the grid of the NMOS tube N22 and the drain of the PMOS tube P19 respectively, the grid of the PMOS tube P20 and the grid of the PMOS tube P21 respectively for inputting a reference current IA, and the drain of the PMOS tube P21 is electrically connected with the drain of the NMOS tube N22 and the input end of the inverter INV3 respectively.

Compared with the prior art, the invention has the following beneficial effects: according to the invention, on the basis of comparing the voltage of the first energy storage unit through the first comparison unit, the trigger DFF1 is controlled to generate a pulse signal, and on the basis of controlling the trigger DFF2 to output a frequency signal through the pulse signal, the charging current of the first energy storage unit is changed through setting the frequency-shaking unit, so that the pulse generation time of the trigger DFF1 can be changed, the frequency adjustment is realized, and finally the frequency-shaking control of the switching power supply is realized;

in addition, the magnitude of the first charging current can be set according to the magnitude of the external load resistor, so that the device can be flexibly applied;

finally, for the frequency-jittering unit, the frequency-jittering amplitude and the frequency-jittering frequency can be adjusted by setting the size of the second load resistor and the capacity value of the second energy storage unit, so that the debugging is convenient.

Drawings

FIG. 1 is a schematic diagram of the structure of the present invention in an embodiment;

FIG. 2 is a circuit diagram of one implementation of the present invention in an embodiment;

FIG. 3 is a schematic diagram of a dithering unit in an embodiment;

FIG. 4 is a circuit diagram of a first voltage-to-current unit, a second voltage-to-current unit, and a charge-discharge unit in an embodiment;

FIG. 5 is a circuit diagram of a logic control unit in an embodiment;

fig. 6 is a signal waveform diagram of a portion of an electrical node of the dither unit according to an embodiment.

Detailed Description

The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.

As shown in fig. 1, an adjustable jitter frequency oscillator includes a first charging current generating unit 1, a first energy storage unit 2, a first discharging branch 3, a first comparing unit 4, a trigger DFF1, a signal processing unit 5, a trigger DFF2, and a jitter frequency unit 6;

the first charging current generating unit 1 comprises a load connecting end, the load connecting end is used for connecting a load resistor, the first charging current generating unit 1 provides a first charging current for a first connecting end of the first energy storage unit 2 based on the size of the load resistor, the first connecting end of the first energy storage unit 2 is also electrically connected with the first comparing unit 4 and the first discharging branch 3, and a second connecting end of the first energy storage unit 2 is grounded;

the frequency dithering unit 6 is electrically connected with the first charging current generating unit 1 and is used for changing the magnitude of the charging current;

the first comparing unit 4 outputs a comparison signal based on the size of the first connection end of the first energy storage unit 2, the comparison signal is input to the clock end of the trigger DFF1, the Q output end of the trigger DFF1 is electrically connected with the input end of the signal processing unit 5 and the first discharging branch circuit respectively, the first discharging branch circuit 3 provides a discharging path for the first energy storage unit 2 based on the level state of the Q output end of the trigger DFF1, the signal processing unit 5 performs even number of reverse processing on the input signal, the output end of the signal processing unit 5 is electrically connected with the R end of the trigger DFF1 and the clock end of the trigger DFF2 respectively, the D end of the trigger DFF2 is electrically connected with the Q non-output end of the trigger DFF2 itself, and the Q output end of the trigger DFF2 outputs a frequency signal.

In actual use, the first comparing unit 4 outputs a comparison signal based on the voltage of the first energy storage unit 2, the trigger DFF1 outputs a high-low level signal based on the comparison signal output by the first comparing unit 4, the high-low level signal is processed by the signal processing unit 5 and then fed back to the R end of the trigger DFF1 to be electrically connected, so that the trigger DFF1 generates a pulse signal, the overall inversion processing time of the signal processing unit 5 is the duration of the pulse signal, the trigger DFF2 generates a frequency signal based on the pulse signal, the frequency dithering unit 6 changes the charging current provided by the first charging current generating unit 1 to the first energy storage unit 2, so that the voltage rising rate of the first energy storage unit 2 can be changed, the cycle point of the high-low level signal output by the first comparing unit 4 can be changed, the frequency of the frequency signal output by the trigger DFF2 can be changed, and finally the frequency dithering control of the switching power supply can be realized.

Specifically, referring to fig. 2, the first charging current generating unit 1 includes an operational amplifier AMP1, an NMOS transistor N1 and a first current mirror, where a positive input terminal of the operational amplifier AMP1 is used for inputting a first reference voltage, and in this embodiment, the magnitude of the first reference voltage is 3V, a negative input terminal of the operational amplifier AMP1 is electrically connected to a source of the NMOS transistor N1, the source of the NMOS transistor N1 is a load connection terminal, an output terminal of the operational amplifier AMP1 is electrically connected to a gate of the NMOS transistor N1, and the first current mirror is electrically connected to a drain of the NMOS transistor N1, and is used for copying the magnitude of a current flowing through a load resistor and outputting a first charging current;

the jitter unit 6 is electrically connected to the drain of the NMOS transistor N1, and is configured to input current to the drain of the NMOS transistor N1 or make the drain of the NMOS transistor N1 flow out of current.

In actual use, the operational amplifier AMP1 and the NMOS transistor N1 form a negative feedback structure, so as to ensure that the voltage applied to the resistor R1 is stable, and thus ensure that the current flowing through the resistor R1 is stable, and the current is replicated by the first current mirror to form the first charging current flowing to the first energy storage unit 2. The first current mirror includes a PMOS transistor P1 and a PMOS transistor P2, sources of the PMOS transistor P1 and the PMOS transistor P2 are electrically connected for accessing the power supply VDD, a gate of the PMOS transistor P1 is electrically connected with a drain of the PMOS transistor P1, a drain of the NMOS transistor N1 and a gate of the PMOS transistor P2, and a drain of the PMOS transistor P2 is electrically connected with the first energy storage unit 2, in addition, in this embodiment, the first energy storage unit 2 is a capacitor C1.

In some embodiments, to change the magnitude of the first charging current, the magnitude of the first reference voltage, the magnitude of the resistor R1, and the replica ratio of the first current mirror may be changed.

In fig. 2, the second comparing unit 4 includes a comparator CMP1, a positive input terminal of the comparator CMP1 is electrically connected to one end of the capacitor C1, and a negative input terminal of the comparator CMP1 inputs a reference voltage of 3V.

In fig. 2, the first discharging branch 3 provides a discharging path for the first energy storage unit when the Q output terminal of the flip-flop DFF1 outputs a high level signal. Specifically, the first discharging branch 3 includes an NMOS tube N2, a drain electrode of the NMOS tube N2 is electrically connected to the positive input terminal of the comparator CMP1, a gate electrode of the NMOS tube N2 is electrically connected to the Q output terminal of the trigger DFF1, and a source electrode of the NMOS tube N2 is grounded.

In fig. 2, the signal processing unit 5 includes an inverter INV1 and an inverter INV2, the input end of the inverter INV1 is the input end of the signal processing unit 5, the output end of the inverter INV1 is electrically connected with the input end of the inverter INV2, and the output end of the inverter INV2 is the output end of the signal processing unit 5.

In actual use, for the circuit shown in fig. 2, when the capacitor C1 is charged, the voltage of the capacitor C1 rises, when the voltage on the capacitor C1 reaches 3V, the comparator CMP1 outputs a high-level signal, the signal VQ at the Q output end of the flip-flop DFF1 follows the D-end signal of the flip-flop DFF1 (the D-end of the flip-flop DFF1 is connected to the power supply), the NMOS tube N2 is turned on, the capacitor C1 is discharged through the NMOS tube N2, and at the same time, the signal VQ is processed by the signal processing unit 5 to generate a high-level signal to be sent to the R end of the flip-flop DFF1, and then the signal at the Q output end of the flip-flop DFF1 and the signal at the output end of the signal processing unit 5 are reset to a low level;

for the flip-flop DFF2, since the clock terminal CP inputs a high pulse once, the output of the Q output terminal is inverted once, even if the output frequency signal CLK is inverted, so far, the first charging of the capacitor C1 is completed, and then the oscillator continuously repeats the process, to obtain the required clock signal.

Referring to fig. 3, in the present embodiment, the frequency dithering unit 6 includes a first voltage-to-current unit 60, a charge-discharge unit 63, a second voltage-to-current unit 62, and a logic control unit 61;

the first voltage-to-current unit 60 includes a second load connection terminal, where the second load connection terminal is used to connect to a second load resistor, and the first voltage-to-current unit 60 generates a reference current IA, a reference current IB, and a first output current based on the magnitude of the second load resistor;

the voltage input end of the second voltage-to-current unit 62 is connected to the second energy storage unit 64, and generates a comparison current IC, a comparison current ID and a second output current based on the voltage of the second energy storage unit 64;

the first output current output end of the first voltage-to-current unit 60 and the second output current output end of the second voltage-to-current unit 62 are respectively and electrically connected with the drain electrode of the NMOS tube N1; generating a current i_dither for changing the magnitude of the first charging current;

the logic control unit 61 compares the reference current IA and the comparison current IC and compares the reference current IB and the comparison current ID, and inputs a charge-discharge control signal to the charge-discharge unit 63 based on the comparison result, and the charge-discharge unit 63 responds to the charge-discharge control signal and provides a charge path or a discharge path for the second energy storage unit 64 based on the level state of the charge-discharge signal.

Referring to fig. 4, the first voltage-to-current unit 60 includes an operational amplifier AMP2, an NMOS transistor N3, a second current mirror 602, a third current mirror 614, and a fourth current mirror 620;

the positive input terminal of the operational amplifier AMP2 is used for inputting a second reference voltage, the second reference voltage is illustratively 3V, the output terminal of the operational amplifier AMP2 is electrically connected with the gate of the NMOS transistor N3, the negative input terminal of the operational amplifier AMP2 is electrically connected with the source of the NMOS transistor N3, the source of the NMOS transistor N3 is a second load connection terminal, in fig. 3, the second load resistor is a resistor R3, the drain of the NMOS transistor N3 is electrically connected with the main branch 600 of the second current mirror 602, the slave branch 601 of the second current mirror 602 is electrically connected with the main branch 610 of the third current mirror 614, the first slave branch 611 and the second slave branch 612 of the third current mirror 614 are used for outputting the reference current IA and the reference current IB, the third slave branch 613 of the third current mirror 614 is electrically connected with the main branch 621 of the fourth current mirror 620, and the slave branch 622 of the fourth current mirror 620 outputs the first output current.

The main branch 600 of the second current mirror 602 includes a PMOS transistor P3, the sub-branch of the second current mirror 602 includes a PMOS transistor P4, the main branch 610 of the third current mirror 614 includes an NMOS transistor N4, the first sub-branch 611 of the third current mirror 614 includes an NMOS transistor N5, the second sub-branch 612 of the third current mirror 614 includes an NMOS transistor N6, the third sub-branch 613 of the third current mirror 614 includes an NMOS transistor N7, the main branch 621 of the fourth current mirror 620 includes a PMOS transistor P5, the sub-branch 622 of the fourth current mirror 620 includes a PMOS transistor P6, and the drain of the PMOS transistor P6 outputs the first output current.

For the first voltage-to-current unit 60 in fig. 3, the operational amplifier AMP2 and the NMOS transistor N3 form a negative feedback structure for forming a reference current on the resistor R3, and the second current mirror 602, the third current mirror 614, and the fourth current mirror 620 output the reference current IA, the reference current IB, and the first output current based on the reference current.

In fig. 2, the second voltage-to-current unit 62 includes an operational amplifier AMP3, an NMOS transistor N12, a resistor R4, a fifth current mirror 630, and a sixth current mirror 640;

the positive input end of the operational amplifier AMP3 is connected to the second energy storage unit 64, wherein the second energy storage unit 64 is a capacitor C3, the negative input end of the operational amplifier AMP3 is electrically connected to the source of the NMOS tube N12 and one end of the resistor R4, the other end of the resistor R4 is grounded, the output end of the operational amplifier AMP3 is electrically connected to the gate of the NMOS tube N12, the drain of the NMOS tube N12 is electrically connected to the main branch 631 of the fifth current mirror 630, the slave branch 632 of the fifth current mirror 630 is electrically connected to the main branch 641 of the sixth current mirror 640, the first slave branch 642 and the second slave branch 643 of the sixth current mirror 640 are used for outputting the comparison current IC and the comparison current ID, and the third slave branch 644 of the sixth current mirror 640 outputs the second output current.

Wherein the primary leg 631 of the fifth current mirror 630 comprises a PMOS tube P10, the secondary leg 632 of the fifth current mirror 630 comprises a PMOS tube P11, the primary leg 641 of the sixth current mirror 640 comprises an NMOS tube N13, the first secondary leg 642 of the sixth current mirror 640 comprises an NMOS tube N14, the second secondary leg 643 of the sixth current mirror 640 comprises an NMOS tube N15, and the third secondary leg 644 of the sixth current mirror 640 comprises an NMOS tube N16.

For the second voltage-to-current unit 62 in fig. 2, the operational amplifier AMP3 and the NMOS transistor N12 form a negative feedback structure that forms a second current on the resistor R4 based on the voltage of the capacitor C3, and the fifth current mirror 630 and the sixth current mirror 640 generate the comparison current IC, and the second output current based on the second current; since the charge/discharge unit 63 charges/discharges the second energy storage unit 64, the voltage of the second energy storage unit 64 is varied, and thus the output comparison current IC, the comparison current ID, and the second output current are varied.

In fig. 3, the charge and discharge unit 63 includes a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, an NMOS transistor N8, an NMOS transistor N9, an NMOS transistor N10, and an NMOS transistor N11;

the source electrode of the PMOS tube P7 is electrically connected with the source electrode of the PMOS tube P8 and used for being connected with a power supply, the grid electrode of the PMOS tube P7 is electrically connected with the grid electrode of the PMOS tube P8, the drain electrode of the PMOS tube P7 and the drain electrode of the NMOS tube N9 respectively, the drain electrode of the PMOS tube P9 is electrically connected with the positive input end of the operational amplifier AMP3 and the drain electrode of the NMOS tube N11 respectively, the grid electrode of the NMOS tube N11 is electrically connected with the grid electrode of the PMOS tube P9 and used for inputting a charge-discharge control signal Ctrl, the source electrode of the NMOS tube N11 is electrically connected with the drain electrode of the NMOS tube N10, the grid electrode of the NMOS tube N10 is electrically connected with the grid electrode of the NMOS tube N8, the grid electrode of the NMOS tube N9 and the drain electrode of the NMOS tube N8 respectively and used for being connected with a current source Ib, and the source electrode of the NMOS tube N8 and the source electrode of the NMOS tube N10 are grounded.

In actual use, when the charge-discharge control signal Ctrl is at a low level, the PMOS transistor P9 is turned on, and at this time, the power supply VDD charges the capacitor C3 through the PMOS transistors P8 and P9, and when the charge-discharge control signal Ctrl is at a high level, the capacitor C3 discharges through the NMOS transistors N11 and N10.

Referring to fig. 5, in the present embodiment, the logic control unit 61 includes a first comparing unit 650, a second comparing unit 651, a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3, an inverter INV3, and an inverter INV4;

the first comparison unit 650 inputs a first comparison signal to a first input terminal of the NOR gate NOR1 based on magnitudes of the reference current IB and the comparison current ID, the second comparison unit 651 inputs a second comparison signal to an input terminal of the inverter INV3 based on magnitudes of the reference current IA and the comparison current IC, an output terminal of the inverter INV3 is electrically connected to a second input terminal of the NOR gate NOR1 and a first input terminal of the NOR gate NOR3, respectively, a second input terminal of the NOR gate NOR3 is electrically connected to an output terminal of the NOR gate NOR2 and an input terminal of the inverter INV4, respectively, an output terminal of the NOR gate NOR3 is electrically connected to a second input terminal of the NOR gate NOR2, a first input terminal of the NOR gate NOR2 is electrically connected to an output terminal of the NOR gate NOR1, and an output terminal of the inverter INV4 outputs a charge/discharge control signal.

More specifically, the first comparing unit 650 includes a PMOS transistor P12, a PMOS transistor P13, a PMOS transistor P14, a PMOS transistor P15, a PMOS transistor P16, an NMOS transistor N17, an NMOS transistor N18, and an NMOS transistor N19;

the source electrode of the PMOS tube P12 is respectively and electrically connected with the source electrode of the PMOS tube P13, the source electrode of the PMOS tube P14, the source electrode of the PMOS tube P15 and the source electrode of the PMOS tube P16 for accessing the power supply VDD, the grid electrode of the PMOS tube P12 is respectively and electrically connected with the grid electrode of the PMOS tube P13 and the drain electrode of the PMOS tube P12 for accessing the reference current IB, the drain electrode of the PMOS tube P13 is respectively and electrically connected with the drain electrode of the NMOS tube N17, the grid electrode of the NMOS tube N17 and the grid electrode of the NMOS tube N18, the source electrode of the NMOS tube N17 and the source electrode of the NMOS tube N19 are grounded, the drain electrode of the NMOS tube N18 is respectively and electrically connected with the grid electrode of the NMOS tube N19 and the drain electrode of the PMOS tube P14, the grid electrode of the PMOS tube P14 is respectively and electrically connected with the grid electrode of the PMOS tube P15 and the drain electrode of the PMOS tube P16 for inputting the comparison current ID, and the drain electrode of the PMOS tube P16 is respectively and the drain electrode of the NMOS tube N19 and the first input end of the NOR gate 1;

the second comparing unit 651 includes a PMOS pipe P17, a PMOS pipe P18, a PMOS pipe P19, a PMOS pipe P20, a PMOS pipe P21, an NMOS pipe N20, an NMOS pipe N21, and an NMOS pipe N22;

the source of the PMOS tube P17 is electrically connected with the source of the PMOS tube P18, the source of the PMOS tube P19, the source of the PMOS tube P20 and the source of the PMOS tube P21 respectively for accessing the power supply VDD, the grid of the PMOS tube P17 is electrically connected with the grid of the PMOS tube P18 and the grid of the PMOS tube P17 respectively for accessing the comparison current IC, the drain of the PMOS tube P18 is electrically connected with the drain of the NMOS tube N20, the grid of the NMOS tube N20 and the grid of the NMOS tube N21 respectively, the source of the NMOS tube N20, the source of the NMOS tube N21 and the source of the NMOS tube N22 are grounded, the drain of the NMOS tube N21 is electrically connected with the grid of the NMOS tube N22 and the drain of the PMOS tube P19 respectively, the grid of the PMOS tube P20 and the grid of the PMOS tube P21 respectively for inputting the reference current IA, and the drain of the PMOS tube P21 is electrically connected with the drain of the NMOS tube N22 and the input end of the inverter INV3 respectively.

For the circuit shown in fig. 5, the principle of operation is as follows:

when the capacitor C3 is in the charging process, that is, the charge-discharge control signal Ctrl is assumed to be at a low level, at this time, the comparison current ID is lower than the reference current IB, the comparison current IC is higher than the reference current IA, the drain of the NMOS transistor N19 is at a high level, the drain of the NMOS transistor N22 is at a high level, the NOR gate NOR1 outputs a low level signal, the inverter INV3 outputs a low level, and the latch formed by the NOR gate NOR2 and the NOR gate NOR3 outputs a hold state, so the charge-discharge control signal Ctrl is also kept at a low level.

When the voltage of the capacitor C3 is high until the comparison current ID is higher than the reference current IB, the drain of the NMOS transistor N19 becomes low, and at this time, the output of the inverter INV3 is still low, and the NOR gate NOR1 outputs high, so as to control the charge/discharge control signal Ctrl signal to become high, turn off the PMOS transistor P9, and turn on the NMOS transistor N11 for discharging.

In the voltage drop process of the capacitor C3, the comparison current ID is lower than the reference current IB again, the drain electrode of the NMOS transistor N19 is at a high level, the inverter INV3 outputs a low level, and the output is in a hold state, and the charge/discharge control signal Ctrl is held at a high level state for the latch formed by the NOR gate NOR2 and the NOR gate NOR 3;

when the capacitor C3 discharges until the comparison current IC is lower than the reference current IA, the drain of the NMOS transistor N22 becomes a low level state, the inverter INV3 outputs a high level, and the charge/discharge control signal Ctrl is controlled to become a low level state, and then the capacitor C3 is charged.

As shown in fig. 6, the waveform diagram of the relevant node when the jitter unit 6 of the present invention is used is obtained from fig. 6, the current i_dither outputted from the jitter unit 6 changes periodically, wherein the period of the current i_dither is determined by the size of the capacitor C3, the maximum current flowing out and the maximum current flowing in of the current i_dither are determined by the reference current IA and the reference current IB, and the sizes of the reference current IA and the reference current IB are determined by the size of the resistor R3, so that the jitter frequency amplitude can be set by setting the size of the resistor R3.

In summary, the magnitude of the jitter frequency and the frequency of the jitter frequency can be freely set by setting the magnitude of the resistor R3 and the magnitude of the capacitor C3, and different EMC schemes can be designed according to different application scenes, so that the invention is very beneficial to practical application and convenient for debugging, and the cost and the circuit volume can be saved by relatively reducing the leakage inductance distribution and the distribution capacitance or adding some filter devices and other means.

The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.

Claims

1. The adjustable frequency-jittering oscillator is characterized by comprising a first charging current generating unit, a first energy storage unit, a first discharging branch, a first comparison unit, a trigger DFF1, a signal processing unit, a trigger DFF2 and a frequency-jittering unit;

the first comparing unit outputs a comparison signal based on the voltage of a first connecting end of the first energy storage unit, the comparison signal is input to a clock end of a trigger DFF1, a D end of the trigger DFF1 is used for being connected with a power supply VDD, a Q output end of the trigger DFF1 is respectively and electrically connected with an input end of the signal processing unit and a first discharging branch circuit, the first discharging branch circuit provides a discharging path for the first energy storage unit based on the level state of the Q output end of the trigger DFF1, the signal processing unit performs even-number reverse processing on the input signal, an output end of the signal processing unit is respectively and electrically connected with an R end of the trigger DFF1 and a clock end of the trigger DFF2, the D end of the trigger DFF2 is electrically connected with a Q non-output end of the trigger DFF2, and the Q output end of the trigger DFF2 outputs a frequency signal;

the frequency shaking unit comprises a first voltage-to-current unit, a charge-discharge unit, a second voltage-to-current unit and a logic control unit;

the first output current output end of the first voltage-to-current unit and the second output current output end of the second voltage-to-current unit are respectively and electrically connected with the first charging current generation unit;

the logic control unit compares the reference current IA with the comparison current IC and compares the reference current IB with the comparison current ID, and inputs a charge-discharge control signal to the charge-discharge unit based on the comparison result, and the charge-discharge unit responds to the charge-discharge control signal and provides a charge path or a discharge path for the second energy storage unit based on the level state of the charge-discharge control signal.

2. The adjustable jitter oscillator according to claim 1, wherein the first charging current generating unit comprises an operational amplifier AMP1, an NMOS transistor N1 and a first current mirror, wherein a positive input terminal of the operational amplifier AMP1 is used for inputting a first reference voltage, a negative input terminal of the operational amplifier AMP1 is electrically connected with a source electrode of the NMOS transistor N1, a source electrode of the NMOS transistor N1 is the load connection terminal, an output terminal of the operational amplifier AMP1 is electrically connected with a gate electrode of the NMOS transistor N1, and the first current mirror is electrically connected with a drain electrode of the NMOS transistor N1 and is used for copying a magnitude of a current flowing through a load resistor and outputting a first charging current;

3. The adjustable jitter oscillator of claim 1 wherein the first discharge leg provides a discharge path for the first energy storage unit when the Q output of the flip-flop DFF1 outputs a high signal.

4. The adjustable jitter oscillator of claim 1, wherein the signal processing unit includes an inverter INV1 and an inverter INV2, the input end of the inverter INV1 is an input end of the signal processing unit, the output end of the inverter INV1 is electrically connected to the input end of the inverter INV2, and the output end of the inverter INV2 is an output end of the signal processing unit.

5. The adjustable jitter oscillator of claim 1 wherein the first voltage-to-current unit comprises an operational amplifier AMP2, an NMOS transistor N3, a second current mirror, a third current mirror, and a fourth current mirror;

6. The adjustable jitter oscillator of claim 5 wherein the second voltage to current unit comprises an operational amplifier AMP3, an NMOS transistor N12, a resistor R4, a fifth current mirror and a sixth current mirror;

7. The adjustable jitter oscillator of claim 6 wherein the charge and discharge unit comprises PMOS transistor P7, PMOS transistor P8, PMOS transistor P9, NMOS transistor N8, NMOS transistor N9, NMOS transistor N10 and NMOS transistor N11;

8. The adjustable jitter oscillator of claim 7 wherein the logic control unit comprises a first comparison unit, a second comparison unit, NOR gate NOR1, NOR gate NOR2, NOR gate NOR3, inverter INV3, and inverter INV4;

9. The adjustable jitter oscillator of claim 8 wherein the first comparison unit comprises a PMOS transistor P12, a PMOS transistor P13, a PMOS transistor P14, a PMOS transistor P15, a PMOS transistor P16, an NMOS transistor N17, an NMOS transistor N18, and an NMOS transistor N19;