CN202748694U - Real-time clock circuit - Google Patents
Real-time clock circuit Download PDFInfo
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- CN202748694U CN202748694U CN 201220284661 CN201220284661U CN202748694U CN 202748694 U CN202748694 U CN 202748694U CN 201220284661 CN201220284661 CN 201220284661 CN 201220284661 U CN201220284661 U CN 201220284661U CN 202748694 U CN202748694 U CN 202748694U
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- mos transistor
- drain terminal
- grid end
- time clock
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Abstract
The utility model discloses a real-time clock circuit which comprises a constant transconductance bias current generation circuit, a negative resistance generation circuit, an operational amplifier and a buffer. The constant transconductance bias current generation circuit generates a current irrelative to a power supply voltage and supplies to the negative resistance generation circuit, the negative resistance generation circuit generates a negative resistance to offset resistance loss in a crystal, thereby enabling the crystal to be self-excited and oscillated, the operational amplifier amplifies an oscillation signal in the negative resistance generation circuit, and the oscillation signal output by the operational amplifier is shaped by the buffer into square wave. The real-time clock circuit is high in frequency accuracy of an output signal and small in power consumption, and can be integrated inside a chip.
Description
Technical field
The utility model relates to a kind of real time clock circuit that is integrated in chip internal, particularly a kind of low-power consumption real time clock circuit.
Background technology
What Fig. 1 showed is traditional real time clock circuit.It is to produce negative resistance by a phase inverter and a resistance, thus make it with crystal in resistance offset to produce vibration, oscillator signal is undertaken exporting after the shaping by the two-stage phase inverter of back.
Yet the negative resistance value that is produced by phase inverter and resistance among Fig. 1 changes with the variation of temperature and supply voltage, affects the steady operation of circuit.In addition, because the phase inverter of back only carries out shaping to the signal of crystal one end, the oscillator signal of the crystal other end is wasted, and then has increased the power consumption of circuit.
The utility model content
In view of this, the utility model provides a kind of low-power consumption real time clock circuit, and this circuit utilizes a constant transconductance biasing circuit to produce the constant transconductance electric current and offers negative resistance generation circuit, makes the value of negative resistance keep constant, and circuit can steady operation.The utility model utilizes an operational amplifier that the oscillator signal at crystal two ends is amplified in addition, does not have energy to be wasted, and has also just reduced circuit power consumption.
The purpose of this utility model realizes by following technical proposals.
A kind of real time clock circuit that is integrated into chip internal, comprise four partial circuits, in described four partial circuits, the output terminal of constant transconductance bias current generating circuit is connected to negative resistance and produces circuit, the output terminal of negative resistance generation circuit is connected to the input end of operational amplifier, and the output terminal of operational amplifier is connected to the input end of impact damper.
As improvements over the prior art, in this real time clock circuit, described constant transconductance bias current generating circuit comprises: the first MOS transistor, the second MOS transistor, the 3rd MOS transistor, the 4th MOS transistor, the 5th MOS transistor, the 6th MOS transistor and the first resistance;
The first MOS transistor source is connected to power supply, and the grid end is connected to the grid end of the second MOS transistor, and drain terminal is connected to grid end and the drain terminal of the 3rd MOS transistor; The second MOS transistor source is connected to power supply, and the grid end links to each other with the drain terminal of self, and is connected to the drain terminal of the 4th MOS transistor; The 3rd MOS transistor source ground connection, the grid end links to each other with the drain terminal of self, and is connected to the drain terminal of the first MOS transistor; The 4th MOS transistor source is connected to an end of the first resistance, and the grid end connects the grid end of the 3rd MOS transistor, and drain terminal is connected to the drain terminal of the second MOS transistor; The 5th MOS transistor source is connected to power supply, and the grid end links to each other with the drain terminal of self, and is connected to the drain terminal of the 6th MOS transistor; The 6th MOS transistor source ground connection, the grid end connects the grid end of the 4th MOS transistor, and drain terminal is connected to the drain terminal of the 5th MOS transistor; The first resistance one end ground connection, the other end is connected to the source of the 4th MOS transistor.
As improvements over the prior art, in this real time clock circuit, described negative resistance produces circuit and comprises: the 7th MOS transistor, the 8th MOS transistor and the second resistance; The 7th MOS transistor source termination power, the grid end is connected to the grid end of the 5th MOS transistor, and drain terminal is connected to the drain terminal of the 8th MOS transistor, and its drain terminal also is connected to port x OUT simultaneously; The 8th MOS transistor source ground connection, the grid end is connected to port x IN, and drain terminal is connected to the drain terminal of the 7th MOS transistor; The second resistance one end is connected to port x IN, and is connected to the negative input end of operational amplifier; The other end is connected to port x OUT, and is connected to the positive input terminal of operational amplifier.
Further, described port x IN is connected the two ends of external transistor with port x OUT.
As improvements over the prior art, in this real time clock circuit, described operational amplifier is a differential amplifier.
As improvements over the prior art, in this real time clock circuit, described impact damper comprises the two-stage phase inverter, the output of the input concatenation operation amplifier of the first phase inverter, and the input of the second phase inverter connects the output of the first phase inverter.
The utlity model has following advantage:
The utility model real time clock circuit power consumption is little, precision is high, can be integrated in easily chip internal.
The utility model real time clock circuit can be very fast after powering on the output of stable frequency is provided.
Description of drawings
Fig. 1 is traditional real time clock circuit structural drawing;
Fig. 2 is the utility model real time clock circuit structural drawing.
Embodiment
As shown in Figure 2, this real time clock circuit, comprise four parts, constant transconductance bias current generating circuit 100, negative resistance produce circuit 200, operational amplifier 300 and impact damper 400, wherein, the output terminal of constant transconductance bias current generating circuit 100 is connected to negative resistance and produces circuit 200, and the output terminal of negative resistance generation circuit 200 is connected to the input end of operational amplifier 300, and the output terminal of operational amplifier 300 is connected to the input end of impact damper 400;
Among Fig. 2, constant transconductance bias current generating circuit 100 comprises: the first MOS transistor M1,
MOS transistor M2, the 3rd MOS transistor M3, the 4th MOS transistor M4, the 5th MOS transistor M5, the 6th MOS transistor M6 and the first resistance R 1; The first MOS transistor M1 source is connected to power vd D, and the grid end is connected to the grid end of the second MOS transistor M2, and drain terminal is connected to grid end and the drain terminal of the 3rd MOS transistor M3; The second MOS transistor M2 source is connected to power vd D, and the grid end links to each other with the drain terminal of self, and is connected to the drain terminal of the 4th MOS transistor M4; The 3rd MOS transistor M3 source ground connection, the grid end links to each other with the drain terminal of self, and is connected to the drain terminal of the first MOS transistor M1; The 4th MOS transistor M4 source is connected to an end of the first resistance R 1, and the grid end connects the grid end of the 3rd MOS transistor M3, and drain terminal is connected to the drain terminal of the second MOS transistor M2; The 5th MOS transistor M5 source is connected to power vd D, and the grid end links to each other with the drain terminal of self, and is connected to the drain terminal of the 6th MOS transistor M6; The 6th MOS transistor M6 source ground connection, the grid end connects the grid end of the 4th MOS transistor M4, and drain terminal is connected to the drain terminal of the 5th MOS transistor M5; The first resistance R 1 one end ground connection, the other end is connected to the source of the 4th MOS transistor M4;
Described negative resistance produces circuit 200 and comprises: the 7th MOS transistor M7, the 8th MOS transistor M8 and the second resistance R 2; The 7th MOS transistor M7 source meets power vd D, and the grid end is connected to the grid end of the 5th MOS transistor M5, and drain terminal is connected to the drain terminal of the 8th MOS transistor M8, and its drain terminal also is connected to port x OUT simultaneously; The 8th MOS transistor M8 source ground connection, the grid end is connected to port x IN, and drain terminal is connected to the drain terminal of the 7th MOS transistor M7; The second resistance R 2 one ends are connected to port x IN, and are connected to the negative input end of operational amplifier; The other end is connected to port x OUT, and is connected to the positive input terminal of operational amplifier.
The operational amplifier 300 of this real time clock circuit is a differential amplifier.
Described impact damper 400 comprises the two-stage phase inverter, the output terminal of the input end concatenation operation amplifier 300 of the first phase inverter, and the input end of the second phase inverter connects the output terminal of the first phase inverter.
The above only is the utility model preferred embodiment; so it is not to limit scope of the present utility model; the personnel of any book palpus the technology; within not breaking away from spirit and scope of the present utility model; can do on this basis further improvement and variation, because the scope that claims were defined that protection domain of the present utility model is worked as with the application is as the criterion.
Claims (6)
1. real time clock circuit, it is characterized in that, comprise four partial circuits, in described four partial circuits, the output terminal of constant transconductance bias current generating circuit (100) is connected to the input end that negative resistance produces circuit (200), the output terminal of negative resistance generation circuit (200) is connected to the input end of operational amplifier (300), and the output terminal of operational amplifier (300) is connected to the input end of impact damper (400).
2. a kind of real time clock circuit according to claim 1 is characterized in that, described constant transconductance bias current generating circuit (100) comprising:
The first MOS transistor (M1), its source are connected to power supply (VDD), and the grid end is connected to the grid end of MOS transistor (M2), and drain terminal connects grid end and the drain terminal of the 3rd MOS transistor (M3);
MOS transistor (M2), its source are connected to power supply (VDD), and the grid end links to each other with the drain terminal of self, and are connected to the drain terminal of the 4th MOS transistor (M4);
The 3rd MOS transistor (M3), its source ground connection, the grid end links to each other with the drain terminal of self, and is connected to the drain terminal of the first MOS transistor (M1);
The 4th MOS transistor (M4), its source are connected to an end of the first resistance (R1), and the grid end connects the grid end of the 3rd MOS transistor (M3), and drain terminal is connected to the drain terminal of MOS transistor (M2);
The 5th MOS transistor (M5), its source are connected to power supply (VDD), and the grid end links to each other with the drain terminal of self, and are connected to the drain terminal of the 6th MOS transistor (M6);
The 6th MOS transistor (M6), its source ground connection, the grid end connects the grid end of the 4th MOS transistor (M4), and drain terminal is connected to the drain terminal of the 5th MOS transistor (M5);
The first resistance (R1), one end ground connection, the other end is connected to the source of the 4th MOS transistor (M4).
3. a kind of real time clock circuit according to claim 1 is characterized in that, described negative resistance produces circuit (200) and comprising:
The 7th MOS transistor (M7), its source termination power (VDD), the grid end is connected to the grid end of MOS transistor (M5), and drain terminal is connected to the drain terminal of the 8th MOS transistor (M8), and its drain terminal also is connected to port x OUT simultaneously;
The 8th MOS transistor (M8), its source ground connection, the grid end is connected to port x IN, and drain terminal is connected to the drain terminal of the 7th MOS transistor (M7);
The second resistance (R2), the one end is connected to port x IN, and is connected to the negative input end of operational amplifier; The other end is connected to port x OUT, and is connected to the positive input terminal of operational amplifier.
4. a kind of real time clock circuit according to claim 3 is characterized in that, described port x IN is connected the two ends of external transistor with port x OUT.
5. a kind of real time clock circuit according to claim 1 is characterized in that, described operational amplifier (300) is a differential amplifier.
6. a kind of real time clock circuit according to claim 1, it is characterized in that, described impact damper (400) comprises the two-stage phase inverter, the output terminal of the input concatenation operation amplifier of the first phase inverter, and the input end of the second phase inverter connects the output terminal of the first phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220284661 CN202748694U (en) | 2012-06-15 | 2012-06-15 | Real-time clock circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220284661 CN202748694U (en) | 2012-06-15 | 2012-06-15 | Real-time clock circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202748694U true CN202748694U (en) | 2013-02-20 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220284661 Expired - Lifetime CN202748694U (en) | 2012-06-15 | 2012-06-15 | Real-time clock circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202748694U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467810A (en) * | 2014-12-05 | 2015-03-25 | 无锡中星微电子有限公司 | Digital shaping method and clock system adopting digital shaping method |
| CN109639135A (en) * | 2019-01-22 | 2019-04-16 | 上海艾为电子技术股份有限公司 | A kind of charge pump circuit |
-
2012
- 2012-06-15 CN CN 201220284661 patent/CN202748694U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467810A (en) * | 2014-12-05 | 2015-03-25 | 无锡中星微电子有限公司 | Digital shaping method and clock system adopting digital shaping method |
| CN104467810B (en) * | 2014-12-05 | 2018-07-13 | 无锡中感微电子股份有限公司 | A kind of number shaping methods and the clock system using this method |
| CN109639135A (en) * | 2019-01-22 | 2019-04-16 | 上海艾为电子技术股份有限公司 | A kind of charge pump circuit |
| CN109639135B (en) * | 2019-01-22 | 2024-03-01 | 上海艾为电子技术股份有限公司 | Charge pump circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: XI'AN AEROSPACE HUAXUN TECHNOLOGY CO., LTD. Free format text: FORMER NAME: XIAN HUAXUN MICROELECTRONIC CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 710075 hi tech Zone, Shaanxi, Xi'an province 58, No. three, Hui International three floor Patentee after: XI'AN AEROSPACE HUAXUN TECHNOLOGY CO., LTD. Address before: 710075, Xi'an hi tech Zone, Shaanxi Province three science and Technology Road 58, Hao Hui International third floor Patentee before: Xian Huaxun Microelectronic Co., Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130220 |