CN203827294U - Quart crystal oscillating circuit with wide power supply and high stability - Google Patents
Quart crystal oscillating circuit with wide power supply and high stability Download PDFInfo
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- CN203827294U CN203827294U CN201420235124.3U CN201420235124U CN203827294U CN 203827294 U CN203827294 U CN 203827294U CN 201420235124 U CN201420235124 U CN 201420235124U CN 203827294 U CN203827294 U CN 203827294U
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- nmos pass
- pmos transistor
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Abstract
The utility model discloses a quart crystal oscillating circuit with a wide power supply and high stability, relating to the integrated circuit technology field. The quart crystal oscillating circuit with the wide power supply and high stability comprises a frequency selective network, a biasing circuit one, a biasing circuit two, an amplifier circuit and an output circuit. Compared with the prior art, the utility model is a crystal oscillating circuit which possesses low power supply voltage and stable output frequency and fully guarantee the reliability of the oscillating circuit.
Description
Technical field
The utility model relates to technical field of integrated circuits, particularly can be integrated into a kind of wide power of chip internal, the quartz crystal oscillator circuit of high stability.
Background technology
Along with the high speed development of large scale integrated circuit, particularly, in fields such as global positioning system, metering, communication, time and frequency measurements, general degree, accuracy, the stability of reference frequency source are proposed to more and more higher requirement.Thereby, the design and researchp of wide power, high stability quartz crystal oscillating circuit is had very important significance.
Referring to Fig. 1, in prior art, Pierre's Si crystal-oscillator circuit conventional in integrated circuit comprises feedback amplifier circuit, frequency-selective network circuit and buffer stage.Feedback amplifier circuit: current-limiting resistance (or active pull-up, a current source) termination power vd D, the transistorized source electrode of another termination MP1, the transistorized drain electrode of MP1 connects the transistorized drain electrode of MN1, and as the output end vo ut of feedback amplifier, the transistorized source electrode of MN1 connects current-limiting resistance (or active pull-up, current source) one end, another termination VSS, the transistorized grid of MN1 is connected with the transistorized grid of MP1, and as the input Vin of feedback amplifier.Feedback resistance provides direct current biasing for feedback amplifier, the feedback resistance increasing between Vin and Vout makes amplifier in the time of Vout=Vin, produce biasing, force inverter to be operated in the range of linearity, but feedback resistance is directly too large as load power consumption, and the chip area that resistance takies is large, is unfavorable for integrated chip.Frequency-selective network circuit: one end ground connection VSS of capacitor, one end of another termination quartz crystal, one end ground connection VSS of capacitor, the other end of another termination quartz crystal.
Traditional Pierre's Si crystal-oscillator circuit is due to feedback resistance
direct current biasing is provided, makes the input (Vin) of inverter equal output (Vout), namely Vout=Vin=VDD/2, the now mutual conductance of inverter is:
（1）
（2）
（3）
（4）
In the time that supply voltage VDD is very low, inverter service area can depart from linear zone, even in linear zone, the gain of inverter is also very little, and oscillating circuit is also difficult to starting of oscillation, and but feedback resistance is directly too large as load power consumption, and the chip area that resistance takies is large, is unfavorable for integrated chip.
Traditional Pierre's Si crystal-oscillator circuit is difficult to suppress low-frequency disturbance noise, causes the unstable of output frequency.
In sum, be difficult to work under crystal oscillating circuit low-voltage of the prior art, the interference noise of circuit is very large to the stability influence of output frequency, and these all can not finely meet the requirement of present integrated circuit to wide power, high stability output frequency.
Summary of the invention
For above-mentioned the deficiencies in the prior art, the purpose of this utility model is to provide the quartz crystal oscillator circuit of a kind of wide power, high stable.It is a kind of possess low supply voltage, stable crystal oscillating circuit of output frequency, can fully ensure the reliability of oscillating circuit work.
In order to reach foregoing invention object, the technical solution of the utility model realizes as follows:
The quartz crystal oscillator circuit of wide power, high stability, its design feature is that it comprises frequency-selective network circuit, biasing circuit one, biasing circuit two, amplifier circuit and output circuit.
Frequency-selective network circuit comprises: the first capacitor, the second capacitor and first crystal oscillator.One end of the first capacitor is connected with one end of the second capacitor and ground connection VSS, the XTAL_OUT end of another termination first crystal oscillator of the first capacitor as output, the XTAL_IN end of another termination first crystal oscillator of the second capacitor the input as frequency-selective network of frequency-selective network.
Biasing circuit one comprises: the 5th PMOS transistor, the 4th PMOS transistor and the 3rd PMOS transistor.The transistorized source electrode of the 5th PMOS meets power vd D, the transistorized drain electrode of the 5th PMOS meets its grid the input Iin as biasing circuit, the transistorized grid of the 5th PMOS is also connected to the transistorized grid of the 4th PMOS, the transistorized source electrode of the 4th PMOS meets power vd D, the transistorized drain electrode of the 4th PMOS connects the drain electrode of the 4th nmos pass transistor, the transistorized grid of the 4th PMOS connects the transistorized grid of the 3rd PMOS, the transistorized source electrode of the 3rd PMOS meets power vd D, and the transistorized drain electrode of the 3rd PMOS is as the first output Iout1 of biasing circuit.
Biasing circuit two comprises: the 4th nmos pass transistor and the 3rd nmos pass transistor.The source ground VSS of the 4th nmos pass transistor, the grid of the 4th nmos pass transistor connects its drain electrode, and connects the grid of the 3rd nmos pass transistor, and the drain electrode of the 3rd nmos pass transistor is as the second output Iout2 of biasing circuit.
Amplifier circuit comprises: the second nmos pass transistor, the first nmos pass transistor, a PMOS transistor, the 2nd PMOS transistor, the 3rd capacitor and the 4th capacitor.The drain electrode of the second nmos pass transistor meets the first output Iout1 of biasing circuit, and connect the second nmos pass transistor grid, the source electrode of the second nmos pass transistor connects the drain electrode of the first nmos pass transistor, the source ground VSS of the first nmos pass transistor, the grid of the first nmos pass transistor connects the grid of the second nmos pass transistor, the grid of one termination the first nmos pass transistor of the 3rd capacitor, one end of the 3rd another termination of capacitor the 4th capacitor as the input of amplifier, the transistorized grid of another termination the one PMOS of the 4th capacitor, the transistorized source electrode of the one PMOS meets power vd D, the transistorized drain electrode of the one PMOS connects the transistorized source electrode of the 2nd PMOS, the transistorized grid of the one PMOS connects the transistorized grid of the 2nd PMOS, the transistorized drain electrode of the 2nd PMOS meets the second output Iout2 of biasing circuit, and connect the transistorized grid of the 2nd PMOS, the drain electrode of the first nmos pass transistor is connected with the transistorized drain electrode of a PMOS, and as the output XTALOUT of amplifier.The input of amplifier circuit is connected with the XTAL_IN end of first crystal oscillator, and the output CLOCK_OUT of amplifier circuit is connected with the XTAL_OUT of first crystal oscillator end.
Output circuit comprises: the first Schmidt trigger, a CMOS inverter and the 2nd CMOS inverter that connect successively.The input CLOCK_IN of the first Schmidt trigger meets the output XTALOUT of amplifier, a stable clock signal of output CLOCK_OUT output of the 2nd CMOS inverter.
In above-mentioned quartz crystal oscillator circuit, the 3rd capacitor in described amplifier circuit and the 4th capacitor adopt native capacitor; Described the first nmos pass transistor, the second nmos pass transistor, a PMOS transistor and the 2nd PMOS transistor adopt native transistor.
The utility model, owing to having adopted above-mentioned structure, compared with existing technical scheme, has following advantage:
1) the first nmos pass transistor in the utility model amplifier circuit and the transistorized grid voltage of a PMOS are provided by biasing circuit, there is the ability of higher voltage transitions electric current, so amplifier has larger gain than traditional Pierre's Si inverter.
2) the 3rd capacitor in the utility model amplifier circuit and the 4th capacitor have played the effect of stopping direct current and high pass filter, the 3rd capacitor and the 4th capacitor both can not be destroyed in stable DC biasing, the interference signal of low frequency can be attenuated again, can allow like this frequency of output more stable.
3) form that the second nmos pass transistor in the utility model amplifier circuit adopts diode to be connected with the 2nd PMOS transistor, make the transistorized grid voltage of the first nmos pass transistor and a PMOS improve a Vgs, can support like this to work under low power supply, namely can be under the power supply normal starting of oscillation of oscillating circuit, meets the modern demand to low power work especially.
4) in the utility model amplifier circuit, do not re-use feedback resistance, can reduce like this power consumption of oscillating circuit, can reduce again the area of circuit layout, be conducive to the integrated and cost of crystal oscillating circuit.
Below in conjunction with the drawings and specific embodiments, the utility model is described further.
Brief description of the drawings
Fig. 1 is quartz crystal oscillator circuit schematic diagram in prior art;
Fig. 2 is the quartz crystal vibration schematic diagram in the utility model embodiment.
Embodiment
Referring to Fig. 2, the utility model oscillating circuit comprises frequency-selective network circuit 101, biasing circuit one 102_1, biasing circuit two 102_2, amplifier circuit 103 and output circuit 104.
Frequency-selective network circuit 101 comprises: the first capacitor C1, the second capacitor C2 and first crystal oscillator.One end of the first capacitor C1 is connected with one end of the second capacitor C2 and ground connection VSS, the XTAL_OUT end of another termination first crystal oscillator of the first capacitor C1 as output, the XTAL_IN end of another termination first crystal oscillator of the second capacitor C2 the input as frequency-selective network of frequency-selective network.
Biasing circuit one 102_1 comprises: the 5th PMOS transistor MP5, the 4th PMOS transistor MP4 and the 3rd PMOS transistor MP3.The source electrode of the 5th PMOS transistor MP5 meets power vd D, the drain electrode of the 5th PMOS transistor MP5 meets its grid the input Iin as biasing circuit, the grid of the 5th PMOS transistor MP5 is also connected to the grid of the 4th PMOS transistor MP4, the source electrode of the 4th PMOS transistor MP4 meets power vd D, the drain electrode of the 4th PMOS transistor MP4 connects the drain electrode of the 4th nmos pass transistor MN4, the grid of the 4th PMOS transistor MP4 connects the grid of the 3rd PMOS transistor MP3, the source electrode of the 3rd PMOS transistor MP3 meets power vd D, the drain electrode of the 3rd PMOS transistor MP3 is as the first output Iout1 of biasing circuit.
Biasing circuit two 102_2 comprise: the 4th nmos pass transistor MN4 and the 3rd nmos pass transistor MN3.The source ground VSS of the 4th nmos pass transistor MN4, the grid of the 4th nmos pass transistor MN4 connects its drain electrode, and connects the grid of the 3rd nmos pass transistor MN3, and the drain electrode of the 3rd nmos pass transistor MN3 is as the second output Iout2 of biasing circuit.
Amplifier circuit 103 comprises: the second nmos pass transistor MN2, the first nmos pass transistor MN1, a PMOS transistor MP1, the 2nd PMOS transistor MP2, the 3rd capacitor C3 and the 4th capacitor C4.The drain electrode of the second nmos pass transistor MN2 meets the first output Iout1 of biasing circuit, and connect the second nmos pass transistor MN2 grid, the source electrode of the second nmos pass transistor MN2 connects the drain electrode of the first nmos pass transistor MN1, the source ground VSS of the first nmos pass transistor MN1, the grid of the first nmos pass transistor MN1 connects the grid of the second nmos pass transistor MN2, the grid of a termination first nmos pass transistor MN1 of the 3rd capacitor C3, one end of the 3rd another termination of capacitor C3 the 4th capacitor C4 as the input of amplifier, the grid of another termination the one PMOS transistor MP1 of the 4th capacitor C4, the source electrode of the one PMOS transistor MP1 meets power vd D, the drain electrode of the one PMOS transistor MP1 connects the source electrode of the 2nd PMOS transistor MP2, the grid of the one PMOS transistor MP1 connects the grid of the 2nd PMOS transistor MP2, the drain electrode of the 2nd PMOS transistor MP2 meets the second output Iout2 of biasing circuit, and connect the grid of the 2nd PMOS transistor MP2, the drain electrode of the first nmos pass transistor MN1 is connected with the drain electrode of a PMOS transistor MP1, and as the output XTALOUT of amplifier.The input of amplifier circuit 103 is connected with the XTAL_IN end of first crystal oscillator, and the output CLOCK_OUT of amplifier circuit 103 is connected with the XTAL_OUT of first crystal oscillator end.
Output circuit 104 comprises: the first Schmidt trigger S1, a CMOS inverter 2 and the 2nd CMOS inverter 3 that connect successively.The input CLOCK_IN of the first Schmidt trigger S1 meets the output XTALOUT of amplifier, a stable clock signal of output CLOCK_OUT output of the 2nd CMOS inverter 3.
The 3rd capacitor C3 in amplifier circuit 103 and the 4th capacitor C4 adopt native capacitor.The first nmos pass transistor MN1, the second nmos pass transistor MN2, a PMOS transistor MP1 and the 2nd PMOS transistor MP2 adopt native transistor.
Referring to Fig. 2, the course of work of the utility model crystal oscillating circuit is:
In the time selecting the quartz crystal of different characteristic frequency, the utility model circuit just can produce corresponding frequency of oscillation, and the first capacitor C1, the second capacitor C2 form frequency-selective network circuit 101 described above together with quartz crystal, and the phase shift of 180 ° is provided.
Biasing circuit one 102_1 in the utility model and biasing circuit two 102_2, for the amplifier circuit 103 in the utility model provides direct current biasing, require consideration from circuit low-power consumption and frequency of oscillation amplitude, and input current Iin can not be too large.In order to ensure that the first nmos pass transistor MN1 and a PMOS transistor MP1 in amplifier circuit described above 103 are operated in saturation region:
（5）
（6）
（7）
Obtained by formula (6), (7):
（8）
In like manner can obtain:
(9)
In order to ensure the maximum amplitude of oscillation of output frequency, we can make
with
value can amplifier circuit the first nmos pass transistor MN1 be set and a PMOS transistor MP1 breadth length ratio arranges with crossing.So can obtain the mutual conductance of amplifier the first nmos pass transistor MN1:
(10)
Can be drawn by formula (8), (10):
（11）
In like manner can obtain the mutual conductance of amplifier the one PMOS transistor MP1:
（12）
Known by formula (10), (11): the mutual conductance of above-mentioned amplifier
, and can find out compared with formula (4)
so, in the case of same breadth length ratio amplifier gain meeting of the present utility model more much larger than the gain of traditional inverter, and no longer need feedback resistance to do direct current biasing, so not only can reduce the power consumption of circuit but also chip area that can small electric road.
Meanwhile, from formula (8) and (9), the bias voltage of amplifier circuit the first nmos pass transistor MN1 described above is higher than traditional inverter bias voltage
force down than traditional inverter biased electrical with the bias voltage of a PMOS transistor MP1
, amplifier described in the utility model is like this more suitable for low supply voltage work.
The 3rd capacitor C3 in the utility model amplifier circuit 103 and the 4th capacitor C4, both can cut off direct current, to avoid direct current biasing destroyed, can play again the effect of high pass filter, can filter well like this low-frequency noise, reduce the impact of noise on oscillator frequency, thereby greatly improved the stability of oscillating circuit clock signal.
For the selectable output signal shaping circuit of first crystal oscillator in the utility model, the signal of XTAL_IN end and XTAL_OUT end is off-gauge sinusoidal signal.Therefore, designed output buffer at first crystal oscillator output end, oscillator output signal has been amplified to shaping.
From above-mentioned, the utility model embodiment is by biasing circuit one 102_1, biasing circuit two 102_2 and amplifier circuit 103, can effectively play gain control and amplitude control to crystal oscillator, thus the amplitude of the oscillation output signal can control balance time and the power consumption size of circuit.And crystal oscillating circuit of the present utility model can also work under lower power supply, there is wider range of application.The utility model embodiment passes through the 3rd capacitor C3 and the introducing of the 4th capacitor C4 and the characteristic of amplifier itself, the high order harmonic component of elimination output signal better, the output noise of reduction circuit.
It should be noted that, above-mentioned execution mode only illustrates basic ideas of the present utility model in a schematic way, and built-up circuit number, shape, device arrangement mode, connected mode with built-up circuit relevant in the utility model but not while implementing according to reality are drawn.When its actual enforcement, kenel, quantity, connected mode, device arrangement mode, the device parameters of each circuit can be random change.
Above-described embodiment is only the utility model preferred embodiment, can not limit the extension of technical solutions of the utility model.Amendment, equivalent variations and the apparent change etc. of any known technology that all genus those skilled in the art do on technical solutions of the utility model basis, within all should belonging to protection range of the present utility model.
Claims (2)
1. the quartz crystal oscillator circuit of wide power, high stability, is characterized in that, it comprises frequency-selective network circuit (101), biasing circuit one (102_1), biasing circuit two (102_2), amplifier circuit (103) and output circuit (104);
Frequency-selective network circuit (101) comprising: the first capacitor (C1), the second capacitor (C2) and first crystal oscillator, one end of the first capacitor (C1) is connected with one end of the second capacitor (C2) and ground connection VSS, the XTAL_OUT end of another termination first crystal oscillator of the first capacitor (C1) as the output of frequency-selective network, the XTAL_IN end of another termination first crystal oscillator of the second capacitor (C2) the input as frequency-selective network;
Biasing circuit one (102_1) comprising: the 5th PMOS transistor (MP5), the 4th PMOS transistor (MP4) and the 3rd PMOS transistor (MP3), the source electrode of the 5th PMOS transistor (MP5) meets power vd D, the drain electrode of the 5th PMOS transistor (MP5) meets its grid the input Iin as biasing circuit, the grid of the 5th PMOS transistor (MP5) is also connected to the grid of the 4th PMOS transistor (MP4), the source electrode of the 4th PMOS transistor (MP4) meets power vd D, the drain electrode of the 4th PMOS transistor (MP4) connects the drain electrode of the 4th nmos pass transistor (MN4), the grid of the 4th PMOS transistor (MP4) connects the grid of the 3rd PMOS transistor (MP3), the source electrode of the 3rd PMOS transistor (MP3) meets power vd D, the drain electrode of the 3rd PMOS transistor (MP3) is as the first output Iout1 of biasing circuit,
Biasing circuit two (102_2) comprising: the 4th nmos pass transistor (MN4) and the 3rd nmos pass transistor (MN3); The source ground VSS of the 4th nmos pass transistor (MN4), the grid of the 4th nmos pass transistor (MN4) connects its drain electrode, and connecing the grid of the 3rd nmos pass transistor (MN3), the drain electrode of the 3rd nmos pass transistor (MN3) is as the second output Iout2 of biasing circuit;
Amplifier circuit (103) comprising: the second nmos pass transistor (MN2), the first nmos pass transistor (MN1), a PMOS transistor (MP1), the 2nd PMOS transistor (MP2), the 3rd capacitor (C3) and the 4th capacitor (C4), the drain electrode of the second nmos pass transistor (MN2) meets the first output Iout1 of biasing circuit, and connect the second nmos pass transistor (MN2) grid, the source electrode of the second nmos pass transistor (MN2) connects the drain electrode of the first nmos pass transistor (MN1), the source ground VSS of the first nmos pass transistor (MN1), the grid of the first nmos pass transistor (MN1) connects the grid of the second nmos pass transistor (MN2), the grid of one termination the first nmos pass transistor (MN1) of the 3rd capacitor (C3), one end of the 3rd another termination of capacitor (C3) the 4th capacitor (C4) as the input of amplifier, the grid of another termination the one PMOS transistor (MP1) of the 4th capacitor (C4), the source electrode of the one PMOS transistor (MP1) meets power vd D, the drain electrode of the one PMOS transistor (MP1) connects the source electrode of the 2nd PMOS transistor (MP2), the grid of the one PMOS transistor (MP1) connects the grid of the 2nd PMOS transistor (MP2), the drain electrode of the 2nd PMOS transistor (MP2) meets the second output Iout2 of biasing circuit, and connect the grid of the 2nd PMOS transistor (MP2), the drain electrode of the first nmos pass transistor (MN1) is connected with the drain electrode of a PMOS transistor (MP1), and as the output XTALOUT of amplifier, the input of amplifier circuit (103) is connected with the XTAL_IN of first crystal oscillator end, and the output CLOCK_OUT of amplifier circuit (103) is connected with the XTAL_OUT of first crystal oscillator end,
Output circuit (104) comprising: the first Schmidt trigger (S1), a CMOS inverter (2) and the 2nd CMOS inverter (3) that connect successively; The input CLOCK_IN of the first Schmidt trigger (S1) meets the output XTALOUT of amplifier, a stable clock signal of output CLOCK_OUT output of the 2nd CMOS inverter (3).
2. quartz crystal oscillator circuit as claimed in claim 1, is characterized in that, the 3rd capacitor (C3) in described amplifier circuit (103) and the 4th capacitor (C4) adopt native capacitor; Described the first nmos pass transistor (MN1), the second nmos pass transistor (MN2), a PMOS transistor (MP1) and the 2nd PMOS transistor (MP2) adopt native transistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420235124.3U CN203827294U (en) | 2014-05-09 | 2014-05-09 | Quart crystal oscillating circuit with wide power supply and high stability |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420235124.3U CN203827294U (en) | 2014-05-09 | 2014-05-09 | Quart crystal oscillating circuit with wide power supply and high stability |
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| CN203827294U true CN203827294U (en) | 2014-09-10 |
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| CN201420235124.3U Withdrawn - After Issue CN203827294U (en) | 2014-05-09 | 2014-05-09 | Quart crystal oscillating circuit with wide power supply and high stability |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897164A (en) * | 2014-05-09 | 2016-08-24 | 北京同方微电子有限公司 | quartz crystal oscillating circuit with wide power supply and high stability |
-
2014
- 2014-05-09 CN CN201420235124.3U patent/CN203827294U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897164A (en) * | 2014-05-09 | 2016-08-24 | 北京同方微电子有限公司 | quartz crystal oscillating circuit with wide power supply and high stability |
| CN105897164B (en) * | 2014-05-09 | 2019-01-18 | 紫光同芯微电子有限公司 | A kind of quartz crystal oscillator circuit of wide power, high stability |
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Address after: 100083 Beijing City, Haidian District Wudaokou Wangzhuang Road No. 1 Tongfang Technology Plaza D floor 18 West Patentee after: Beijing Tongfang Microelectronics Company Address before: 100083 Haidian District Tsinghua Tongfang Technology Plaza, block A, floor 29, Beijing Patentee before: Beijing Tongfang Microelectronics Company |
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Address after: 100083 18 floor, West Tower, block D, Tongfang science and Technology Plaza, 1 Wang Zhuang Road, Wudaokou, Haidian District, Beijing. Patentee after: Purple light co core Microelectronics Co., Ltd. Address before: 100083 18 floor, West Tower, block D, Tongfang science and Technology Plaza, 1 Wang Zhuang Road, Wudaokou, Haidian District, Beijing. Patentee before: Beijing Tongfang Microelectronics Company |
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Granted publication date: 20140910 Effective date of abandoning: 20190118 |