CN105897164B - A kind of quartz crystal oscillator circuit of wide power, high stability - Google Patents
A kind of quartz crystal oscillator circuit of wide power, high stability Download PDFInfo
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- CN105897164B CN105897164B CN201410193545.9A CN201410193545A CN105897164B CN 105897164 B CN105897164 B CN 105897164B CN 201410193545 A CN201410193545 A CN 201410193545A CN 105897164 B CN105897164 B CN 105897164B
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Abstract
The quartz crystal oscillator circuit of a kind of wide power, high stability, is related to technical field of integrated circuits.The present invention includes frequency-selective network circuit, biasing circuit one, biasing circuit two, amplifier circuit and output circuit.Compared with the existing technology, the present invention be it is a kind of have the stable crystal oscillating circuit of low supply voltage, output frequency, can fully ensure that oscillating circuit work reliability.
Description
Technical field
The present invention relates to technical field of integrated circuits, especially can be integrated into a kind of wide power, the high stable of chip interior
The quartz crystal oscillator circuit of property.
Background technique
With the high speed development of large scale integrated circuit, especially in global positioning system, metering, communication, time and frequency
The fields such as rate metering, propose increasingly higher demands to the general geological coodinate system of reference frequency source, accuracy, stability.Thus, to width
Power supply, the design of high stability quartz crystal oscillating circuit and research have very important significance.
Referring to Fig. 1, in the prior art, common Pierce crystal oscillator circuit includes feedback amplifier in integrated circuit
Circuit, frequency-selective network circuit and buffer stage.Feedback amplifier circuit: current-limiting resistance (or active pull-up, current source) one end
Power vd D, the drain electrode of another termination MP1 transistor are met, the source electrode of MP1 transistor connects the source electrode of MN1 transistor, and as feedback
The source electrode of output end vo ut, the MN1 transistor of amplifier connects current-limiting resistance (or active pull-up, current source) one end, another
VSS is terminated, the grid of MN1 transistor is connected with the grid of MP1 transistor, and the input terminal Vin as feedback amplifier.Instead
Feed resistance provides direct current biasing for feedback amplifier, and increased feedback resistance makes amplifier in Vout=Vin between Vin and Vout
When generate biasing, force inverters work in linear region, but feedback resistance is too big directly as load power consumption, and resistance accounts for
Chip area is big, is unfavorable for integrated chip.Frequency-selective network circuit: one end of capacitor is grounded VSS, another termination quartz
One end of crystal, one end of capacitor are grounded VSS, the other end of another termination quartz crystal.
Traditional Pierce crystal oscillator circuit is due to feedback resistanceDirect current biasing is provided, so that phase inverter is defeated
Enter end (Vin) and be equal to output end (Vout), that is, Vout=Vin=VDD/2, the mutual conductance of phase inverter at this time are as follows:
When supply voltage VDD is very low, inverters work area can departing from linear zone, even if in linear zone, phase inverter
Gain also very little, oscillating circuit are also difficult starting of oscillation, and but feedback resistance it is too big directly as load power consumption, and resistance occupies
Chip area it is big, be unfavorable for integrated chip.
Traditional Pierce crystal oscillator circuit is difficult to inhibit low frequency interfering noise, causes the unstable of output frequency.
In conclusion being difficult work under crystal oscillating circuit low-voltage in the prior art, the interference noise of circuit is to defeated
The stability influence of frequency is very big out, these cannot all meet present integrated circuit to wide power, high stability output frequency very well
The requirement of rate.
Summary of the invention
In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a kind of wide powers, the stone of high stable
English crystal oscillating circuit.It is it is a kind of have the stable crystal oscillating circuit of low supply voltage, output frequency, can fully ensure that vibration
Swing the reliability of circuit work.
In order to achieve the above object of the invention, technical solution of the present invention is realized as follows:
The quartz crystal oscillator circuit of a kind of wide power, high stability, is structurally characterized in that, it includes frequency-selective network electricity
Road, biasing circuit one, biasing circuit two, amplifier circuit and output circuit.
Frequency-selective network circuit includes: first capacitor device, the second capacitor and first crystal oscillator.The one of first capacitor device
End is connected with one end of the second capacitor and is grounded VSS, the XTAL_ of another termination first crystal oscillator of first capacitor
OUT terminal and output end as frequency-selective network, the end XTAL_IN of another termination first crystal oscillator of the second capacitor is simultaneously made
For the input terminal of frequency-selective network.
Biasing circuit one includes: the 5th PMOS transistor, the 4th PMOS transistor and third PMOS transistor.5th PMOS
The source electrode of transistor meets power vd D, and the drain electrode of the 5th PMOS transistor meets its grid and the input terminal Iin as biasing circuit,
The grid of 5th PMOS transistor is also connected to the grid of the 4th PMOS transistor, and the source electrode of the 4th PMOS transistor connects power supply
VDD, the drain electrode of the 4th PMOS transistor connect the drain electrode of the 4th NMOS transistor, and the grid of the 4th PMOS transistor meets the 3rd PMOS
The grid of transistor, the source electrode of third PMOS transistor meet power vd D, and the drain electrode of third PMOS transistor is as biasing circuit
First output end Iout1.
Biasing circuit two includes: the 4th NMOS transistor and third NMOS transistor.The source electrode of 4th NMOS transistor connects
Ground VSS, the grid of the 4th NMOS crystal connect its drain electrode, and connect the grid of third NMOS transistor, the leakage of third NMOS transistor
Second output terminal Iout2 of the pole as biasing circuit.
Amplifier circuit includes: the second NMOS transistor, the first NMOS transistor, the first PMOS transistor, the 2nd PMOS
Transistor, third capacitor and the 4th capacitor.The drain electrode of second NMOS transistor connects the first output end of biasing circuit
Iout1, and connect the second NMOS transistor grid, the source electrode of the second NMOS transistor connect the drain electrode of the first NMOS transistor, and first
The source electrode of NMOS transistor is grounded VSS, and the grid of the first NMOS transistor connects the grid of the second NMOS transistor, third capacitor
One termination the first NMOS transistor grid, third capacitor it is another termination the 4th capacitor one end and as amplifier
Input terminal, the grid of the first PMOS transistor of another termination of the 4th capacitor, the source electrode of the first PMOS transistor connect power supply
VDD, the drain electrode of the first PMOS transistor connect the source electrode of the second PMOS transistor, and the grid of the first PMOS transistor meets the 2nd PMOS
The drain electrode of the grid of transistor, the second PMOS transistor meets the second output terminal Iout2 of biasing circuit, and connects the 2nd PMOS crystal
The drain electrode of the grid of pipe, the first NMOS transistor is connected with the drain electrode of the first PMOS transistor, and the output as amplifier
Hold XTALOUT.The input terminal of amplifier circuit is connected with the end XTAL_IN of first crystal oscillator, amplifier circuit it is defeated
Outlet CLOCK_OUT is connected with the end XTAL_OUT of first crystal oscillator.
Output circuit includes: sequentially connected first Schmidt trigger, the first CMOS inverter and the 2nd CMOS reverse phase
Device.The input terminal CLOCK_IN of first Schmidt trigger meets the output end XTALOUT of amplifier, the second CMOS inverter it is defeated
Outlet CLOCK_OUT exports a stable clock signal.
In above-mentioned quartz crystal oscillator circuit, third capacitor and the 4th capacitor in the amplifier circuit are adopted
Use native capacitor；First NMOS transistor, the second NMOS transistor, the first PMOS transistor and the second PMOS transistor
Using native transistor.
The present invention has the advantage that compared with the prior art scheme due to using above-mentioned structure
1) the first NMOS transistor in amplifier circuit of the present invention and the grid voltage of the first PMOS transistor are by biasing
Circuit provides, the ability with higher voltage switching current, so amplifier has more greatly than traditional Pierre's Si phase inverter
Gain.
2) the third capacitor in amplifier circuit of the present invention and the 4th capacitor play stopping direct current and high-pass filter
Effect, third capacitor and the 4th capacitor can not only be biased with stable DC and be not destroyed, but also the interference of low frequency can be believed
It number attenuates, the frequency of output can be allowed more stable in this way.
3) the second NMOS transistor in amplifier circuit of the present invention and the second PMOS transistor are using diode connection
Form can support low electricity so that the first NMOS transistor and the grid voltage of the first PMOS transistor improve a Vgs in this way
Work under source, that is, oscillating circuit can the normal starting of oscillation under power supply, especially meet the modern demand to low power work.
4) feedback resistance is not used in amplifier circuit of the present invention, can reduce the power consumption of oscillating circuit in this way, and can
To reduce the area of circuit layout, the integrated and cost for being conducive to crystal oscillating circuit is reduced.
The present invention will be further described with reference to the accompanying drawings and detailed description.
Detailed description of the invention
Fig. 1 is quartz crystal oscillator circuit schematic diagram in the prior art；
Fig. 2 is that the quartz crystal in the embodiment of the present invention vibrates schematic diagram.
Specific embodiment
Referring to Fig. 2, oscillating circuit of the present invention includes frequency-selective network circuit 101, one 102_1 of biasing circuit, biasing circuit two
102_2, amplifier circuit 103 and output circuit 104.
Frequency-selective network circuit 101 includes: first capacitor device C1, the second capacitor C2 and first crystal oscillator.First electricity
One end of container C1 is connected with one end of the second capacitor C2 and is grounded VSS, another termination first crystal of first capacitor C1
The end XTAL_OUT of oscillator and output end as frequency-selective network, another termination first crystal oscillator of the second capacitor C2
The end XTAL_IN and input terminal as frequency-selective network.
One 102_1 of biasing circuit includes: the 5th PMOS transistor MP5, the 4th PMOS transistor MP4 and the 3rd PMOS crystal
Pipe MP3.The source electrode of 5th PMOS transistor MP5 meets power vd D, and the drain electrode of the 5th PMOS transistor MP5 connects its grid and conduct
The grid of the input terminal Iin, the 5th PMOS transistor MP5 of biasing circuit are also connected to the grid of the 4th PMOS transistor MP4, the
The source electrode of four PMOS transistor MP4 meets power vd D, and the drain electrode of the 4th PMOS transistor MP4 connects the leakage of the 4th NMOS transistor MN4
Pole, the grid of the 4th PMOS transistor MP4 connect the grid of third PMOS transistor MP3, and the source electrode of third PMOS transistor MP3 connects
First output end Iout1 of the drain electrode of power vd D, third PMOS transistor MP3 as biasing circuit.
Two 102_2 of biasing circuit includes: the 4th NMOS transistor MN4 and third NMOS transistor MN3.4th NMOS crystal
The source electrode of pipe MN4 is grounded VSS, and the grid of the 4th NMOS crystal MN4 connects its drain electrode, and connects the grid of third NMOS transistor MN3,
Second output terminal Iout2 of the drain electrode of third NMOS transistor MN3 as biasing circuit.
Amplifier circuit 103 includes: the second NMOS transistor MN2, the first NMOS transistor MN1, the first PMOS transistor
MP1, the second PMOS transistor MP2, third capacitor C3 and the 4th capacitor C4.The drain electrode of second NMOS transistor MN2 connects partially
First output end Iout1 of circuits, and the second NMOS transistor MN2 grid is connect, the source electrode of the second NMOS transistor MN2 connects
The source electrode of the drain electrode of one NMOS transistor MN1, the first NMOS transistor MN1 is grounded VSS, the grid of the first NMOS transistor MN1
Connect the grid of the second NMOS transistor MN2, the grid of a first NMOS transistor MN1 of termination of third capacitor C3, third electricity
One end of the 4th capacitor C4 of another termination of container C3 and input terminal as amplifier, another termination of the 4th capacitor C4 the
The grid of one PMOS transistor MP1, the source electrode of the first PMOS transistor MP1 connect power vd D, the leakage of the first PMOS transistor MP1
Pole connects the source electrode of the second PMOS transistor MP2, and the grid of the first PMOS transistor MP1 connects the grid of the second PMOS transistor MP2,
The drain electrode of second PMOS transistor MP2 meets the second output terminal Iout2 of biasing circuit, and connects the grid of the second PMOS transistor MP2
The drain electrode of pole, the first NMOS transistor MN1 is connected with the drain electrode of the first PMOS transistor MP1, and the output as amplifier
Hold XTALOUT.The input terminal of amplifier circuit 103 is connected with the end XTAL_IN of first crystal oscillator, amplifier circuit
103 output end CLOCK_OUT is connected with the end XTAL_OUT of first crystal oscillator.
Output circuit 104 includes: sequentially connected first Schmidt trigger S1, the first CMOS inverter 2 and second
CMOS inverter 3.The input terminal CLOCK_IN of first Schmidt trigger S1 meets the output end XTALOUT of amplifier, and second
The output end CLOCK_OUT of CMOS inverter 3 exports a stable clock signal.
Third capacitor C3 and the 4th capacitor C4 in amplifier circuit 103 use native capacitor.First NMOS is brilliant
Body pipe MN1, the second NMOS transistor MN2, the first PMOS transistor MP1 and the second PMOS transistor MP2 use native transistor.
Referring to Fig. 2, the course of work of crystal oscillating circuit of the present invention are as follows:
When selecting the quartz crystal of different characteristic frequency, circuit of the present invention can generate corresponding frequency of oscillation, and first is electric
Container C1, the second capacitor C2 constitute frequency-selective network circuit 101 described above together with quartz crystal, and provide 180 °
Phase shift.
One 102_1 of biasing circuit and two 102_2 of biasing circuit in the present invention are that the amplifier circuit 103 in the present invention mentions
For direct current biasing, require to consider from circuit low-power consumption and frequency of oscillation amplitude, input current Iin cannot be too big.In order to guarantee
The first NMOS transistor MN1 and the first PMOS transistor MP1 in amplifier circuit 103 described above work in saturation region:
It is obtained by formula (6), (7):
It can similarly obtain:
In order to guarantee the maximum amplitude of oscillation of output frequency, we can be enabledWith's
Value same can cross setting amplifier circuit the first NMOS transistor MN1 and the first PMOS transistor MP1 breadth length ratio is configured.Institute
The mutual conductance of the first NMOS transistor of amplifier MN1 can be obtained:
It can be obtained by formula (8), (10):
The mutual conductance of the first PMOS transistor of amplifier MP1 can similarly be obtained:
By formula (10), (11): the mutual conductance of above-mentioned amplifier, and and formula
(4) comparing can be seen that, so amplifier gain of the invention in the case where same breadth length ratio can be than traditional
The gain of phase inverter is much larger, and feedback resistance is no longer needed to do direct current biasing, not only can reduce the power consumption of circuit in this way but also
It can be with the chip area on small electric road.
Meanwhile by formula (8) and (9) it is found that the biased electrical of the first NMOS transistor of amplifier circuit MN1 described above
The traditional inverter offsets voltage of pressure ratio is highWith the first PMOS transistor
The bias voltage of MP1 is lower than traditional inverter offsets voltage, this sample
The invention amplifier is more suitable for low supply voltage work.
Third capacitor C3 and the 4th capacitor C4 in amplifier circuit 103 of the present invention, can both separate direct current, to keep away
Exempt from direct current biasing to be destroyed, and high-pass filter can be played the role of, low-frequency noise can be filtered well in this way, reduces
Influence of the noise to oscillator frequency, to substantially increase the stability of oscillating circuit output clock signal.
For the selectable output signal shaping circuit of first crystal oscillator in the present invention, the end XTAL_IN and XTAL_OUT
The signal at end is off-gauge sinusoidal signal.Therefore, output buffer is devised in first crystal oscillator output end,
Shaping is amplified to oscillator output signal.
From the foregoing, it can be seen that the embodiment of the present invention passes through one 102_1 of biasing circuit, two 102_2 of biasing circuit and amplifier electricity
Road 103 can effectively act as gain control and amplitude control to crystal oscillator, so as to control oscillation when balance
The amplitude of output signal and the power consumption size of circuit.And crystal oscillating circuit of the invention can also under lower power supply work
Make, there is broader application range.The embodiment of the present invention passes through the introducing and amplification of third capacitor C3 and the 4th capacitor C4
The characteristic of device itself can preferably filter off the higher hamonic wave of output signal, reduce the output noise of circuit.
It should be noted that the above embodiment basic ideas that only the invention is illustrated in a schematic way, in the present invention
Related built-up circuit rather than built-up circuit number, shape, device arrangement mode, connection type when according to actual implementation are drawn
System.The kenel, quantity, connection type of each circuit, device arrangement mode, device parameters can be arbitrarily to change when its actual implementation
Become.
Embodiment described above is only preferred embodiments of the present invention, cannot limit prolonging for technical solution of the present invention
It stretches.All category those skilled in the art modification of made any well-known technique, equivalent variations on the basis of technical solution of the present invention
Changed etc. with obvious, be within the scope of protection of the invention within.
Claims (2)
1. the quartz crystal oscillator circuit of a kind of wide power, high stability, which is characterized in that it includes frequency-selective network circuit
(101), biasing circuit one (102_1), biasing circuit two (102_2), amplifier circuit (103) and output circuit (104)；
Frequency-selective network circuit (101) includes: first capacitor device (C1), the second capacitor (C2) and first crystal oscillator, and first
One end of capacitor (C1) is connected with one end of the second capacitor (C2) and is grounded VSS, another termination of first capacitor (C1)
The end XTAL_OUT of first crystal oscillator and output end as frequency-selective network, another termination first of the second capacitor (C2)
The end XTAL_IN of crystal oscillator and input terminal as frequency-selective network；
Biasing circuit one (102_1) includes: the 5th PMOS transistor (MP5), the 4th PMOS transistor (MP4) and the 3rd PMOS brilliant
Body pipe (MP3)；The source electrode of 5th PMOS transistor (MP5) meets power vd D, and the drain electrode of the 5th PMOS transistor (MP5) connects its grid
Pole and input terminal Iin as biasing circuit, the grid of the 5th PMOS transistor (MP5) are also connected to the 4th PMOS transistor
(MP4) grid, the source electrode of the 4th PMOS transistor (MP4) meet power vd D, and the drain electrode of the 4th PMOS transistor (MP4) connects
The grid of the drain electrode of four NMOS transistors (MN4), the 4th PMOS transistor (MP4) connects the grid of third PMOS transistor (MP3),
The source electrode of third PMOS transistor (MP3) meets power vd D, the drain electrode of third PMOS transistor (MP3) as biasing circuit the
One output end Iout1；
Biasing circuit two (102_2) includes: the 4th NMOS transistor (MN4) and third NMOS transistor (MN3)；4th NMOS is brilliant
The source electrode of body pipe (MN4) is grounded VSS, and the grid of the 4th NMOS crystal (MN4) connects its drain electrode, and connects third NMOS transistor
(MN3) grid, second output terminal Iout2 of the drain electrode of third NMOS transistor (MN3) as biasing circuit；
Amplifier circuit (103) includes: the second NMOS transistor (MN2), the first NMOS transistor (MN1), the first PMOS crystal
Manage (MP1), the second PMOS transistor (MP2), third capacitor (C3) and the 4th capacitor (C4)；Second NMOS transistor
(MN2) drain electrode meets the first output end Iout1 of biasing circuit, and connects the second NMOS transistor (MN2) grid, and the 2nd NMOS is brilliant
The source electrode of body pipe (MN2) connects the drain electrode of the first NMOS transistor (MN1), and the source electrode of the first NMOS transistor (MN1) is grounded VSS,
The grid of first NMOS transistor (MN1) connects the grid of the second NMOS transistor (MN2), a termination of third capacitor (C3) the
The grid of one NMOS transistor (MN1), third capacitor (C3) it is another termination the 4th capacitor (C4) one end and as amplification
The input terminal of device, the grid of the first PMOS transistor of another termination (MP1) of the 4th capacitor (C4), the first PMOS transistor
(MP1) source electrode meets power vd D, and the drain electrode of the first PMOS transistor (MP1) connects the source electrode of the second PMOS transistor (MP2), the
The grid of one PMOS transistor (MP1) connects the grid of the second PMOS transistor (MP2), the drain electrode of the second PMOS transistor (MP2)
The second output terminal Iout2 of biasing circuit is met, and connects the grid of the second PMOS transistor (MP2), the first NMOS transistor (MN1)
Drain electrode be connected with the drain electrode of the first PMOS transistor (MP1), and the output end XTALOUT as amplifier；Amplifier electricity
The input terminal on road (103) is connected with the end XTAL_IN of first crystal oscillator, the output end of amplifier circuit (103)
CLOCK_OUT is connected with the end XTAL_OUT of first crystal oscillator；
Output circuit (104) includes: sequentially connected first Schmidt trigger (S1), the first CMOS inverter (2) and second
CMOS inverter (3)；The input terminal CLOCK_IN of first Schmidt trigger (S1) meets the output end XTALOUT of amplifier, the
The output end CLOCK_OUT of two CMOS inverters (3) exports a stable clock signal.
2. quartz crystal oscillator circuit as described in claim 1, which is characterized in that in the amplifier circuit (103)
Three capacitors (C3) and the 4th capacitor (C4) use native capacitor；First NMOS transistor (MN1), the 2nd NMOS are brilliant
Body pipe (MN2), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) use native transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410193545.9A CN105897164B (en) | 2014-05-09 | 2014-05-09 | A kind of quartz crystal oscillator circuit of wide power, high stability |
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| CN201410193545.9A CN105897164B (en) | 2014-05-09 | 2014-05-09 | A kind of quartz crystal oscillator circuit of wide power, high stability |
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| CN105897164B true CN105897164B (en) | 2019-01-18 |
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Families Citing this family (2)
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| CN109274336B (en) * | 2017-07-18 | 2021-05-04 | 杭州晶华微电子股份有限公司 | Crystal oscillator circuit with ultralow voltage and ultralow power consumption |
| CN111585539A (en) * | 2020-04-26 | 2020-08-25 | 和芯星通（上海）科技有限公司 | Crystal oscillator circuit and control method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2511046Y (en) * | 2001-02-28 | 2002-09-11 | 矽统科技股份有限公司 | High-noise-immunity low-power device for quantz oscillator |
| CN201898477U (en) * | 2010-12-13 | 2011-07-13 | 上海集成电路研发中心有限公司 | Crystal oscillator |
| US20130141171A1 (en) * | 2009-12-31 | 2013-06-06 | Shuiwen Huang | Method to Shorten Crystal Oscillator's Startup Time |
| CN203827294U (en) * | 2014-05-09 | 2014-09-10 | 北京同方微电子有限公司 | Quart crystal oscillating circuit with wide power supply and high stability |
-
2014
- 2014-05-09 CN CN201410193545.9A patent/CN105897164B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2511046Y (en) * | 2001-02-28 | 2002-09-11 | 矽统科技股份有限公司 | High-noise-immunity low-power device for quantz oscillator |
| US20130141171A1 (en) * | 2009-12-31 | 2013-06-06 | Shuiwen Huang | Method to Shorten Crystal Oscillator's Startup Time |
| CN201898477U (en) * | 2010-12-13 | 2011-07-13 | 上海集成电路研发中心有限公司 | Crystal oscillator |
| CN203827294U (en) * | 2014-05-09 | 2014-09-10 | 北京同方微电子有限公司 | Quart crystal oscillating circuit with wide power supply and high stability |
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Effective date of registration: 20221222 Address after: 063000 Xinxing Electronic Industrial Park, Yutian County, Tangshan City, Hebei Province Patentee after: TANGSHAN GUOXIN JINGYUAN ELECTRONICS Co.,Ltd. Address before: 100083 18 floor, West Tower, block D, Tongfang science and Technology Plaza, 1 Wang Zhuang Road, Wudaokou, Haidian District, Beijing. Patentee before: ZIGUANG TONGXIN MICROELECTRONICS CO.,LTD. Patentee before: TANGSHAN GUOXIN JINGYUAN ELECTRONICS Co.,Ltd. |