CN106774575B - A kind of low pressure difference linear voltage regulator - Google Patents
A kind of low pressure difference linear voltage regulator Download PDFInfo
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- CN106774575B CN106774575B CN201611250322.7A CN201611250322A CN106774575B CN 106774575 B CN106774575 B CN 106774575B CN 201611250322 A CN201611250322 A CN 201611250322A CN 106774575 B CN106774575 B CN 106774575B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The present invention provides a kind of low pressure difference linear voltage regulator, including operational amplifier, output switching tube, first resistor module and second resistance module, further includes: first switch tube, control terminal receive default clock signal, first end is connected with power supply, and second end is connected with the power end of operational amplifier；The duty ratio of low high level is a:b, 0 < a < b in default clock signal；Second switch, control terminal receive default clock signal, and first end is connected with the output end of operational amplifier, and second end is connected with the control terminal of output switching tube；Capacitance module, one end respectively with the second end of second switch and export the control terminal of switching tube and be connected, when exporting switching tube is the first NMOS tube, other end ground connection, when exporting switching tube as the first PMOS tube, the other end is connected with power supply；Third switching tube, first end are connected with second resistance module, and control terminal receives the inversion signal of default clock signal, second end ground connection.Of the invention is low in energy consumption.
Description
Technical field
The present invention relates to field of circuit technology, more particularly to a kind of low pressure difference linear voltage regulator.
Background technique
In modern society, more and more handheld electric products are emerged in large numbers, these products mostly use battery to power.Battery
As a kind of power supply, output voltage is not fixed and invariable in service life, but is gradually reduced with the time is used.
And cell voltage is usually all higher than the normal working voltage of chip, such as some inner cell voltages of application are 3.6V, and in chip
The operating voltage of circuit is much of that as long as 2.5V.In this case, it just needs to integrate a low pressure difference linear voltage regulator in chip,
As long as guaranteeing that cell voltage is higher than 2.5V, low pressure difference linear voltage regulator exports stable 2.5V, circuit safely may be used
It is run by ground.
VCC ' is input power to the circuit of existing low pressure difference linear voltage regulator as shown in Figure 1:, and Vout ' is output voltage,
Vref ' is input reference voltage, and N1 ' is output NMOS tube.Operational amplifier AMP ' makes operational amplifier by negative-feedback
The voltage of two input terminals of AMP ' reaches unanimity, then output voltage VO UT '=VREF ' * (R1 '+R2 ')/R2 '.
Existing low pressure difference linear voltage regulator, which has the disadvantage in that, has harshness to power consumption using the handheld electric products of battery
It is required that power consumption is smaller to mean that battery can work the longer time.And Fig. 1 mesolow difference linear constant voltage regulator needs to locate always
In working condition, power consumption is very big, is unable to satisfy the power consumption demand of chip.
Summary of the invention
In view of the above problems, the embodiment of the present invention is designed to provide a kind of low pressure difference linear voltage regulator, existing to solve
The problem for having low pressure difference linear voltage regulator quiescent dissipation big.
To solve the above-mentioned problems, the embodiment of the invention discloses a kind of low pressure difference linear voltage regulators, including operation amplifier
Device, output switching tube, first resistor module and second resistance module, the low pressure difference linear voltage regulator further include: first switch
Pipe, the control terminal of the first switch tube receive default clock signal, and the first end of the first switch tube is connected with power supply, institute
The second end for stating first switch tube is connected with the power end of the operational amplifier；Low level and height in the default clock signal
The duty ratio of level is a:b, 0 < a < b；Second switch, the control terminal of the second switch receive the default clock letter
Number, the first end of the second switch is connected with the output end of the operational amplifier, the second end of the second switch
It is connected with the control terminal of the output switching tube；Capacitance module, one end of the capacitance module respectively with the second switch
Second end be connected with the control terminal of the output switching tube, when the output switching tube is the first NMOS tube, the capacitor
The other end of module is grounded, when the output switching tube is the first PMOS tube, the other end of the capacitance module and the electricity
Source is connected；Third switching tube, the first end of the third switching tube are connected with the second resistance module, the third switching tube
Control terminal receive the inversion signal of the default clock signal, the second end ground connection of the third switching tube；When described default
When clock signal is low level, the first switch tube, the second switch, the third switching tube and output switch
Pipe conducting；When the default clock signal is high level, the first switch tube, the second switch, the third are opened
It closes pipe to close, the output switching tube conducting.
Optionally, the first switch tube is the second PMOS tube.
Optionally, the second switch is third PMOS tube.
Optionally, the third switching tube is the second NMOS tube.
Optionally, the capacitance module includes at least one capacitor.
Optionally, low level and the duty ratio of high level are 1:n in the default clock signal, and n is greater than 1.
Optionally, the low pressure difference linear voltage regulator further include: clock generation circuit, the clock generation circuit respectively with
The control terminal of the first switch tube, the control terminal of the second switch are connected with the control terminal of the third switching tube, institute
Clock generation circuit is stated for generating the inversion signal of the default clock signal and the default clock signal.
Optionally, the clock generation circuit includes: the first inversed module, including 2m+1 sequentially connected first reverse phases
The input terminal of device, first inversed module is connected with output end；Wherein, m is the integer greater than 0；Frequency divider, the frequency divider
Input terminal be connected with the output end of first inversed module, the frequency divider is for output to first inversed module
Clock is divided, and exports the default clock signal；Second inversed module, including 2p+1 sequentially connected second reverse phases
The input terminal of device, second inversed module is connected with the output end of the frequency divider, and second inversed module is to described pre-
If clock signal carries out reverse phase, to export the inversion signal of the default clock signal；Wherein, p is whole more than or equal to 0
Number.
Optionally, the first resistor module is first resistor, and the second resistance module is second resistance.
The low pressure difference linear voltage regulator of the embodiment of the present invention includes following advantages: in the power end and power supply of operational amplifier
Between first switch tube is set, operational amplifier output end and export switching tube control terminal between second switch is set
And capacitance module, and third switching tube is set between second resistance module and ground, and then passes through default clock signal control
First switch tube and second switch, and the inversion signal by presetting clock signal control third switching tube, wherein default
Low level and the duty ratio of high level are a:b, 0 < a < b in clock signal, and when default clock signal is low level, first is opened
Guan Guan, second switch, third switching tube and output switching tube conducting, capacitance module store charge, low pressure difference linear voltage regulator
It is in running order；When default clock signal is high level, first switch tube, second switch, third switching tube are closed, defeated
Switching tube is connected out, and capacitance module discharges charge, and low pressure difference linear voltage regulator is in stop working state.In this way, the present invention is real
The low pressure difference linear voltage regulator of example is applied without in running order always, work is only in when default clock signal is low level
State, compared with existing low pressure difference linear voltage regulator, power consumption is extremely low.
Detailed description of the invention
Fig. 1 is the electrical block diagram of existing low pressure difference linear voltage regulator；
Fig. 2 is a kind of electrical block diagram of low pressure difference linear voltage regulator embodiment of the invention；
Fig. 3 is the electrical block diagram of another low pressure difference linear voltage regulator embodiment of the invention；
Fig. 4 is the structural schematic diagram of clock generation circuit in a kind of low pressure difference linear voltage regulator embodiment of the invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
The low pressure difference linear voltage regulator of the embodiment of the present invention may include operational amplifier 1, the 2, first electricity of output switching tube
It hinders module 3 and second resistance module 4, low pressure difference linear voltage regulator can also include: first switch tube 5, the control of first switch tube 5
End processed receives default clock signal A, and the first end of first switch tube 5 is connected with power supply, the second end and operation of first switch tube 5
The power end of amplifier 1 is connected, supply voltage VCC；Low level and the duty ratio of high level are a:b in default clock signal A,
0 < a < b；Second switch 6, the control terminal of second switch 6 receive default clock signal A, the first end of second switch 6
It is connected with the output end of operational amplifier 1, the second end of second switch 6 is connected with the control terminal of output switching tube 2；Capacitor mould
Block 7, one end of capacitance module 7 are connected with the control terminal of the second end of second switch 6 and output switching tube 2 respectively, work as output
When switching tube 2 is the first NMOS tube N1, the other end ground connection of capacitance module 7, when exporting switching tube 2 is the first PMOS tube P1,
The other end of capacitance module 7 is connected with power supply；Third switching tube 8, first end and 4 phase of second resistance module of third switching tube 8
Even, the control terminal of third switching tube 8 receives the inversion signal A_D of default clock signal A, the second end ground connection of third switching tube 8；
When default clock signal A is low level, first switch tube 5, second switch 6, third switching tube 8 and output switching tube 2 are led
Logical, low pressure difference linear voltage regulator is in normal operating conditions, and operational amplifier 1 charges to capacitance module 7；When default clock signal
When A is high level, first switch tube 5, second switch 6, third switching tube 8 are closed, and output switching tube 2 is connected, low voltage difference line
Property voltage-stablizer be in stop working state, capacitance module 7 leaks electricity to output switching tube 2.
In this way, the time that low pressure difference linear voltage regulator works normally is shorter, and the time to stop working is long, then
In default clock signal A whole cycle, low pressure difference linear voltage regulator average power consumption will be very low.Assuming that low pressure difference linearity pressure stabilizing
Average current when device works normally is I, then in default clock signal A whole cycle, low pressure difference linear voltage regulator is averaged
Electric current is I/ (b/a+1), and therefore, b/a is bigger, and in default clock signal A whole cycle, low pressure difference linear voltage regulator is averaged
Electric current is smaller, and average power consumption is lower.
For example, in one embodiment of the invention, presetting low level and the duty ratio of high level in clock signal A is 1:
N, n are greater than 1, i.e., at this point, a=1, b=n, due to the general very little of the electric leakage of capacitance module 7, it is possible to n be arranged greater than 1.If low
Average current when pressure difference linear voltage regulator works normally is I, then in default clock signal A whole cycle, low pressure difference linearity
The average current of voltage-stablizer is I/ (n+1), at this point, n is bigger, in default clock signal A whole cycle, low pressure difference linearity pressure stabilizing
The average current of device is smaller, and average power consumption is lower.
Specifically, Fig. 2 is in a kind of low pressure difference linear voltage regulator embodiment of the invention, when output switching tube 2 is first
Structural schematic diagram when NMOS tube N1, Fig. 3 are in another low pressure difference linear voltage regulator embodiment of the invention, when output switchs
Structural schematic diagram when pipe 2 is the first PMOS tube P1.In Fig. 2, the drain terminal of the first NMOS tube N1 is connected with power supply, first resistor mould
One end of block 3 is connected with the source of the first NMOS tube N1, one end of second resistance module 4 and the other end of first resistor module 3
It is connected, the other end of second resistance module 4 is connected with the first end of third switching tube 8.In Fig. 3, the source of the first PMOS tube P1
Be connected with power supply, one end of first resistor module 3 is connected with the drain terminal of the first PMOS tube P1, one end of second resistance module 4 with
The other end of first resistor module 3 is connected, and the other end of second resistance module 4 is connected with the first end of third switching tube 8.
In addition, referring to Fig. 2, the inverting input terminal of operational amplifier 1 receives reference voltage Vref, operational amplifier 1 it is same
Phase input terminal is connected with the other end of one end of second resistance module 4 and first resistor module 3.Referring to Fig. 3, operational amplifier 1
Non-inverting input terminal receive reference voltage, the inverting input terminal of operational amplifier 1 and one end of second resistance module 4 and the first electricity
The other end for hindering module 3 is connected.
Wherein, when low pressure difference linear voltage regulator is in normal operating conditions, Vout=Vref* (R1+R2)/R2, Vg=
Vout+Vt.Wherein, Vout is the output voltage of low pressure difference linear voltage regulator, and R1 is the resistance value of first resistor module 3, and R2 is
The resistance value of second resistance module 4, Vg be export switching tube 2 control terminal voltage, Vt be output switching tube 2 in control terminal with it is defeated
Voltage difference between the second end of switching tube 2 out.When low pressure difference linear voltage regulator is in stop working state, due to capacitor mould
Block 7 leaks electricity to output switching tube 2, and Vg can slowly become smaller, and Vout slowly becomes smaller with Vg.
Optionally, referring to Fig. 2 and Fig. 3, first switch tube 5 can be the second PMOS tube P2, and second switch 6 can be the
Three PMOS tube P3, third switching tube 8 can be the second NMOS tube N2.At this point, the grid end of the second PMOS tube P2 receives default clock
Signal A, the source of the second PMOS tube P2 are connected with power supply, the power end phase of the drain terminal and operational amplifier 1 of the second PMOS tube P2
Even.The grid end of third PMOS tube P3 receives default clock signal A, the source of third PMOS tube P3 and the output of operational amplifier 1
End is connected, and the drain terminal of third PMOS tube P3 is connected with the control terminal of output switching tube 2.The drain terminal of second NMOS tube N2 and the second electricity
It hinders module 4 to be connected, the grid end of the second NMOS tube N2 receives the inversion signal A_D of default clock signal A, the source of the second NMOS tube N2
End ground connection.
Optionally, capacitance module 7 may include at least one capacitor.In Fig. 2 and Fig. 3, capacitance module 7 includes a capacitor
C。
Optionally, low pressure difference linear voltage regulator can also include: clock generation circuit, and clock generation circuit is respectively with first
The control terminal of switching tube 5, the control terminal of second switch 6 are connected with the control terminal of third switching tube 8, and clock generation circuit is used for
Generate the inversion signal A_D of default clock signal A and default clock signal A.
Optionally, referring to Fig. 4, clock generation circuit may include: the first inversed module 9, including 2m+1 are sequentially connected
The first phase inverter F1, the input terminal of the first inversed module 9 is connected with output end；Wherein, m is the integer greater than 0；Frequency divider
10, the input terminal of frequency divider 10 is connected with the output end of the first inversed module 9, and frequency divider 10 is used for the first inversed module 9
Output clock is divided, and exports default clock signal A；Second inversed module 11, including 2p+1 sequentially connected second
Phase inverter F2, the input terminal of the second inversed module 11 are connected with the output end of frequency divider 10, the second inversed module 11 to it is default when
Clock signal A carries out reverse phase, to export the inversion signal A_D of default clock signal A；Wherein, p is the integer more than or equal to 0.Figure
In 4, the first inversed module 9 may include 3 sequentially connected first phase inverter F1, and the second inversed module 11 includes can be with 1
Second phase inverter F2.Wherein, the first phase inverter F1 and the second phase inverter F2 can be identical phase inverter or different phase inverters.
In Fig. 4,3 sequentially connected first phase inverter F1 form oscillator in the first inversed module 9, when node B level
When being high, node C level be it is low, node D level again can drag down node B level when being high, the clock that entire oscillator exports
Period is exactly the delay time of three the first phase inverter F1.Clock cycle, low level and the height that frequency divider 10 can according to need
The duty ratio of level divides the output clock of the first inversed module 9.
Optionally, referring to Fig. 2 and Fig. 3, first resistor module 3 can be first resistor, and second resistance module 4 can be the
The resistance value of two resistance, first resistor module 3 and second resistance module 4 can be equal or unequal.
The low pressure difference linear voltage regulator of the embodiment of the present invention includes following advantages: in the power end and power supply of operational amplifier
Between first switch tube is set, operational amplifier output end and export switching tube control terminal between second switch is set
And capacitance module, and third switching tube is set between second resistance module and ground, and then passes through default clock signal control
First switch tube and second switch, and the inversion signal by presetting clock signal control third switching tube, wherein default
Low level and the duty ratio of high level are a:b, 0 < a < b in clock signal, and when default clock signal is low level, first is opened
Guan Guan, second switch, third switching tube and output switching tube conducting, capacitance module store charge, low pressure difference linear voltage regulator
It is in running order；When default clock signal is high level, first switch tube, second switch, third switching tube are closed, defeated
Switching tube is connected out, and capacitance module discharges charge, and low pressure difference linear voltage regulator is in stop working state.In this way, the present invention is real
The low pressure difference linear voltage regulator of example is applied without in running order always, work is only in when default clock signal is low level
State, compared with existing low pressure difference linear voltage regulator, average power consumption is extremely low.
It should be noted that the function of second switch 6 can be realized by third NMOS tube in the embodiment of the present invention, this
When, the control terminal of third NMOS tube receives the inversion signal of default clock signal, the drain terminal and operational amplifier of third NMOS tube
Output end be connected, the source of third NMOS tube is connected with the control terminal for exporting switching tube.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
Although the preferred embodiment of the embodiment of the present invention has been described, once a person skilled in the art knows bases
This creative concept, then additional changes and modifications can be made to these embodiments.So the following claims are intended to be interpreted as
Including preferred embodiment and fall into all change and modification of range of embodiment of the invention.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements not only wrap
Those elements are included, but also including other elements that are not explicitly listed, or further includes for this process, method, article
Or the element that terminal device is intrinsic.In the absence of more restrictions, being wanted by what sentence "including a ..." limited
Element, it is not excluded that there is also other identical elements in process, method, article or the terminal device for including the element.
Above to a kind of low pressure difference linear voltage regulator provided by the present invention, it is described in detail, it is used herein
A specific example illustrates the principle and implementation of the invention, and the above embodiments are only used to help understand originally
The method and its core concept of invention；At the same time, for those skilled in the art, according to the thought of the present invention, specific
There will be changes in embodiment and application range, in conclusion the content of the present specification should not be construed as to of the invention
Limitation.
Claims (8)
1. a kind of low pressure difference linear voltage regulator, which is characterized in that including operational amplifier, output switching tube, first resistor module
With second resistance module, the low pressure difference linear voltage regulator further include:
First switch tube, the control terminal of the first switch tube receive default clock signal, the first end of the first switch tube
It is connected with power supply, the second end of the first switch tube is connected with the power end of the operational amplifier；The default clock letter
Low level and the duty ratio of high level are a:b, 0 < a < b in number；
Second switch, the control terminal of the second switch receive the default clock signal, and the of the second switch
One end is connected with the output end of the operational amplifier, the control of the second end of the second switch and the output switching tube
End is connected；
Wherein, the second switch is third NMOS tube, and the control terminal of the third NMOS tube receives the default clock letter
Number inversion signal, the drain terminal of the third NMOS tube is connected with the output end of the operational amplifier, the third NMOS tube
Source with it is described output switching tube control terminal be connected；
Capacitance module, one end of the capacitance module respectively with the second end of the second switch and the output switching tube
Control terminal is connected, when the output switching tube is the first NMOS tube, the other end ground connection of the capacitance module, when the output
When switching tube is the first PMOS tube, the other end of the capacitance module is connected with the power supply；
Third switching tube, the first end of the third switching tube are connected with the second resistance module, the third switching tube
Control terminal receives the inversion signal of the default clock signal, the second end ground connection of the third switching tube；
When the default clock signal is low level, the first switch tube, the second switch, the third switching tube
It is connected with the output switching tube；When the default clock signal is high level, the first switch tube, the second switch
Pipe, the third switching tube are closed, the output switching tube conducting；
Wherein, low level and the duty ratio of high level are 1:n in the default clock signal, and n is greater than 1.
2. low pressure difference linear voltage regulator according to claim 1, which is characterized in that the first switch tube is the 2nd PMOS
Pipe.
3. low pressure difference linear voltage regulator according to claim 1, which is characterized in that the second switch is the 3rd PMOS
Pipe.
4. low pressure difference linear voltage regulator according to claim 1, which is characterized in that the third switching tube is the 2nd NMOS
Pipe.
5. low pressure difference linear voltage regulator according to claim 1, which is characterized in that the capacitance module includes at least one
Capacitor.
6. low pressure difference linear voltage regulator according to claim 1, which is characterized in that further include:
Clock generation circuit, the clock generation circuit respectively with the control terminal of the first switch tube, the second switch
Control terminal be connected with the control terminal of the third switching tube, the clock generation circuit is for generating the default clock signal
With the inversion signal of the default clock signal.
7. low pressure difference linear voltage regulator according to claim 6, which is characterized in that the clock generation circuit includes:
First inversed module, including 2m+1 sequentially connected first phase inverters, the input terminal of first inversed module with it is defeated
Outlet is connected；Wherein, m is the integer greater than 0；
Frequency divider, the input terminal of the frequency divider are connected with the output end of first inversed module, the frequency divider for pair
The output clock of first inversed module is divided, and exports the default clock signal；
Second inversed module, including 2p+1 sequentially connected second phase inverters, the input terminal of second inversed module and institute
The output end for stating frequency divider is connected, and second inversed module carries out reverse phase to the default clock signal, described pre- to export
If the inversion signal of clock signal；Wherein, p is the integer more than or equal to 0.
8. low pressure difference linear voltage regulator according to claim 7, which is characterized in that the first resistor module is the first electricity
Resistance, the second resistance module are second resistance.
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| CN110362141A (en) * | 2018-04-10 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | A kind of power supply circuit and electronic equipment |
| CN109656292B (en) * | 2018-11-06 | 2020-07-31 | 源创芯动科技(宁波)有限公司 | Voltage regulator and system on chip |
| CN109871060B (en) * | 2019-02-27 | 2021-04-06 | 上海华虹宏力半导体制造有限公司 | Linear voltage regulator circuit |
| CN113741608B (en) * | 2021-08-30 | 2022-11-08 | 普冉半导体(上海)股份有限公司 | Linear voltage regulator circuit |
| US11789478B2 (en) * | 2022-02-22 | 2023-10-17 | Credo Technology Group Limited | Voltage regulator with supply noise cancellation |
| CN115469703B (en) * | 2022-10-27 | 2024-05-03 | 北京智芯微电子科技有限公司 | Linear voltage stabilizing circuit, working method and electronic equipment |
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| US5852359A (en) * | 1995-09-29 | 1998-12-22 | Stmicroelectronics, Inc. | Voltage regulator with load pole stabilization |
| TWI263124B (en) * | 2004-11-19 | 2006-10-01 | Sunplus Technology Co Ltd | Voltage regulator circuit with low quiescent current |
| TWI323073B (en) * | 2006-12-14 | 2010-04-01 | Novatek Microelectronics Corp | Power circuit and charge pumping circuit |
| CN103472882B (en) * | 2013-09-30 | 2015-04-15 | 电子科技大学 | Low dropout regulator of integrated slew rate enhancement circuit |
| CN206441031U (en) * | 2016-12-29 | 2017-08-25 | 北京兆易创新科技股份有限公司 | A kind of low pressure difference linear voltage regulator |
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|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. |