CN105553256A - Charge pump circuit and display apparatus - Google Patents
Charge pump circuit and display apparatus Download PDFInfo
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- CN105553256A CN105553256A CN201610105782.4A CN201610105782A CN105553256A CN 105553256 A CN105553256 A CN 105553256A CN 201610105782 A CN201610105782 A CN 201610105782A CN 105553256 A CN105553256 A CN 105553256A
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- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/076—Charge pumps of the Schenkel-type the clock signals being boosted to a value being higher than the input voltage value
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a charge pump circuit and a display apparatus. The charge pump circuit comprises a voltage input terminal, a voltage output terminal, a hysteretic comparison unit, a logic control unit and a boosting unit; the hysteretic comparison unit is connected with the voltage input terminal, and the logic control unit is connected with an output terminal of the hysteretic comparison unit and is used for outputting a first control signal to the boosting unit when the hysteretic comparison unit outputs a first level, and outputting a second control signal to the boosting unit when the hysteretic comparison unit outputs a second level; an output terminal of the boosting unit is connected with the voltage output terminal; and the boosting unit is used for amplifying a voltage at the position of the voltage input terminal in a first ratio under the action of the first control signal, and amplifying the voltage at the position of the voltage input terminal in a second ratio under the action of the second control signal. The invention can solve the problems that an input voltage range of an existing charge pump circuit is easy to limit in a low fixed ratio, and the existing charge pump circuit has low efficiency in a high fixed ratio.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a charge pump circuit and a display device.
Background
With the development of the integrated circuit manufacturing process in the prior art, the operating voltage of the circuit chip is continuously reduced. The driving voltage required by a device such as a Liquid Crystal Display (LCD) is usually higher than the operating voltage of the circuit chip, so that a boosting circuit is additionally provided to meet the requirement of the driving voltage.
In the existing booster circuit, a charge pump is preferred due to simple structure, easy integration and high efficiency. However, in the related art, the charge pump generating the driving voltage requires a wide input voltage range and a constant output voltage. However, in practical application, only a charge pump with fixed multiplying power can be selected, and at this time, if a low fixed multiplying power is adopted, the input voltage range is easily limited; if a high fixed multiplying power is adopted, the high efficiency under the high input voltage is difficult to ensure.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a charge pump circuit and a display device, and solves the problems that the input voltage range of the existing charge pump circuit is easily limited under low fixed multiplying power and the efficiency is low under high fixed multiplying power.
In a first aspect, the present invention provides a charge pump circuit, which includes a voltage input terminal and a voltage output terminal, and further includes a hysteresis comparing unit, a logic control unit, and a boosting unit; wherein,
the hysteresis comparison unit is connected with the voltage input end and used for converting the output first level into a second level when the voltage at the voltage input end rises to a first preset voltage and converting the output second level into the first level when the voltage at the voltage input end falls to a second preset voltage; the first preset voltage is higher than the second preset voltage;
the logic control unit is connected with the output end of the hysteresis comparison unit and is used for outputting a first control signal to the boosting unit when the hysteresis comparison unit outputs a first level and outputting a second control signal to the boosting unit when the hysteresis comparison unit outputs a second level;
the output end of the boosting unit is connected with the voltage output end; the voltage boosting unit is used for amplifying the voltage at the voltage input end by a first multiplying power under the action of the first control signal and amplifying the voltage at the voltage input end by a second multiplying power under the action of the second control signal; the first magnification is less than the second magnification.
Optionally, the boosting unit includes: the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, the ninth switch, the first capacitor, the second capacitor and the third capacitor; wherein,
the control ends of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch and the ninth switch are respectively connected with one output end of the logic control unit;
the first switch is connected between the voltage input end and a first node;
the second switch is connected between the voltage input end and a second node;
the third switch is connected between the voltage input end and a third node;
the fourth switch is connected between the voltage input end and a fourth node;
the fifth switch is connected between the second node and the third node;
the sixth switch is connected between the fourth node and a voltage common;
the seventh switch is connected between the second node and a voltage common terminal;
the eighth switch is connected between the first node and the voltage output terminal;
the ninth switch is connected between the third node and the voltage output terminal;
the first capacitor is connected between the third node and the fourth node;
the second capacitor is connected between the first node and the second node;
the third capacitor is connected between the voltage output terminal and a voltage common terminal.
Optionally, the logic control unit is further configured to output a first control signal to the voltage boosting unit when the hysteresis comparing unit outputs a first level, so as to turn on a first switch, a fifth switch, and a sixth switch and turn off the rest of the switches in the voltage boosting unit in a first time period, and turn on a second switch, a fourth switch, an eighth switch, and a ninth switch and turn off the rest of the switches in a second time period immediately after the first time period.
Optionally, the logic control unit is further configured to output a second control signal to the voltage boosting unit when the hysteresis comparing unit outputs a second level, so as to turn on the first switch, the third switch, the sixth switch, and the seventh switch and turn off the rest of the switches in the voltage boosting unit in a first time period, and turn on the second switch, the fourth switch, the eighth switch, and the ninth switch and turn off the rest of the switches in a second time period immediately after the first time period.
Optionally, the hysteresis comparing unit includes a voltage dividing module, a switching module and an operational amplifier; wherein,
the voltage division module is arranged between the voltage input end and the voltage common end and is provided with a first voltage division output end and a second voltage division output end;
the control end of the switch module is connected with the output end of the hysteresis comparison unit; the switch module is used for conducting the first voltage division output end and the second voltage division output end when the control end is at a low level;
and the positive phase input end of the operational amplifier is connected with the first voltage division output end, the negative phase input end of the operational amplifier is connected with the reference voltage, and the output end of the operational amplifier is connected with the output end of the hysteresis comparison unit.
Optionally, the voltage dividing module includes a first resistor, a second resistor, and a third resistor; wherein,
the first resistor is connected between the voltage input end and the first voltage division output end;
the second resistor is connected between the first voltage division output end and the second voltage division output end;
the third resistor is connected between the second voltage division output end and a voltage public end.
Optionally, the switch module includes a P-type transistor; the grid electrode of the transistor is connected with the control end of the switch module, and the source electrode and the drain electrode of the transistor are respectively connected with one of the first voltage division output end and the second voltage division output end.
In a second aspect, the present invention further provides a display device, including the charge pump circuit.
Optionally, the charge pump circuit is located on a flexible circuit board bound to the display panel in the display device.
Optionally, the charge pump circuit is disposed in a chip, and the chip is located on a flexible circuit board bound to the display panel in the display device.
According to the technical scheme, the circuit structure based on the hysteresis comparator unit, the logic control unit and the boosting unit can switch between the first multiplying power and the second multiplying power under two output states of the hysteresis comparator. Therefore, when the input voltage is lower, the voltage can be boosted by the second high multiplying power so as to expand the input range of the input voltage; and when the input voltage is higher, boosting can be carried out through the low second multiplying power so as to guarantee the efficiency of the charge pump circuit. Therefore, the charge pump circuit can solve the problems that the input voltage range of the existing charge pump circuit is easily limited under low fixed multiplying power and the efficiency is low under high fixed multiplying power. Further, compared with the prior art, the charge pump circuit provided by the invention has a larger input voltage range and higher efficiency, namely, better performance.
Drawings
Fig. 1 is a block diagram of a charge pump circuit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a charge pump circuit according to an embodiment of the invention;
fig. 3 is a logic diagram illustrating the hysteresis comparison unit outputting the first level and the second level conversion according to an embodiment of the present invention.
Detailed Description
The following further describes embodiments of the invention with reference to the drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
Fig. 1 is a block diagram of a charge pump circuit according to an embodiment of the present invention. Referring to fig. 1, the charge pump circuit includes a voltage input terminal VIN and a voltage OUTPUT terminal OUTPUT, and further includes a hysteresis comparing unit 1, a logic control unit 2, and a voltage boosting unit 3, where:
the hysteresis comparing unit 1 is connected to the voltage input terminal VIN, and configured to convert the output first level into a second level when the voltage at the voltage input terminal VIN rises to a first preset voltage, and convert the output second level into the first level when the voltage at the voltage input terminal VIN falls to a second preset voltage; the first predetermined voltage is higher than the second predetermined voltage;
the logic control unit 2 is connected to an output terminal of the hysteresis comparing unit 1, and configured to output a first control signal to the boosting unit 3 when the hysteresis comparing unit 1 outputs a first level, and output a second control signal to the boosting unit 3 when the hysteresis comparing unit 1 outputs a second level;
the OUTPUT end of the boosting unit 3 is connected to the voltage OUTPUT end OUTPUT; the boosting unit 3 is configured to amplify the voltage at the voltage input terminal VIN by a first magnification under the action of the first control signal, and amplify the voltage at the voltage input terminal VIN by a second magnification under the action of the second control signal; the first magnification is smaller than the second magnification.
It is to be understood that the first level and the second level in the above description refer to two preset potentials (for example, a high level and a low level commonly used in digital logic circuits) respectively representing two different logic states with respect to the logic control unit 2, and those skilled in the art can set the potentials according to the selected device and the adopted circuit structure, which is not limited by the embodiment.
The hysteresis comparison unit 1 in the charge pump circuit outputs a level corresponding to the voltage according to the voltage at the voltage input end VIN, the logic control unit 2 outputs a control signal corresponding to the level to the voltage boosting unit 3 according to the level output by the hysteresis comparison unit 1, so that the voltage boosting unit 3 amplifies the voltage at the voltage input end VIN according to the multiplying factor corresponding to the control signal, the charge pump circuit can amplify the voltage at the voltage input end VIN by switching the amplifying multiplying factor according to the range of the input voltage at the voltage input end VIN, thereby expanding the range of the input voltage, realizing that the high input voltage is amplified by adopting the low multiplying factor, the low input voltage is amplified by adopting the high multiplying factor, and the input voltage is amplified by adopting the inherent multiplying factor compared with the prior art, so that the input voltage can be lower, and meanwhile, the range of the input voltage is expanded, the efficiency of the charge pump is improved.
As an instructive example of a circuit configuration, when the circuit connection relationship and the input/output relationship are satisfied, the hysteresis comparing unit 1 may be implemented by referring to a circuit configuration of any conventional hysteresis comparator, the boosting unit 3 may be implemented by referring to a circuit configuration of any conventional boosting circuit, and the logic control unit 2 may be implemented by using a logic circuit based on a specific form of a control signal required by the boosting unit 3, which is not limited in the present invention.
As a more specific example, fig. 2 is a circuit configuration diagram of a charge pump circuit in an embodiment of the present invention, see fig. 2:
in an embodiment of the present invention, the boosting unit 3 includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, a first capacitor C1, a second capacitor C2, and a third capacitor C3; wherein,
the control terminals of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8 and the ninth switch S9 are respectively connected to an output terminal (not shown in the figure) of the logic control unit 2; it can be understood that the nine switches are all circuit structures that can be controlled to be turned on or turned off by a signal connected to the control terminal. Specifically, the circuit connection relationship inside the booster unit 3 is as follows:
the first switch S1 is connected between the voltage input terminal VIN and a first node a; the second switch S2 is connected between the voltage input terminal VIN and a second node b; the third switch S3 is connected between the voltage input terminal VIN and a third node c; the fourth switch S4 is connected between the voltage input terminal VIN and a fourth node d; the fifth switch S5 is connected between the second node b and the third node c; the sixth switch S6 is connected between the fourth node d and a voltage common terminal; the seventh switch S7 is connected between the second node b and a voltage common terminal; the eighth switch S8 is connected between the first node a and the voltage OUTPUT terminal OUTPUT; the ninth switch S9 is connected between the third node c and the voltage OUTPUT terminal OUTPUT; the first capacitor C1 is connected between the third node C and the fourth node d; the second capacitor C2 is connected between the first node a and the second node b; the third capacitor C3 is connected between the voltage OUTPUT terminal OUTPUT and a voltage common terminal.
Based on the circuit configuration of the voltage boosting unit 3, the logic control unit 2 is further configured to output a first control signal to the voltage boosting unit 3 when the hysteresis comparing unit 1 outputs the first level, so as to turn on the first switch S1, the fifth switch S5, and the sixth switch S6 and turn off the remaining switches in the voltage boosting unit 3 in a first time period, and turn on the second switch S2, the fourth switch S4, the eighth switch S8, and the ninth switch S9 and turn off the remaining switches in a second time period immediately after the first time period. Based on this, the booster unit 3 can achieve 1.5 times amplification of the voltage at the voltage input terminal.
Also based on the circuit configuration of the boosting unit 3, the logic control unit 2 is further configured to output a second control signal to the boosting unit 3 when the hysteresis comparing unit 1 outputs a second level, so as to turn on the first switch S1, the third switch S3, the sixth switch S6 and the seventh switch S7 and turn off the rest of the switches in the boosting unit 3 in a first period, and turn on the second switch S2, the fourth switch S4, the eighth switch S8 and the ninth switch S9 and turn off the rest of the switches in the boosting unit 3 in a second period immediately after the first period. Based on this, the booster unit 3 can achieve a 2-fold amplification of the voltage at the voltage input.
In the embodiment of the present invention, the hysteresis comparing unit 1 includes a voltage dividing module 11, a switching module 12 and an operational amplifier 13; wherein,
the voltage dividing module 11 is disposed between the voltage input terminal VIN and a voltage common terminal, and has a first voltage dividing output terminal e and a second voltage dividing output terminal f; the control end of the switch module 12 is connected with the output end of the hysteresis comparison unit 1; the switch module 12 is configured to turn on the first voltage division output end e and the second voltage division output end f when the control end is at a low level; the non-inverting input terminal of the operational amplifier 13 is connected to the first voltage division output terminal e, the inverting input terminal thereof is connected to the reference voltage Vref, and the output terminal g thereof is connected to the output terminal of the hysteresis comparing unit 1.
As shown in fig. 2, the voltage divider module 11 includes a first resistor R1, a second resistor R2, and a third resistor R3; wherein, the first resistor R1 is connected between the voltage input terminal VIN and the first voltage-dividing output terminal e; the second resistor R2 is connected between the first voltage-dividing output terminal e and the second voltage-dividing output terminal f; the third resistor R3 is connected between the second voltage division output terminal f and a voltage common terminal.
It can be seen that the switch module comprises a P-type transistor T1, the gate of which transistor T1 is connected to the control terminal of the switch module 11, and the source and drain are connected to one of the first voltage-dividing output terminal e and the second voltage-dividing output terminal f, respectively. Thereby, the transistor T1 can short-circuit the second resistor R2 when the level at the output terminal g is low, so that the voltage Vs at the non-inverting input terminal of the operational amplifier 13 rises; the transistor T1 may thereafter turn off the first and second divided voltage output terminals e and f when the output terminal g is high, so that the voltage Vs at the non-inverting input terminal of the operational amplifier 13 decreases.
Based on this, the hysteresis comparing unit 1 shown in fig. 2 can realize the input-output relationship as shown in fig. 3. It should be noted that the present embodiment does not need to limit the types of the transistors of the switch module 12.
In order to more clearly illustrate the structure and function of each module, the following describes the operation principle of the charge pump circuit in detail, as shown in fig. 2:
for convenience of description, it is assumed that R1 ═ R2 ═ R3, and of course, the resistance values of R1, R2, and R3 may be set arbitrarily as needed, and this embodiment does not limit this.
As shown in fig. 3, the horizontal axis represents the input voltage VIN of the voltage input terminal VIN, and the vertical axis represents the level Vg of the output terminal g of the operational amplifier 13 (i.e., Vg ═ 0 corresponds to the first level, and Vg ═ 1 corresponds to the second level). When the input voltage VIN of the voltage input terminal VIN is less than or equal to 1.5Vref, the voltage Vs < Vref at the positive phase input terminal, the output terminal g of the operational amplifier 13 is at a low level Vg equal to 0, the transistor T1 is turned on, the positive phase input terminal and the second voltage division output terminal f are turned on at this time, the resistor R2 is shorted, and Vs equal to 0.5 VIN. When the input voltage VIN at the voltage input terminal VIN continues to rise to be greater than 1.5Vref and smaller than 2Vref, the voltage Vs at the non-inverting input terminal becomes 0.5VIN < Vref, the output terminal g of the operational amplifier 13 is kept at the low level, and the transistor T1 continues to be turned on. When the input voltage VIN of the voltage input terminal VIN is greater than or equal to 2Vref, Vs is 0.5VIN, and is greater than or equal to Vref, the output voltage Vg at the output terminal g of the operational amplifier 13 is 1, the transistor T1 is turned off, and Vs is 2/3 VIN. When the input voltage VIN at the voltage input terminal VIN drops to greater than 1.5Vref and less than 2Vref, Vs is 2/3VIN > Vref, the output terminal g of the operational amplifier 13 still maintains high level, and the transistor T1 is turned off. When the input voltage VIN of the voltage input terminal VIN is less than or equal to 1.5Vref, Vs < Vref, and the output terminal g of the operational amplifier 13 becomes a low level.
The signal at the output terminal g of the operational amplifier 13 is sent to the logic control unit 2, and the logic control unit 2 determines the current level according to Vg, so as to control the switches S1-S9 to be turned on and off, and select different boosting multiples. If the capacitance values of the first capacitor C1 and the second capacitor C2 are equal, the voltage boost unit 3 can output two voltages of 1.5Vin and 2Vin (i.e. the first multiplying factor is 1.5, and the second multiplying factor is 2).
Specifically, as described above, when the input voltage VIN of the voltage input terminal VIN rises to the first preset voltage 2Vref, the level at the output terminal g of the operational amplifier 13 changes from high level to low level, and the logic control unit 2 outputs the first control signal to the voltage boosting unit 3, so that in the first time period (charging phase): the first switch S1, the fifth switch S5, and the sixth switch S6 are turned on, and the remaining second switch S2, the third switch S3, the fourth switch S4, the seventh switch S7, the eighth switch S8, and the ninth switch S9 are turned off. At this time, the upper end of the second capacitor C2 is connected to the voltage input terminal VIN, and the lower end is connected to the second node b; the first capacitor C1 is connected to the second node b at the upper end and to the voltage common at the lower end in the figure. It can be seen that the first capacitor C1 and the second capacitor C2 are connected in series in the loop "voltage input terminal VIN-second node b-voltage common terminal", so that the two capacitors can have the same capacitance value and each have the voltage of 0.5VIN from the upper end to the lower end after charging.
In a second time period (discharge phase) immediately after the first time period: the second switch S2, the fourth switch S4, the eighth switch S8, and the ninth switch S9 are turned on, and the remaining first switch S1, the third switch S3, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are turned off. At this time, the upper end of the first capacitor C1 is connected to the voltage OUTPUT terminal OUTPUT, and the lower end is connected to the voltage input terminal VIN; the second capacitor C2 is connected to the voltage OUTPUT terminal OUTPUT at the upper end and to the voltage input terminal VIN at the lower end. It can be understood that, since both capacitors are charged in the previous first time period and have a voltage of 0.5Vin between the upper end and the lower end, when the circuit connection relationship in the second time period changes, the two capacitors maintain the voltage of 0.5Vin between the upper end and the lower end under the charge holding effect, so that the OUTPUT terminal OUTPUT is higher than the voltage input terminal Vin by a voltage equal to 0.5 Vin. Thus, the output terminal voltage Vout is Vin +0.5Vin is 1.5Vin, that is, the boosting unit 3 can amplify the input voltage by 1.5 times.
As mentioned above, when the input voltage VIN of the voltage input terminal VIN drops to the second preset voltage 1.5Vref, the level at the output terminal g of the operational amplifier 13 is changed from low level to high level, and the logic control unit 2 outputs the second control signal to the voltage boost unit 3, so that in the first time period (charging phase): the first switch S1, the third switch S3, the sixth switch S6 and the seventh switch S7 are turned on, and the remaining second switch S2, the fourth switch S4, the fifth switch S5, the eighth switch S8 and the ninth switch S9 are turned off. At this time, the upper end of the first capacitor C1 is connected to the voltage input terminal VIN, and the lower end is connected to the voltage common terminal; the second capacitor C2 has an upper end connected to the voltage input terminal VIN and a lower end connected to the voltage common terminal. It can be seen that the first capacitor C1 and the second capacitor C2 in the first time period are connected in parallel between the voltage input terminal VIN and the voltage common terminal, so that both terminals have VIN after the charging is completed.
In a second time period (discharge phase) immediately following the first time period: the second switch S2, the fourth switch S4, the eighth switch S8, and the ninth switch S9 are turned on, and the remaining first switch S1, the third switch S3, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are turned off. At this time, the upper end of the first capacitor C1 is connected to the voltage OUTPUT terminal OUTPUT, and the lower end is connected to the voltage input terminal VIN; the second capacitor C2 is connected to the voltage OUTPUT terminal OUTPUT at the upper end and to the voltage input terminal VIN at the lower end. It can be understood that, since both the capacitors are charged in the previous first time period and have a voltage of + Vin between the upper end and the lower end, when the circuit connection relationship in the second time period changes, the two capacitors maintain the voltage of + Vin between the upper end and the lower end under the charge holding effect, so that the OUTPUT terminal OUTPUT is higher than the voltage input terminal Vin by a voltage equal to Vin. Thus, the output terminal voltage Vout + Vin is 2Vin, that is, the boosting unit 3 can amplify the input voltage by a factor of 2.
It is understood that the first time period and the second time period are set according to the value ranges of the first capacitor C1, the second capacitor C2, the input voltage Vin, and the allowable range of the voltage-boosting time delay, on one hand, the first capacitor C1 and the second capacitor C2 can complete the charging process, and on the other hand, the voltage-boosting process is not delayed for a long time.
It will also be appreciated that the first preset voltage and the second preset voltage may be used to determine the boundary value of the magnification transformation, and thus may be set according to the specific application requirements. In addition, the first multiplying factor and/or the second multiplying factor of other numerical values can be realized based on the specific setting of the relative magnitude of the capacitance value or based on the structure of other boosting circuits, which is not limited in the present invention.
The embodiment of the invention also provides a display device which comprises the charge pump circuit. The display device in this embodiment may be: any product or component with a display function, such as a display panel, electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
The charge pump circuit is positioned on a flexible circuit board bound with the display panel in the display device; or the charge pump circuit is arranged in a chip, and the chip is positioned on a flexible circuit board which is bound with the display panel in the display device. The present embodiment does not limit the arrangement position of the charge pump circuit.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The terms "upper", "lower", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the description of the present invention, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
Claims (10)
1. A charge pump circuit comprises a voltage input end and a voltage output end, and is characterized by further comprising a hysteresis comparison unit, a logic control unit and a boosting unit; wherein,
the hysteresis comparison unit is connected with the voltage input end and used for converting the output first level into a second level when the voltage at the voltage input end rises to a first preset voltage and converting the output second level into the first level when the voltage at the voltage input end falls to a second preset voltage; the first preset voltage is higher than the second preset voltage;
the logic control unit is connected with the output end of the hysteresis comparison unit and is used for outputting a first control signal to the boosting unit when the hysteresis comparison unit outputs a first level and outputting a second control signal to the boosting unit when the hysteresis comparison unit outputs a second level;
the output end of the boosting unit is connected with the voltage output end; the voltage boosting unit is used for amplifying the voltage at the voltage input end by a first multiplying power under the action of the first control signal and amplifying the voltage at the voltage input end by a second multiplying power under the action of the second control signal; the first magnification is less than the second magnification.
2. The charge pump circuit of claim 1, wherein the boost unit comprises: the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, the ninth switch, the first capacitor, the second capacitor and the third capacitor; wherein,
the control ends of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch and the ninth switch are respectively connected with one output end of the logic control unit;
the first switch is connected between the voltage input end and a first node;
the second switch is connected between the voltage input end and a second node;
the third switch is connected between the voltage input end and a third node;
the fourth switch is connected between the voltage input end and a fourth node;
the fifth switch is connected between the second node and the third node;
the sixth switch is connected between the fourth node and a voltage common;
the seventh switch is connected between the second node and a voltage common terminal;
the eighth switch is connected between the first node and the voltage output terminal;
the ninth switch is connected between the third node and the voltage output terminal;
the first capacitor is connected between the third node and the fourth node;
the second capacitor is connected between the first node and the second node;
the third capacitor is connected between the voltage output terminal and a voltage common terminal.
3. The charge pump circuit according to claim 2, wherein the logic control unit is further configured to output a first control signal to the voltage boosting unit when the hysteresis comparing unit outputs a first level, so as to turn on a first switch, a fifth switch, and a sixth switch and turn off the rest of the switches in the voltage boosting unit in a first time period, and turn on a second switch, a fourth switch, an eighth switch, and a ninth switch and turn off the rest of the switches in the voltage boosting unit in a second time period immediately after the first time period.
4. The charge pump circuit according to claim 2, wherein the logic control unit is further configured to output a second control signal to the voltage boosting unit when the hysteresis comparing unit outputs a second level, so as to turn on a first switch, a third switch, a sixth switch, and a seventh switch in the voltage boosting unit and turn off the remaining switches in a first period, and turn on a second switch, a fourth switch, an eighth switch, and a ninth switch in the voltage boosting unit and turn off the remaining switches in a second period immediately after the first period.
5. The charge pump circuit of claim 1, wherein the hysteresis comparison unit comprises a voltage division module, a switch module and an operational amplifier; wherein,
the voltage division module is arranged between the voltage input end and the voltage common end and is provided with a first voltage division output end and a second voltage division output end;
the control end of the switch module is connected with the output end of the hysteresis comparison unit; the switch module is used for conducting the first voltage division output end and the second voltage division output end when the control end is at a low level;
and the positive phase input end of the operational amplifier is connected with the first voltage division output end, the negative phase input end of the operational amplifier is connected with the reference voltage, and the output end of the operational amplifier is connected with the output end of the hysteresis comparison unit.
6. The charge pump circuit of claim 5, wherein the voltage divider module comprises a first resistor, a second resistor, and a third resistor; wherein,
the first resistor is connected between the voltage input end and the first voltage division output end;
the second resistor is connected between the first voltage division output end and the second voltage division output end;
the third resistor is connected between the second voltage division output end and a voltage public end.
7. The charge pump circuit of claim 5, wherein the switch module comprises a P-type transistor; the grid electrode of the transistor is connected with the control end of the switch module, and the source electrode and the drain electrode of the transistor are respectively connected with one of the first voltage division output end and the second voltage division output end.
8. A display device comprising the charge pump circuit according to any one of claims 1 to 7.
9. The display device of claim 8, wherein the charge pump circuit is located on a flexible circuit board bound to a display panel within the display device.
10. The display device according to claim 8, wherein the charge pump circuit is provided in a chip on a flexible circuit board bound to a display panel in the display device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610105782.4A CN105553256B (en) | 2016-02-25 | 2016-02-25 | Charge pump circuit and display device |
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| CN201610105782.4A CN105553256B (en) | 2016-02-25 | 2016-02-25 | Charge pump circuit and display device |
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| CN105553256B (en) | 2018-05-29 |
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