CN104820458B - A kind of voltage regulator circuit, power supervisor and display unit - Google Patents
A kind of voltage regulator circuit, power supervisor and display unit Download PDFInfo
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Abstract
The invention discloses a kind of voltage regulator circuit, power supervisor and display unit, not only comprise: the first reference signal end, signal output part, be connected on the first resistance and the second resistance between signal output part and the first reference signal end and be connected to the first resistance and the second resistance between the second reference signal end, also comprise: be connected in parallel on the first resistance two ends secondary voltage regulate electronic circuit. Because regulating electronic circuit, secondary voltage in above-mentioned voltage regulator circuit can pass through the resistance between conditioning signal output and the first reference signal end, after making the voltage of signal output part first become buffer voltagc, become again target voltage, even if the voltage of signal output part reaches target voltage after changing by two-stage step, thereby avoided in existing voltage regulator circuit, the voltage of signal output part just directly rises to the problem of target voltage after of short duration climbing.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a voltage regulator circuit, a power manager and a display device.
Background
The input voltage of the current display panel is generally a fixed voltage, but the display panel needs to work normally, and different circuit modules in the display panel need different working voltages. Therefore, the display panel generally divides an input voltage according to different circuit modules by a Power Manager (PMIC) into different target voltages, such as AVDD, DVDD, VON, VOFF, etc., to drive the different circuit modules in the display panel to operate normally.
Therefore, a power manager generally includes a plurality of voltage regulating circuits, each for outputting a target voltage. Specifically, the structure of the conventional voltage regulation circuit is shown in fig. 1a, and includes: a first reference signal terminal Vref1, a signal output terminal Vout, a first resistor R1 and a second resistor R2 connected in series between the signal output terminal Vout and the first reference signal terminal Vref1, and a second reference signal terminal Vref2 connected between the first resistor R1 and the second resistor R2. In this voltage regulating circuit, the voltage at the signal output terminal Vout: vout＝Vref2–(Vref1-Vref2) × (R1/R2), wherein VoutIs the voltage of the signal output terminal Vout, where Vref1Is the voltage of a first reference signal terminal Vref1, where Vref2Is the voltage of the second reference signal terminal Vref 2. For different voltage regulating circuits, Vref1And Vref2Generally, the voltage regulating circuit has a fixed value, so that the voltage regulating circuit can accurately output the target voltage according to the regulation of the ratio of the first resistor to the second resistor.
However, in the above-mentioned voltage regulating circuit, during the power-on process of the display panel, as shown in fig. 1b, the voltage V of the signal output terminal VoutoutAfter a short ramp, the voltage is directly raised to the target voltage, and the target voltage is assumed to be 8V. Therefore, a large instantaneous current is generated when the display panel is turned on, and an electric field inside the display panel is rapidly changed, so that the display panel has a plurality of adverse effects.
Disclosure of Invention
In view of this, embodiments of the present invention provide a voltage regulating circuit, a power manager and a display device, which are used to solve the problem in the prior art that the voltage at the signal output terminal of the voltage regulating circuit is prevented from directly rising to a target voltage after a short time of rising.
Accordingly, an embodiment of the present invention provides a voltage regulation circuit, including: the circuit comprises a first reference signal terminal, a signal output terminal, a first resistor and a second resistor which are connected between the signal output terminal and the first reference signal terminal in series, and a second reference signal terminal connected between the first resistor and the second resistor; further comprising: the secondary voltage regulator subcircuit is connected in parallel with two ends of the first resistor; wherein,
the secondary voltage regulating sub-circuit is used for changing the voltage of the signal output end into buffer voltage within preset time after signals are input at the first reference signal end and the second reference signal end; after the preset time, adjusting the resistance between the signal output end and the first reference signal end to change the voltage of the signal output end from the buffer voltage to a target voltage and maintain the target voltage, wherein the target voltage is not equal to the buffer voltage.
Specifically, in practical implementation, in the above circuit provided in the embodiment of the present invention, one end of the first resistor is connected to the signal output terminal, and one end of the second resistor is connected to the first reference signal terminal; or
One end of the second resistor is connected with the signal output end, and one end of the first resistor is connected with the first reference signal end.
In a possible implementation manner, in the above circuit provided in an embodiment of the present invention, the secondary voltage regulator sub-circuit specifically includes: the third resistor, the switch controller and the delay module; wherein,
one end of the third resistor is connected with one end of the first resistor, and the other end of the third resistor is connected with the other end of the first resistor through the switch controller;
the control end of the switch controller is connected with the delay module;
the delay module is used for controlling the switch controller to be in a cut-off state within a preset time after signals are input at the first reference signal end and the second reference signal end; and after the preset time, controlling the switch controller to be in a conducting state.
In a possible implementation manner, in the above circuit provided in an embodiment of the present invention, the delay module specifically includes: the fourth resistor, the capacitor, the signal input end and the control signal output end; wherein,
the control signal output end is respectively connected with the control end of the switch controller, one end of the fourth resistor and one end of the capacitor, the other end of the fourth resistor is connected with the signal input end, and the other end of the capacitor is grounded.
In a possible implementation manner, in the above circuit provided by the embodiment of the present invention, the switch controller is a switch transistor.
Specifically, in practical implementation, in the above circuit provided by the embodiment of the present invention, the switch transistor is an N-type transistor or a P-type transistor.
Correspondingly, the embodiment of the invention also provides a power supply manager, which comprises at least one voltage regulating circuit provided by the embodiment of the invention.
Correspondingly, the embodiment of the invention also provides a display device which comprises the power supply manager provided by the embodiment of the invention.
The voltage regulating circuit, the power manager and the display device provided by the embodiment of the invention not only comprise: first reference signal terminal, signal output terminal, series connection first resistance and the second resistance between signal output terminal and first reference signal terminal and connect the second reference signal terminal between first resistance and second resistance, still include: the secondary voltage regulator subcircuit is connected in parallel with two ends of the first resistor; the secondary voltage regulator sub-circuit is used for changing the voltage of the signal output end into buffer voltage within preset time after signals are input at the first reference signal end and the second reference signal end; after the preset time, adjusting the resistance between the signal output end and the first reference signal end to change the voltage of the signal output end from the buffer voltage to a target voltage and keep the target voltage, wherein the target voltage is not equal to the buffer voltage. The secondary voltage regulating sub-circuit in the voltage regulating circuit can make the voltage of the signal output end change into the buffer voltage and then into the target voltage by regulating the resistance between the signal output end and the first reference signal end, even if the voltage of the signal output end reaches the target voltage after two-stage step change, thereby avoiding the problem that the voltage of the signal output end directly rises to the target voltage after short-time climbing in the existing voltage regulating circuit.
Drawings
FIG. 1a is a schematic circuit diagram of a conventional voltage regulation circuit;
FIG. 1b is a schematic diagram of the voltage at the signal output of the voltage regulator circuit shown in FIG. 1a reaching a target voltage;
fig. 2a and fig. 2b are schematic structural diagrams of a voltage regulating circuit according to an embodiment of the present invention;
FIG. 2c is a schematic diagram of the voltage at the signal output of the voltage regulating circuit shown in FIGS. 2a and 2b reaching a target voltage;
fig. 3a to fig. 3d are schematic structural diagrams of a voltage regulating circuit according to an embodiment of the present invention.
Detailed Description
The following describes specific embodiments of a voltage regulating circuit, a power manager and a display device according to embodiments of the present invention in detail with reference to the accompanying drawings.
An embodiment of the present invention provides a voltage regulation circuit, as shown in fig. 2a and fig. 2b, including: a first reference signal terminal Vref1, a signal output terminal Vout, a first resistor R1 and a second resistor R2 connected in series between the signal output terminal Vout and the first reference signal terminal Vref1, and a second reference signal terminal Vref2 connected between the first resistor R1 and the second resistor R2; further comprising: a secondary voltage regulator sub-circuit 1 connected in parallel with both ends of the first resistor R1; wherein,
as shown in the input/output timing diagram of the circuit shown in fig. 2c, the secondary voltage regulator sub-circuit 1 is configured to change the voltage of the signal output terminal Vout into the buffer voltage V1 within a preset time T1 after the signals are input from the first reference signal terminal Vref1 and the second reference signal terminal Vref 2; after a predetermined time T1, the resistance between the signal output terminal Vout and the first reference signal terminal Vref1 is adjusted to make the voltage V of the signal output terminal VoutoutThe buffer voltage V1 is changed into a target voltage V2, and the target voltage V2 is maintained, wherein the target voltage V2 is not equal to the buffer voltage V1.
The voltage regulating circuit provided by the embodiment of the invention not only comprises: first reference signal terminal, signal output terminal, series connection first resistance and the second resistance between signal output terminal and first reference signal terminal and connect the second reference signal terminal between first resistance and second resistance, still include: the secondary voltage regulator subcircuit is connected in parallel with two ends of the first resistor; the secondary voltage regulator sub-circuit is used for changing the voltage of the signal output end into buffer voltage within preset time after signals are input at the first reference signal end and the second reference signal end; after the preset time, adjusting the resistance between the signal output end and the first reference signal end to change the voltage of the signal output end from the buffer voltage to a target voltage and keep the target voltage, wherein the target voltage is not equal to the buffer voltage. The secondary voltage regulating sub-circuit in the voltage regulating circuit can make the voltage of the signal output end change into the buffer voltage and then into the target voltage by regulating the resistance between the signal output end and the first reference signal end, even if the voltage of the signal output end reaches the target voltage after two-stage step change, thereby avoiding the problem that the voltage of the signal output end directly rises to the target voltage after short-time climbing in the existing voltage regulating circuit.
Specifically, in the above voltage regulating circuit according to the embodiment of the present invention, as shown in fig. 2a, one end of the first resistor R1 is connected to the signal output terminal Vout, and one end of the second resistor R2 is connected to the first reference signal terminal Vref1, that is, the secondary voltage regulating sub-circuit 1 is connected in series to the resistor near the signal output terminal Vout; or
As shown in fig. 2b, one end of the second resistor R2 is connected to the signal output terminal Vout, and one end of the first resistor R1 is connected to the first reference signal terminal Vref1, i.e. the secondary voltage regulator sub-circuit 1 is connected in series to the resistor near the first reference signal terminal Vref 1.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
Specifically, in the foregoing voltage regulation circuit provided in the embodiment of the present invention, as shown in fig. 3a and 3d, the secondary voltage regulation sub-circuit 1 may specifically include: a third resistor R3, a switch controller 11 and a delay module 12; wherein,
one end of the third resistor R3 is connected to one end of the first resistor R1, and the other end of the third resistor R3 is connected to the other end of the first resistor R1 through the switch controller 11;
the control end of the switch controller 11 is connected with the delay module 12;
the delay module 12 is configured to control the switch controller 11 to be in an off state within a preset time after the signals are input from the first reference signal terminal Vref1 and the second reference signal terminal Vref2, and control the switch controller 11 to be in an on state after the preset time. Thus, when the delay module 12 controls the switch controller 11 to be in the on state, the third resistor R3 is connected in parallel with the first resistor R1, so that the resistance between the signal output terminal Vout and the first reference signal terminal Vref1 is adjusted from R1+ R2 within the preset time to (R1 × R3)/(R1+ R3) + R2 after the preset time, and the voltage of the signal output terminal Vout is adjusted by the change of the resistance.
Specifically, in the above voltage regulating circuit according to the embodiment of the present invention, as shown in fig. 3a and 3b, when the first resistor R1 is close to the signal output terminal Vout, as shown in fig. 3a, one end of the third resistor R3 may be connected between the first resistor R1 and the second resistor R2, the other end of the third resistor R3 is connected to one end of the switch controller 11, and the other end of the switch controller 11 is connected to the signal output terminal Vout; alternatively, as shown in fig. 3b, one end of the switch controller 11 may be connected between the first resistor R1 and the second resistor R2, the other end of the switch controller 11 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the signal output terminal Vout; and is not limited herein.
Accordingly, in practical implementation, in the above voltage regulation circuit provided in the embodiment of the present invention, as shown in fig. 3c and 3d, when the first resistor R1 is close to the first reference signal terminal Vref1, as shown in fig. 3c, one end of the third resistor R3 may be connected between the first resistor R1 and the second resistor R2, the other end of the third resistor R3 is connected to one end of the switch controller 11, and the other end of the switch controller 11 is connected to the first reference signal terminal Vref 1; alternatively, as shown in fig. 3d, one end of the switch controller 11 may be connected between the first resistor R1 and the second resistor R2, the other end of the switch controller 11 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the first reference signal terminal Vref 1; and is not limited herein.
The above is only an example of the specific structure of the secondary voltage regulator sub-circuit, and in the specific implementation, the specific structure of the secondary voltage regulator sub-circuit is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Preferably, in the voltage regulating circuit provided in the embodiment of the present invention, as shown in fig. 3a to 3d, the delay module 12 may specifically include: a fourth resistor R4, a capacitor C, a signal input end Vin and a control signal output end Vc; wherein,
the control signal output end Vc is connected to the control end of the switch controller 11, one end of the fourth resistor R4, and one end of the capacitor C4, respectively, the other end of the fourth resistor R4 is connected to the signal input end Vin, and the other end of the capacitor C is grounded.
It should be noted that, when the delay module is composed of the fourth resistor and the capacitor, the charging duration of the capacitor is the preset time, so that when the signal input terminal, the first reference signal terminal and the second reference signal terminal have signals input at the same time, the switch controller is in the off state and the third resistor and the first resistor are in the off state because the capacitor is still in the charging state within the preset time, and therefore the resistance between the signal output terminal and the first reference signal terminal is R1+ R2, and after the preset time, the capacitor is fully charged and the switch controller is in the on state and the third resistor and the first resistor are connected in parallel, so that the resistance between the signal output terminal and the first reference signal terminal becomes (R1 × R3)/(R1+ R3) + R2.
The above is only an example of the specific structure of the delay module, and in the specific implementation, the specific structure of the delay module is not limited to the above structure provided by the embodiment of the present invention, and may also be other structures known by those skilled in the art, and is not limited herein.
Preferably, in the voltage regulating circuit provided in the embodiment of the present invention, as shown in fig. 3a to 3d, the switch controller 11 may be a switch transistor M. Further, the switching transistor M may be an N-type transistor or a P-type transistor, which is not limited herein.
It should be noted that the switching transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), and is not limited herein.
The operation of the voltage regulating circuit provided by the embodiment of the present invention will be described below by taking the voltage regulating circuits shown in fig. 3a and 3c as examples.
Example one:
taking the structure of the voltage regulation circuit shown in fig. 3a as an example to describe the operation process, specifically, when the first reference signal terminal Vref1, the second reference signal terminal Vref2, and the signal input terminal Vin all have signal inputs:
during a predetermined time, the capacitor C starts to charge, and the switching transistor M is in a turned-off state, so that only the first resistor R1 and the second resistor R2 between the first reference signal terminal Vref1 and the signal output terminal Vout are turned on, and the total resistance between the first reference signal terminal Vref1 and the signal output terminal Vout is R1+ R2. Assume that the voltage of the first reference signal terminal Vref1 is denoted as Vref1The voltage of the second reference signal terminal Vref2 is denoted as Vref2Voltage at the signal output terminal Vout represents VoutIn this stage, according to the formula (V)ref1-Vref2)/R2＝(Vref2-Vout) It can be known from/R1 that the voltage at the signal output terminal Vout changes from zero to Vout＝Vref2–(Vref1-Vref2) × (R1/R2), the voltage value is the buffer voltage, therefore, the buffer voltage is determined by the ratio of the first resistor and the second resistor in the predetermined time.
After a predetermined time, the capacitor C is fully charged, and the switching transistor M is in a conducting state, so that only the first resistor R1, the second resistor R2 and the third resistor R3 between the first reference signal terminal Vref1 and the signal output terminal Vout are conducting, and the total resistance between the first reference signal terminal Vref1 and the signal output terminal Vout becomes (R1 × R3)/(R1+ R3) + R2ref1-Vref2)/R2＝(Vref2-Vout)/[(R1×R3)/(R1+R3)]It can be known that the voltage of the signal output terminal Vout changes from the buffer voltage to the target voltage: vout＝Vref2–(Vref1-Vref2)(R1×R3)/[(R1+R3)×R2]And maintaining the target voltage, so that the target voltage is determined by the ratio of the first resistor, the second resistor and the third resistor within a preset time.
The voltage regulating circuit regulates the resistance between the signal output end and the first reference signal end through the secondary voltage regulating sub-circuit, so that the voltage of the signal output end is changed into the buffer voltage and then is changed into the target voltage, even if the voltage of the signal output end reaches the target voltage after passing through two-stage step change, the problem that the voltage of the signal output end directly rises to the target voltage after temporarily climbing in the existing voltage regulating circuit is avoided.
Example two:
taking the structure of the voltage regulation circuit shown in fig. 3c as an example to describe the operation process, specifically, when the first reference signal terminal Vref1, the second reference signal terminal Vref2, and the signal input terminal Vin all have signal inputs:
during a predetermined time, the capacitor C starts to charge, and the switching transistor M is in a turned-off state, so that only the first resistor R1 and the second resistor R2 between the first reference signal terminal Vref1 and the signal output terminal Vout are turned on, and the total resistance between the first reference signal terminal Vref1 and the signal output terminal Vout is R1+ R2. Assume that the voltage of the first reference signal terminal Vref1 is denoted as Vref1The voltage of the second reference signal terminal Vref2 is denoted as Vref2Voltage at the signal output terminal Vout represents VoutIn this stage, according to the formula (V)ref1-Vref2)/R1＝(Vref2-Vout) It can be known from/R2 that the voltage at the signal output terminal Vout changes from zero to Vout＝Vref2–(Vref1-Vref2) × (R2/R1), the voltage value is the buffer voltage, therefore, the buffer voltage is determined by the ratio of the first resistor and the second resistor in the predetermined time.
After a predetermined time, the capacitor C is fully charged, and the switching transistor M is in a conducting state, so that only the first resistor R1, the second resistor R2 and the third resistor R3 between the first reference signal terminal Vref1 and the signal output terminal Vout are conducting, and the total resistance between the first reference signal terminal Vref1 and the signal output terminal Vout becomes (R1 × R3)/(R1+ R3) + R2ref1-Vref2)/[(R1×R3)/(R1+R3)]＝(Vref2-Vout) /R2 may beIt is known that the voltage of the signal output terminal Vout changes from the buffer voltage to the target voltage Vout＝Vref2–(Vref1-Vref2)×R2/[(R1×R3)/(R1+R3)]And maintaining the target voltage, so that the target voltage is determined by the ratio of the first resistor, the second resistor and the third resistor within a preset time.
The voltage regulating circuit regulates the resistance between the signal output end and the first reference signal end through the secondary voltage regulating sub-circuit, so that the voltage of the signal output end is changed into the buffer voltage and then is changed into the target voltage, even if the voltage of the signal output end reaches the target voltage after passing through two-stage step change, the problem that the voltage of the signal output end directly rises to the target voltage after temporarily climbing in the existing voltage regulating circuit is avoided.
Based on the same inventive concept, embodiments of the present invention further provide a display device, including the electrostatic protection system provided in embodiments of the present invention, and since the principle of the display device to solve the problem is similar to that of the electrostatic protection system, the implementation of the display device may refer to the implementation of the electrostatic protection system, and repeated details are omitted.
Based on the same inventive concept, embodiments of the present invention further provide a display device, including any one of the display devices provided in embodiments of the present invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
The embodiment of the invention provides a voltage regulating circuit, a power supply manager and a display device, which not only comprise: first reference signal terminal, signal output terminal, series connection first resistance and the second resistance between signal output terminal and first reference signal terminal and connect the second reference signal terminal between first resistance and second resistance, still include: the secondary voltage regulator subcircuit is connected in parallel with two ends of the first resistor; the secondary voltage regulator sub-circuit is used for changing the voltage of the signal output end into buffer voltage within preset time after signals are input at the first reference signal end and the second reference signal end; after the preset time, adjusting the resistance between the signal output end and the first reference signal end to change the voltage of the signal output end from the buffer voltage to a target voltage and keep the target voltage, wherein the target voltage is not equal to the buffer voltage. The secondary voltage regulating sub-circuit in the voltage regulating circuit can make the voltage of the signal output end change into the buffer voltage and then into the target voltage by regulating the resistance between the signal output end and the first reference signal end, even if the voltage of the signal output end reaches the target voltage after two-stage step change, thereby avoiding the problem that the voltage of the signal output end directly rises to the target voltage after short-time climbing in the existing voltage regulating circuit.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A voltage regulation circuit comprising: the circuit comprises a first reference signal terminal, a signal output terminal, a first resistor and a second resistor which are connected between the signal output terminal and the first reference signal terminal in series, and a second reference signal terminal connected between the first resistor and the second resistor; it is characterized by also comprising: the secondary voltage regulator subcircuit is connected in parallel with two ends of the first resistor; wherein,
the secondary voltage regulating sub-circuit is used for changing the voltage of the signal output end into buffer voltage within preset time after signals are input at the first reference signal end and the second reference signal end; after the preset time, adjusting the resistance between the signal output end and the first reference signal end to change the voltage of the signal output end from the buffer voltage to a target voltage and maintain the target voltage, wherein the target voltage is not equal to the buffer voltage.
2. The voltage regulation circuit of claim 1 wherein one terminal of the first resistor is connected to the signal output terminal and one terminal of the second resistor is connected to the first reference signal terminal; or
One end of the second resistor is connected with the signal output end, and one end of the first resistor is connected with the first reference signal end.
3. The voltage regulation circuit of claim 2, wherein the secondary voltage regulation subcircuit, in particular, comprises: the third resistor, the switch controller and the delay module; wherein,
one end of the third resistor is connected with one end of the first resistor, and the other end of the third resistor is connected with the other end of the first resistor through the switch controller;
the control end of the switch controller is connected with the delay module;
the delay module is used for controlling the switch controller to be in a cut-off state within a preset time after signals are input at the first reference signal end and the second reference signal end; and after the preset time, controlling the switch controller to be in a conducting state.
4. The voltage regulation circuit of claim 3, wherein the delay module specifically comprises: the fourth resistor, the capacitor, the signal input end and the control signal output end; wherein,
the control signal output end is respectively connected with the control end of the switch controller, one end of the fourth resistor and one end of the capacitor, the other end of the fourth resistor is connected with the signal input end, and the other end of the capacitor is grounded.
5. The voltage regulation circuit of claim 3, wherein the switch controller is a switching transistor.
6. The voltage regulation circuit of claim 5, wherein the switching transistor is an N-type transistor or a P-type transistor.
7. A power manager comprising at least one voltage regulation circuit as claimed in any one of claims 1 to 6.
8. A display device comprising the power manager of claim 7.
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