JP6557567B2 - Charge / discharge control device - Google Patents

Description

  The present invention relates to a charge / discharge control device.

  Conventionally, when the current supply from the power supply to the load is sufficient, the switch output stage is stepped down to charge the battery from the power supply, and when the current supply from the power supply to the load is insufficient, the switch output stage is There has been proposed a charge / discharge control device that performs a boosting operation to discharge (current compensation) from a battery to a load.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP2015-149801A

  However, the conventional charge / discharge control device has room for further improvement (for example, improvement of transient response at the time of sudden load change) in the charge / discharge switching operation.

  In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed in the present specification provides a charge / discharge control device capable of appropriately switching between a battery charging operation and a discharging operation. With the goal.

  Therefore, the charge / discharge control device disclosed in this specification includes a switch output stage connected between a power source and a load and a battery; and when the current supply from the power source to the load is sufficient, The switch output stage is stepped down to charge the battery from the power source, and when the current supply from the power source to the load is insufficient, the switch output stage is boosted to supply the load from the battery to the load. A switch driving device that performs discharging, and the switch driving device drives the switch output stage so as to promote an increase when battery current starts to flow from the battery to the load during discharging of the battery. The configuration is the first configuration.

  In the charge / discharge control device having the first configuration, the switch driving device is configured so that the input current supplied from the power source does not exceed an upper limit value when charging or discharging the battery. A configuration for driving the stage (second configuration) may be used.

  In the charging / discharging control device having the first or second configuration, the switch driving device causes the switch output stage to prevent a battery current flowing from the battery to the load from exceeding an upper limit value when the battery is discharged. A configuration for driving (third configuration) is preferable.

  In the charge / discharge control device having any one of the first to third configurations, the switch driving device is configured such that the battery current flowing from the power source to the battery does not exceed an upper limit value when the battery is charged. A configuration for driving the output stage (fourth configuration) is preferable.

  In the charge / discharge control device having any one of the first to fourth configurations, the switch drive device drives the switch output stage so that the battery voltage does not exceed an upper limit value when the battery is charged ( The fifth configuration is preferable.

  In the charging / discharging control device having any one of the first to fifth configurations, the switch driving device is a measured value of an input current supplied from the power supply or a measured value of a battery current flowing from the battery to the load. May be configured to output to the outside of the apparatus (sixth configuration).

  In the charging / discharging control device having any one of the first to sixth configurations, the switch driving device includes a first voltage generating circuit that generates a first voltage corresponding to a charging / discharging state of the battery, and a first waveform of a slope waveform. A second voltage generation circuit for generating two voltages, a comparison circuit for comparing the first voltage and the second voltage to generate a pulse width modulation signal, and the switch output stage according to the pulse width modulation signal. And a driving circuit to be driven (seventh configuration).

  In the charge / discharge control device according to the seventh configuration, the switch driving device further includes a zero-cross detection circuit that detects that the battery current has reached zero and forcibly stops the switch output stage. (Eighth configuration) is preferable.

  In the charge / discharge control device having any one of the first to eighth configurations, the switch output stage includes a half-bridge output circuit including a pair of upper and lower switch elements connected in series between the power source and a ground terminal, A configuration including a LC filter circuit connected between the half-bridge output circuit and the battery (a ninth configuration) may be employed.

  An electronic device disclosed in the present specification includes a charge / discharge control device having any one of the first to ninth configurations, and a battery charged / discharged by the charge / discharge control device ( Tenth configuration).

  According to the invention disclosed in the present specification, it is possible to provide a charge / discharge control device capable of appropriately switching between a battery charging operation and a discharging operation.

Application diagram showing an example of the overall configuration of an electronic device Current path diagram when charging the battery Current path diagram during battery discharge Block diagram showing an example of a main part configuration of a semiconductor device Block diagram showing one configuration example of a drive circuit 1 is a circuit diagram showing a first embodiment of a first voltage generation circuit; Timing chart showing an example of charge / discharge switching operation Timing chart showing first example (high duty) of charging operation Timing chart showing second example (low duty) of charging operation Timing chart showing first example (low duty) of discharge operation Timing chart showing second example of discharge operation (high duty) Circuit diagram showing a second embodiment of the first voltage generation circuit Timing chart showing the effect of improving transient response External view of laptop

<Electronic equipment>
FIG. 1 is an application diagram illustrating an example of the overall configuration of an electronic device. The electronic device X of this configuration example includes a charge / discharge control device 10, a battery 20, and a host 30.

  The charge / discharge control device 10 is a main body that controls the charging operation from the adapter ADP to the battery 20 and the discharging operation from the battery 20 to the system SYS. The adapter ADP is a power source for the electronic device X, and corresponds to, for example, an AC adapter that generates a DC voltage from an AC voltage. The system SYS is a load that operates upon receiving power supply from the adapter ADP or the battery 20, and corresponds to, for example, a power management IC that supplies various drive voltages to a CPU [central processing unit].

  The battery 20 is a secondary battery that is charged and discharged by the charge / discharge control device 10. As the battery 20, a lithium ion battery, a nickel metal hydride battery, a nickel cadmium battery, or the like can be used.

  The host 30 exchanges information with the charge / discharge control device 10 and controls the charge / discharge operation of the battery 20 in an integrated manner. Examples of information transmitted from the charge / discharge control device 10 to the host 30 include an actual measured value of the adapter current I1 and an actual measured value of the battery current I2 (for example, a discharge current). On the other hand, the transmission information from the host 30 to the charge / discharge control device 10 includes an upper limit value of the adapter current I1, an upper limit value of the battery current I2, an upper limit value of the battery voltage V20, or a setting value of the switching frequency. it can. For example, by appropriately changing the upper limit value of the battery voltage V20, it is possible to flexibly cope with a change in the number of cells of the battery 20. In addition, as a communication means between the charge / discharge control device 10 and the host 30, a dedicated communication terminal provided for each of various communication signals may be used, or a general-purpose communication interface (for example, SMB [ system management bus]) may be used.

<Charge / discharge control device>
Next, the configuration and operation of the charge / discharge control device 10 will be described with reference to FIG. The charge / discharge control apparatus 10 of this configuration example includes a semiconductor device 11 and various discrete components (N-channel MOS [metal oxide semiconductor] field effect transistors N1 to N3, a coil L1, capacitors C1 and C2 attached to the semiconductor device 11). And resistors R1 and R2).

  The semiconductor device 11 is a switch drive device that performs drive control of the switch output stage (N1, N2, L1, C1) in order to charge and discharge the battery 20. The semiconductor device 11 has a plurality of external terminals (ACP, ACN, BGATE, BOOT, HDRV, PHASE, LDRV, SRP, SRN) as means for establishing electrical connection with the outside of the device.

  The ACP pin is connected to the adapter ADP and the first end of the sense resistor R1. The ACN pin is connected to the second end of the sense resistor R1, the system SYS, the drain of the transistor N1, and the drain of the transistor N3. The sense resistor R1 is a current / voltage conversion element for detecting an adapter current I1 (= corresponding to an input current) supplied from the adapter ADP as a voltage signal (= sense voltage VI1).

  The BGATE pin is connected to the gate of transistor N3. The BOOT pin is connected to the first end of the capacitor C2. The HDRV pin is connected to the gate of the transistor N1. The PHASE pin is connected to the second end of the capacitor C2, the source of the transistor N1, the drain of the transistor N2, and the first end of the coil L1. The LDRV pin is connected to the gate of transistor N2. The source of the transistor N2 is connected to the ground terminal.

  The SRP pin is connected to the source of the transistor N3, the second end of the coil L1, and the first end of the sense resistor R2. The SRN pin is connected to the second end of the sense resistor R2, the first end of the capacitor C1, and the positive end of the battery 20. The second terminal of the capacitor C1 and the negative terminal of the battery 20 are connected to the ground terminal. The sense resistor R2 is a current / voltage conversion element for detecting the battery current I2 (charging current or discharging current) flowing through the battery 20 as a voltage signal (= sense voltage VI2). The sense voltage VI2 becomes positive when the battery 20 is charged and becomes negative when the battery 20 is discharged.

  Among the discrete components, the transistors N1 and N2, the coil L1, and the capacitor C1 function as a switch output stage connected between the power supply terminal (= application terminal of the power supply voltage Vx) and the battery 20. More specifically, the transistors N1 and N2 are a pair of upper and lower switch elements connected in series between a power supply terminal and a ground terminal, and a rectangular wave-shaped switch voltage Vsw is generated by a complementary on / off operation. A half-bridge output circuit to be generated is formed. The coil L1 and the capacitor C1 form an LC filter circuit connected between the half-bridge output circuit (N1 and N2) and the battery 20.

  When the role of the transistors N1 and N2 is described functionally, the transistor N1 functions as an output transistor and the transistor N2 functions as a synchronous rectification transistor when the battery 20 is charged (= step-down operation of the switch output stage) To do. On the other hand, when the battery 20 is discharged (= when boosting the switch output stage), the transistor N2 functions as an output transistor, and the transistor N1 functions as a synchronous rectification transistor.

  Among the discrete components, the capacitor C2 forms a bootstrap circuit together with the diode D1 (see FIG. 4) built in the semiconductor device 11.

  Of the discrete components, the transistor N3 functions as a short switch for directly connecting the system SYS and the battery 20.

  In the charge / discharge control device 10 of this configuration example, when the current supply from the adapter ADP to the system SYS is sufficient, the semiconductor device 11 performs step-down operation of the switch output stage to charge the battery 20 from the adapter ADP. On the other hand, when the current supply from the adapter ADP to the system SYS is insufficient, the switch output stage is boosted to discharge the battery 20 from the system SYS (current compensation).

  FIG. 2 is a current path diagram during charging of the battery 20 (= during step-down operation of the switch output stage). In this case, charging from the adapter ADP to the battery 20 is performed in parallel with current supply from the adapter ADP to the system SYS.

  FIG. 3 is a current path diagram when the battery 20 is discharged (= when the switch output stage is boosted). In this case, current is supplied from the adapter ADP to the system SYS, and discharge from the battery 20 to the system SYS is performed in parallel.

<Semiconductor device>
FIG. 4 is a block diagram illustrating a configuration example of a main part of the semiconductor device 11. The semiconductor device 11 of this configuration example includes, as main circuit blocks, a first voltage generation circuit 100, a second voltage generation circuit 200, a comparison circuit 300, a drive circuit 400, an internal power supply circuit 500, and a zero cross detection circuit. 600 is integrated.

  The first voltage generation circuit 100 monitors the sense voltage VI1 appearing between the ACP pin and the ACN pin and the sense voltage VI2 appearing between the SRP pin and the SRN pin, respectively, and the first voltage according to the charge / discharge state of the battery 20 Va is generated. In addition, the first voltage generation circuit 100 generates a turbo signal St corresponding to the monitoring result of the sense voltage VI1 and outputs the turbo signal St to the zero cross detection circuit 600. The turbo signal St is a binary signal that is at a high level during the charging mode (step-down mode) and is at a low level during the discharge mode (step-up mode).

  The second voltage generation circuit 200 generates a second voltage Vb having a slope waveform (such as a ramp waveform, a triangular waveform, or an RC waveform) at a predetermined switching frequency fsw.

  The comparison circuit 300 compares the first voltage Va input to the non-inverting input terminal (+) and the second voltage Vb input to the inverting input terminal (−) to generate the pulse width modulation signal PWM. The pulse width modulation signal PWM is at a low level when the first voltage Va is lower than the second voltage Vb, and is at a high level when the first voltage Va is higher than the second voltage Vb.

  The drive circuit 400 operates by receiving the internal power supply voltage Vreg and the boost voltage VB, and generates the gate signals GH and GL according to the pulse width modulation signal PWM.

  The internal power supply circuit 500 generates a predetermined internal power supply voltage Vreg and supplies it to the drive circuit 400. The internal power supply voltage Vreg is also applied to the anode of the diode D1 (forward voltage drop: Vf). The cathode of the diode D1 is connected to the BOOT pin and forms a bootstrap circuit together with the external capacitor C2 (see FIGS. 1 to 3). Therefore, at the BOOT pin, it is possible to obtain a boost voltage VB that is higher than the switch voltage Vsw appearing at the PHASE pin by the charging voltage (≈Vreg−Vf) of the capacitor C2.

  The zero-cross detection circuit 600 generates a zero-cross signal Sz corresponding to the monitoring result of the sense voltage VI2 and outputs it to the drive circuit 400. The zero cross signal Sz is at a low level when the battery current I2 is flowing, and is at a high level when the battery current I2 is not flowing (= when the battery current I2 becomes zero). The drive circuit 400 has a function of forcibly stopping the switch output stage while the zero-cross signal Sz is at a high level.

  Note that the detection polarity of the zero cross detection circuit 600 is switched according to the turbo signal St. For example, since the battery current I2 flows from the adapter ADP toward the battery 20 during the charging mode (step-down mode), the sense voltage VI2 varies in the positive region. Therefore, when the turbo signal St is at the high level (= the logic level in the charging mode), the zero cross detection circuit 600 sets the zero cross signal Sz to the high level when the sense voltage VI2 reaches the zero value from the positive value. increase.

  On the other hand, in the discharge mode (in the boost mode), since the battery current I2 flows out from the battery 20 toward the system SYS, the sense voltage VI2 varies in the negative region. Therefore, when the turbo signal St is at the low level (= the logic level in the discharge mode), the zero cross detection circuit 600 sets the zero cross signal Sz to the high level when the sense voltage VI2 reaches the zero value from the negative value. increase.

<Drive circuit>
FIG. 5 is a block diagram illustrating a configuration example of the drive circuit 400. The drive circuit 400 of this configuration example includes drive units 410 and 420 and a control unit 430.

  The driver 410 generates the gate signal GH by increasing the current capability of the control signal SH. The gate signal GH is at a high level when the control signal SH is at a high level, and is at a low level when the control signal SH is at a low level. The upper power supply terminal of the drive unit 410 is connected to the application terminal of the boost voltage VB, and the lower power supply terminal of the drive part 410 is connected to the application terminal of the switch voltage Vsw. Therefore, the gate signal GH is a binary signal that is pulse-driven between the boost voltage VB and the switch voltage Vsw.

  The driver 420 generates the gate signal GL by increasing the current capability of the control signal SL. The gate signal GL is at a high level when the control signal SL is at a high level, and is at a low level when the control signal SH is at a low level. The upper power supply terminal of the drive unit 420 is connected to the application terminal for the internal power supply voltage Vreg, and the lower power supply terminal of the drive unit 420 is connected to the application terminal for the ground voltage GND. Therefore, the gate signal GL is a binary signal that is pulse-driven between the internal power supply voltage Vreg and the ground voltage GND.

  The controller 430 operates in response to the supply of the internal power supply voltage Vreg, and generates control signals SH and SL according to the pulse width modulation signal PWM. More specifically, when the pulse width modulation signal PWM is at a high level, the control signal SH is basically at a high level and the control signal SL is at a low level. On the other hand, when the pulse width modulation signal PWM is at a low level, the control signal SH is basically at a low level and the control signal SL is at a high level.

  That is, when the pulse width modulation signal PWM is at a high level, the transistor N1 is basically turned on and the transistor N2 is turned off. On the other hand, when the pulse width modulation signal PWM is at a low level, the transistor N1 is basically turned off and the transistor N2 is turned on. Thus, the transistors N1 and N2 forming the switch output stage are turned on / off in a complementary manner.

  However, if the on / off switching timings of the transistors N1 and N2 are completely reversed, the transistors N1 and N2 are turned on simultaneously unintentionally, which may cause an excessive through current. Therefore, the control unit 430 has a function of providing both simultaneous off periods (so-called dead time) at the on / off switching timing of the transistors N1 and N2.

  More specifically, when the pulse width modulation signal PWM rises from a low level to a high level, the control unit 430 conversely performs the pulse width modulation such that the transistor N2 is turned off and then the transistor N1 is turned on. When the signal PWM falls from the high level to the low level, each on / off switching timing is appropriately controlled so that the transistor N1 is turned on after the transistor N1 is turned off.

  The control unit 430 also has a function of forcibly stopping the switch output stage while the zero cross signal Sz is at a high level. During the forced stop of the switch output stage, the control signals SH and SL are both at a low level.

<First Voltage Generation Circuit (First Embodiment)>
FIG. 6 is a circuit diagram showing a first embodiment of the first voltage generation circuit 100. The first voltage generation circuit 100 of the present embodiment includes differential amplifiers 111 to 113, error amplifiers 121 to 124, a voltage dividing unit 130, a first voltage generation unit 140, and a charge / discharge switching unit 150. .

  The differential amplifier 111 amplifies the sense voltage VI1 input between the non-inverting input terminal (+) connected to the ACP pin and the inverting input terminal (−) connected to the ACN pin, and the amplified voltage V111 and V111x (= V111 / α, where α> 1) are generated. Accordingly, the amplified voltages V111 and V111x increase as the adapter current I1 flowing from the ACP pin to the ACN pin increases. That is, the differential amplifier 111 functions as adapter current monitoring means.

  The differential amplifier 112 amplifies the sense voltage VI2 input between the non-inverting input terminal (+) connected to the SRN pin and the inverting input terminal (−) connected to the SRP pin, and the amplified voltage V112 is generated. Therefore, the amplified voltage V112 becomes higher as the battery current I2 flowing from the SRN pin to the SRP pin (for the sake of convenience, hereinafter referred to as battery discharge current I2d) is increased. That is, the differential amplifier 112 functions as a discharge current monitoring unit.

  The differential amplifier 113 amplifies the sense voltage VI2 input between the non-inverting input terminal (+) connected to the SRP pin and the inverting input terminal (−) connected to the SRN pin, and the amplified voltage V113 is generated. Accordingly, the amplified voltage V113 becomes higher as the battery current I2 flowing from the SRP pin to the SRN pin (for convenience sake, hereinafter referred to as battery charging current I2c) is increased. That is, the differential amplifier 113 functions as a charging current monitoring unit.

  The error amplifier 121 generates a current I121 according to a difference between a predetermined reference voltage V1 input to the non-inverting input terminal (+) and an amplified voltage V111 input to the inverting input terminal (−). An output amplifier (a so-called gm amplifier or transconductance amplifier). When the amplified voltage V111 is lower than the reference voltage V1, an error current I121 having a magnitude corresponding to the difference flows in the positive direction (= direction of flowing out from the error amplifier 121). On the other hand, when the amplified voltage V111 is higher than the reference voltage V1, an error current I121 corresponding to the difference flows in the negative direction (= direction flowing into the error amplifier 121). The reference voltage V1 corresponds to the upper limit value of the adapter current I1. That is, the error amplifier 121 forms a feedback loop for limiting the adapter current I1 to the upper limit value or less.

  The error amplifier 122 generates a current I122 according to the difference between a predetermined reference voltage V2 input to the inverting input terminal (−) and the amplified voltage V112 input to the non-inverting input terminal (+). Output amplifier. When the amplified voltage V112 is higher than the reference voltage V2, an error current I122 having a magnitude corresponding to the difference flows in the positive direction (= direction of flowing out from the error amplifier 122). On the other hand, when the amplified voltage V112 is lower than the reference voltage V2, an error current I122 corresponding to the difference flows in the negative direction (= direction flowing into the error amplifier 122). The reference voltage V2 corresponds to the upper limit value of the discharge current. That is, error amplifier 122 forms a feedback loop for limiting battery discharge current I2d to an upper limit value or less.

  The error amplifier 123 generates a current I123 according to the difference between the predetermined reference voltage V3 input to the non-inverting input terminal (+) and the amplified voltage V113 input to the inverting input terminal (−). Output amplifier. When the amplified voltage V113 is lower than the reference voltage V3, an error current I123 having a magnitude corresponding to the difference flows in the positive direction (= direction of flowing out from the error amplifier 123). On the other hand, when the amplified voltage V113 is higher than the reference voltage V3, an error current I123 corresponding to the difference flows in the negative direction (= direction into the error amplifier 123). The reference voltage V3 corresponds to the upper limit value of the charging current. That is, error amplifier 123 forms a feedback loop for limiting battery charging current I2c to an upper limit value or less.

  The error amplifier 124 generates an error current I124 according to a difference between a predetermined reference voltage V4 input to the non-inverting input terminal (+) and the divided voltage V130 input to the inverting input terminal (−). Current output amplifier. When the divided voltage V130 is lower than the reference voltage V4, an error current I124 having a magnitude corresponding to the difference flows in the positive direction (= direction of flowing out from the error amplifier 124). On the other hand, when the divided voltage V130 is higher than the reference voltage V4, an error current I124 corresponding to the difference flows in the negative direction (= direction flowing into the error amplifier 124). Reference voltage V4 corresponds to the upper limit value of battery voltage V20. That is, the error amplifier 124 forms a feedback loop for limiting the battery voltage V20 to the upper limit value or less.

  The voltage divider 130 includes resistors 131 and 132 connected in series between the SRN pin (= the application terminal of the battery voltage V20) and the ground terminal, and generates the divided voltage V130 by dividing the battery voltage V20. To do.

  The first voltage generator 140 receives the error currents I121 to I124 and generates the first voltage Va.

  The charge / discharge switching unit 150 controls the switching from the charge mode (step-down mode) to the discharge mode (step-up mode) by monitoring the amplified voltage V111x (and thus the adapter current I1).

<First voltage generator>
Next, the configuration and operation of the first voltage generation unit 140 will be described with reference to FIG. The first voltage generation unit 140 of this configuration example includes npn-type bipolar transistors n1 and n2, pnp-type bipolar transistors p1 to p3, and current sources CS0 to CS2.

  The collector of the transistor n1 is connected to the internal power supply terminal. The emitter of the transistor n1 is connected to the output terminal of the error amplifier 121. The base of the transistor n1 is connected to the output terminal of the error amplifier 122. The base of the transistor p1 is connected to the output terminal of the error amplifier 121. The base of the transistor p2 is connected to the output terminal of the error amplifier 124. Both the collector of the transistor p1 and the collector of the transistor p2 are connected to the ground terminal. The base of the transistor p3 is connected to the output terminal of the error amplifier 123, and is also connected to the emitter of the transistor p1 and the emitter of the transistor p2. The collector of the transistor p3 is connected to the ground terminal. The emitter of the transistor p3 is connected to the base of the transistor n2. The collector of the transistor n2 is connected to the internal power supply terminal. The emitter of the transistor n2 is connected to the output terminal of the first voltage Va. The current source CS0 is connected between the internal power supply terminal and the base of the transistor p3. The current source CS1 is connected between the internal power supply terminal and the emitter of the transistor p3. The current source CS2 is connected between the emitter of the transistor n2 and the ground terminal.

  First, feedback control based on the error current I121 (= upper limit control of the adapter current I1) will be described. For example, when the adapter current I1 increases as the system current I0 (= corresponding to the load current flowing through the system SYS) increases, the amplified voltage V111 increases. Here, while the amplified voltage V111 is lower than the reference voltage V1, the error current I121 in the positive direction decreases as the adapter current I1 increases. Further, when the amplified voltage V111 becomes higher than the reference voltage V1, a negative error current I121 starts to flow. Due to this behavior, the conductivity of the transistor p1 is increased and the base voltage of the transistor p3 is lowered, so that the first voltage Va is lowered.

  That is, in the feedback control based on the error current I121, the first voltage Va is decreased as the adapter current I1 is increased, and the duty of the pulse width modulation signal PWM (= the ratio of the high level period in the switching period) is decreased. As a result, in the charging mode (step-down mode), the duty of the switch output stage decreases, so that the battery charging current I2c decreases and the adapter current I1 decreases. On the other hand, in the discharge mode (boost mode), the duty of the switch output stage increases, so that the battery discharge current I2d increases and the adapter current I1 decreases.

  As described above, the semiconductor device 11 drives the switch output stage (N1, N2, L1, C1) so that the adapter current I1 does not exceed the predetermined upper limit value when the battery 20 is charged or discharged. It has a function to do.

  Next, feedback control based on error current I122 (= upper limit control of battery discharge current I2d) will be described. When the battery discharge current I2d increases, the amplified voltage V112 increases. Here, while the amplified voltage V112 is lower than the reference voltage V2, the error current I122 in the negative direction decreases as the battery discharge current I2d increases. Further, when the amplified voltage V112 becomes higher than the reference voltage V2, the error current I122 in the positive direction starts to flow. This behavior increases the conductivity of the transistor n1 and raises the base voltage of the transistor p1. Accordingly, the conductivity of the transistor p1 is reduced and the base voltage of the transistor p3 is raised, so that the first voltage Va increases.

  That is, in the feedback control based on the error current I122, the first voltage Va is increased as the battery discharge current I2d is increased, and the duty of the pulse width modulation signal PWM is increased. As a result, the duty of the switch output stage decreases, and the battery discharge current I2d decreases.

  As described above, the semiconductor device 11 has a function of driving the switch output stages (N1, N2, L1, C1) so that the battery discharge current I2d does not exceed a predetermined upper limit value when the battery 20 is discharged. Yes.

  Next, feedback control (= upper limit control of battery charging current I2c) based on error current I123 will be described. As the battery charging current I2c increases, the amplified voltage V113 increases. Here, while the amplified voltage V113 is lower than the reference voltage V3, the error current I123 in the positive direction decreases as the battery charging current I2c increases. Furthermore, when the amplified voltage V113 becomes higher than the reference voltage V3, a negative error current I123 starts to flow. Due to this behavior, the base voltage of the transistor p3 is lowered, so that the first voltage Va is lowered.

  That is, in the feedback control based on the error current I123, the first voltage Va is decreased as the battery charging current I2c is increased, and the duty of the pulse width modulation signal PWM is decreased. As a result, the duty of the switch output stage decreases, and the battery charging current I2c decreases.

  Thus, the semiconductor device 11 has a function of driving the switch output stages (N1, N2, L1, C1) so that the battery charging current I2c does not exceed a predetermined upper limit value when the battery 20 is charged. Yes.

  As a situation where the feedback loop using the error amplifier 123 is effective, for example, a situation where the adapter current I1 is smaller than a predetermined upper limit value and the battery voltage V20 does not reach the predetermined upper limit value is cited. Can do.

  Next, feedback control (= upper limit control of battery voltage V20) based on error current I124 will be described. When the battery voltage V20 increases as the battery 20 is charged, the divided voltage V130 increases. Here, while the divided voltage V130 is lower than the reference voltage V4, the positive error current I124 decreases as the battery voltage V20 increases. Further, when the divided voltage V130 becomes higher than the reference voltage V4, the error current I124 in the negative direction starts to flow. This behavior increases the conductivity of the transistor n1 and raises the base voltage of the transistor p1. Accordingly, the conductivity of the transistor p1 is reduced and the base voltage of the transistor p3 is raised, so that the first voltage Va increases.

  That is, in the feedback control based on the error current I124, the higher the battery voltage V20, the lower the first voltage Va and the lower the duty of the pulse width modulation signal PWM. As a result, the duty of the switch output stage decreases, and the battery voltage V20 decreases.

  Thus, the semiconductor device 11 has a function of driving the switch output stages (N1, N2, L1, C1) so that the battery voltage V20 does not exceed a predetermined upper limit value when the battery 20 is charged. .

  As a situation in which the feedback loop using the error amplifier 124 is effective, for example, the adapter current I1 is smaller than a predetermined upper limit value, and the battery 20 is charged and the battery voltage V20 is near the predetermined upper limit value. Can be mentioned.

<Charge / discharge switching unit>
Next, the configuration and operation of the charge / discharge switching unit 150 will be described with reference to FIG. The charge / discharge switching unit 150 of this configuration example includes a comparator 151, a logic unit 152, an inverter 153, and a P-channel MOS field effect transistor 154.

  The comparator 151 compares the amplified voltage V111x input to the non-inverting input terminal (+) with the reference voltage V1 input to the inverting input terminal (−), and generates a comparison signal S151. The comparison signal S151 is at a low level when the amplified voltage V111x is lower than the reference voltage V1, and is at a high level when the amplified voltage V111x is higher than the reference voltage V1. As described above, the amplified voltage V111x has a voltage value (= V111 / α) obtained by dividing the amplified voltage V111 by a predetermined coefficient α (> 1). Accordingly, the comparator 151 functions as an adapter current monitoring unit that detects whether or not the adapter current I1 exceeds a threshold value (= α × V1) that is higher than a predetermined upper limit (= V1).

  The logic unit 152 generates a high-level one-shot pulse for the charge / discharge switching signal S152 using the rising edge of the comparison signal S151 as a trigger, and also changes the turbo signal St from the high level (= the logic level in the charge mode) to the low level. (= Logic level in discharge mode)

  The inverter 153 generates the gate signal S153 by logically inverting the charge / discharge switching signal S152.

  The transistor 154 is connected between the internal power supply terminal and the base of the transistor p1, and is turned on / off according to the gate signal S153. More specifically, the transistor 154 is turned off when the gate signal S153 is at a high level, and turned on when the gate signal S153 is at a low level.

  When the comparison signal S151 rises to a high level and a one-shot pulse is generated in the charge / discharge switching signal S152, the gate signal S153 falls from a high level to a low level, so that the transistor 154 is turned on. As a result, since the base of the transistor p1 is pulled up to the internal power supply terminal, the first voltage Va is sharply raised. Hereinafter, such charge / discharge switching operation will be described in detail.

<Charge / discharge switching operation>
FIG. 7 is a timing chart showing an example of the charge / discharge switching operation. From the top, the gate signals GH and GL, the system current I0 (solid line), the adapter current I1 (large broken line), the battery current I2 (small broken line), The behavior of the first voltage Va (small broken line), the second voltage Vb (solid line), and the turbo signal St is depicted. In this figure, the battery charging current I2c is a positive (> 0) battery current I2, and the battery discharging current I2d is a negative (<0) battery current I2.

  Prior to time t1, system current I0 is hardly required, and adapter current I1 is maintained at a current value sufficiently smaller than the upper limit value. Under such circumstances, the gate signals GH and GL at an appropriate duty by the upper limit control (= constant current control) of the battery charging current I2c described above or the upper limit control (= constant voltage control) of the battery voltage V20. Is generated, and the battery 20 is charged.

  When the system current I0 increases rapidly at time t1, the adapter current I1 also increases accordingly. Under such circumstances, the first voltage Va is lowered by the upper limit control of the adapter current I1 described above, and the duty of the switch output stage is reduced, so that the battery charging current I2c starts to decrease.

  After the time t1, the adapter current I1 continues to increase, and when the first voltage Va decreases to a voltage value lower than the lower end value of the second voltage Vb, the duty of the switch output stage becomes zero, and the battery 20 is charged from the adapter ADP. The operation is stopped. Therefore, priority is given to power supply from the adapter ADP to the system SYS.

  Nevertheless, if the adapter current I1 continues to increase and the adapter current I1 exceeds a predetermined upper limit value (corresponding to V1) at time t2, the charge / discharge switching unit described above Due to the action of 150, the first voltage Va is pulled up to a voltage value exceeding the upper end value of the second voltage V2, and the turbo signal St is changed from a high level (= logic level in the charge mode) to a low level (= in the discharge mode). To the logic level). As described above, in a situation where the adapter current I1 exceeds the predetermined threshold value, it is considered that power supply from the battery 20 to the system SYS (= compensation of the system current I0) is necessary. The operation mode is switched from the step-down mode to the step-up mode.

  At time t2, the switch output stage is forcibly turned off (= transistors N1 and N2 are both turned off) due to zero-crossing detection (details will be described later) of the battery charging current I2c before that time t2. It has become.

  When the first voltage Va falls below the second voltage Vb at time t3, the forced output state of the switch output stage is released and the boosting operation is started. As a result, since the battery discharge current I2d starts to flow from the battery 20 toward the system SYS, the adapter current I1 starts to decrease. Thereafter, the adapter current I1 and the battery discharge current I2d are adjusted to the respective upper limit values, and the boosting mode reaches a steady state.

  Next, the operation states (a) to (d) in the drawing will be described in detail with reference to FIGS.

  FIG. 8 is a timing chart showing a first example (high duty) of the charging operation. In order from the top, the gate signals GH and GL, the battery current I2 (= battery charging current I2c), the zero cross signal Sz, and the first voltage Va. (Small broken line) and the behavior of the second voltage Vb (solid line) are depicted. This figure corresponds to the operation state (a) in FIG. 7 (= before time t1).

  At times t10 to t11, since the second voltage Vb is lower than the second voltage Va, the gate signal GH becomes high level and the gate signal GL becomes low level. Therefore, since the transistor N1 is turned on and the transistor N2 is turned off, the battery current I2 increases.

  When the second voltage Vb becomes higher than the first voltage Va at time t11, the gate signal GH becomes low level and the gate signal GL becomes high level. Therefore, the transistor N1 is turned off and the transistor N2 is turned on, so that the battery current I2 starts to decrease.

  When the second voltage Vb is reset to the lower end value at time t12, the second voltage Vb becomes lower than the first voltage Va again, so that the gate signal GH becomes high level and the gate signal GL becomes low level. Therefore, since the transistor N1 is turned on and the transistor N2 is turned off, the battery current I2 starts to increase again.

  Also after time t12, the charging operation of the battery 20 (= step-down operation of the switch output stage) is performed by repeatedly turning on / off the transistors N1 and N2 as described above.

  In the example of this figure, the duty of the switch output stage is high, and sufficient energy is stored in the coil L1 during the ON period (time t10 to t11, time t12 to t13, time t14 to t15) of the transistor N1. . Therefore, the battery current I2 excited by the coil L1 does not fall below the zero value during the ON period (time t11 to t12, time t13 to t14, time t15 to t16) of the transistor N2. As a result, the zero cross signal Sz remains maintained at a low level.

  FIG. 9 is a timing chart showing a second example (low duty) of the charging operation. In order from the top, the gate signals GH and GL, the battery current I2 (= battery charging current I2c), the zero cross signal Sz, and the first voltage Va. (Small broken line) and the behavior of the second voltage Vb (solid line) are depicted. This figure corresponds to the operating state (b) in FIG. 7 (= immediately before time t2).

  From time t20 to t21, the second voltage Vb is lower than the second voltage Va, and the battery current I2 increases. When the second voltage Vb becomes higher than the first voltage Va at time t21, the battery current I2 starts to decrease. The steps so far are the same as the times t10 to t11 in FIG.

  However, in the example of this figure, since the duty of the switch output stage is low, sufficient energy is not stored in the coil L1 during the ON period (time t20 to t21) of the transistor N1. Therefore, the battery current I2 excited by the coil L1 falls below the zero value during the ON period (time t21 to t23) of the transistor N2 (see time t22). As a result, since the zero cross signal Sz becomes high level, the gate signal GL falls to low level, and the transistor N2 is forcibly turned off.

  When the second voltage Vb is reset to the lower end value at time t23, the second voltage Vb becomes lower than the first voltage Va again, so that the gate signal GH becomes high level and the gate signal GL becomes low level. Therefore, since the transistor N1 is turned on and the transistor N2 is turned off, the battery current I2 starts to increase again. At this time, the zero cross signal Sz falls to the low level.

  After time t23, similarly to the above, the battery current I2 excited in the coil L1 falls below the zero value during the ON period of the transistor N2 (time t24 to t26 and time t27 to t29) (time t25 and time t25). (See time t28). Each time the zero cross signal Sz rises to a high level, the forced stop of the switch output stage is repeated.

  Further, when the adapter current I1 continues to increase and the first voltage Va decreases to a voltage value lower than the lower end value of the second voltage Vb, the duty of the switch output stage becomes zero, and the charging operation from the adapter ADP to the battery 20 is stopped. (See after time t29).

  FIG. 10 is a timing chart showing a first example (low duty) of the discharge operation. In order from the top, the gate signals GH and GL, the battery current I2 (= battery discharge current I2d), the zero cross signal Sz, and the first voltage Va. (Small broken line) and the behavior of the second voltage Vb (solid line) are depicted. This figure corresponds to the operating state (c) in FIG. 7 (= around time t3).

  From time t30 to t31, the first voltage Va exceeds the upper end value of the second voltage Vb. Therefore, the duty of the switch output stage is zero, and the discharging operation from the battery 20 to the system SYS is stopped. At this time, since the zero cross signal Sz is maintained at the high level, the transistors N1 and N2 are both off.

  When the first voltage Va decreases and the second voltage Vb becomes higher than the first voltage Va at time t32, the gate signal GH becomes low level and the gate signal GL becomes high level. Accordingly, since the transistor N1 is turned off and the transistor N2 is turned on, the battery current I2 increases. At this time, the zero cross signal Sz falls to the low level.

  When the second voltage Vb is reset to the lower end value at time t33, the second voltage Vb becomes lower than the first voltage Va again, so that the gate signal GH becomes high level and the gate signal GL becomes low level. Therefore, since the transistor N1 is turned on and the transistor N2 is turned off, the battery current I2 starts to decrease again.

  Here, in the example of this figure, since the duty of the switch output stage is low, sufficient energy is not stored in the coil L1 during the ON period (time t32 to t33) of the transistor N2. Therefore, the battery current I2 excited by the coil L1 falls below the zero value during the ON period (time t33 to t35) of the transistor N1 (see time t34). As a result, since the zero cross signal Sz becomes high level, the gate signal GH falls to low level, and the transistor N1 is forcibly turned off.

  In addition, after time t35, the battery current I2 excited by the coil L1 falls below the zero value during the ON period of the transistor N1 as described above (see time t37). Each time the zero cross signal Sz rises to a high level, the forced stop of the switch output stage is repeated.

  FIG. 11 is a timing chart showing a second example (high duty) of the discharge operation. In order from the top, the gate signals GH and GL, the battery current I2 (= battery discharge current I2d), the zero cross signal Sz, and the first voltage Va. (Small broken line) and the behavior of the second voltage Vb (solid line) are depicted. This figure corresponds to the operating state (d) in FIG. 7 (= after time t3).

  From time t40 to t41, since the second voltage Vb is lower than the second voltage Va, the gate signal GH becomes high level and the gate signal GL becomes low level. Accordingly, since the transistor N1 is turned on and the transistor N2 is turned off, the battery current I1 is decreased.

  When the second voltage Vb becomes higher than the first voltage Va at time t41, the gate signal GH becomes low level and the gate signal GL becomes high level. Accordingly, the transistor N1 is turned off and the transistor N2 is turned on, so that the battery current I2 starts to increase.

  When the second voltage Vb is reset to the lower end value at time t42, the second voltage Vb becomes lower than the first voltage Va again, so that the gate signal GH becomes high level and the gate signal GL becomes low level. Therefore, since the transistor N1 is turned on and the transistor N2 is turned off, the battery current I2 starts to decrease again.

  Also after time t42, in the same manner as described above, the transistors N1 and N2 are repeatedly turned on and off, whereby the discharging operation of the battery 20 (= step-up operation of the switch output stage) is performed.

  In the example of this figure, the duty of the switch output stage is high, and sufficient energy is stored in the coil L1 during the ON period (time t41 to t42, time t43 to t44, time t45 to t46) of the transistor N2. . Therefore, the battery current I2 excited by the coil L1 does not fall below the zero value during the ON period (time t40 to t41, time t42 to t43, time t44 to t45) of the transistor N1. As a result, the zero cross signal Sz remains maintained at a low level.

<First Voltage Generation Circuit (Second Embodiment)>
FIG. 12 is a circuit diagram showing a second embodiment of the first voltage generation circuit 100. The first voltage generation circuit 100 of the present embodiment is characterized in that the first voltage adjustment unit 160 is further added while being based on the first embodiment (FIG. 6). Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 6, and redundant descriptions are omitted. In the following, the characteristic portions of the second embodiment are mainly described.

  The first voltage adjustment unit 160 includes npn-type bipolar transistors n3 to n5, pnp-type bipolar transistors p4 to p7, a current source CS3, and resistors Rx and Ry.

  The base of the transistor p4 is connected to the output terminal of the differential amplifier 112. The emitter of the transistor p4 is connected to the base of the transistor n3. The collector of the transistor p4 is connected to the ground terminal. The emitter of the transistor n3 is connected to the first end of the resistor Rx. A second end of the resistor Rx is connected to the ground end. The collector of the transistor n3 is connected to the collector of the transistor p5. Each emitter of the transistors p5 to p7 is connected to the internal power supply terminal. Each base of the transistors p5 to p7 is connected to the collector of the transistor p5. The collector of the transistor p6 is connected to the base of the transistor n2. The collector of the transistor p7 is connected to the collector of the transistor n4. Each base of the transistors n4 and n5 is connected to the collector of the transistor n4. Each emitter of the transistors n4 and n5 is connected to the ground terminal. The collector of the transistor n5 is connected to the output terminal of the first voltage Va. The current source CS3 is connected between the internal power supply terminal and the emitter of the transistor p4. The resistor Ry is connected between the emitter of the transistor n2 and the output terminal of the first voltage Va.

  When the battery discharge current I2d flows from the SRN pin to the SRP pin, the amplified voltage V112 corresponding to the current value is output. Here, a voltage equivalent to the amplified voltage V112 is applied to the resistor Rx via the transistors p4 and n3. Therefore, the adjustment current Ix (= V112 / Rx) corresponding to the amplified voltage V112 flows through the resistor Rx.

  The adjustment current Ix is caused to flow from the high potential side of the resistor Ry via the base of the transistor n2 by the first current mirror including the transistors p5 and p6. The adjustment current Ix is drawn to the constant potential side of the resistor Ry by the second current mirror composed of the transistors p5 and p7 and the third current mirror composed of the transistors n4 and n5.

  Therefore, a voltage drop ΔV (= Ix × Ry) corresponding to the adjustment current Ix is generated between both ends of the resistor Ry. That is, the first voltage Va output from the first voltage generation circuit 100 of the present embodiment is reduced by the above-described drop voltage ΔV compared to the first embodiment (FIG. 6).

  When battery discharge current I2d is not flowing, amplified voltage V112 has a zero value. Since the adjustment current Ix is also zero, the first voltage Va is not reduced.

  FIG. 13 is a timing chart showing the effect of improving the transient response in the second embodiment. In order from the top, the gate signals GH and GL, the battery current I2 (= battery discharge current I2d), the zero cross signal Sz, the first voltage. The behavior of Va (small broken line) and the second voltage Vb (solid line) is depicted. In this figure, as in the previous FIG. 10, the low duty state at the start of the discharge operation (boost operation) is depicted. Moreover, the thin broken line in this figure has shown the behavior (= behavior when not equipped with the 1st voltage adjustment part 160) of 1st Embodiment.

  In the example of this figure, since the duty of the switch output stage is low as in FIG. 10, the current discontinuous mode of the battery discharge current I2d occurs, and the forced stop of the switch output stage by the zero cross detection is repeated. .

  However, in the present embodiment, when the battery discharge current I2d starts to flow due to the function of the first voltage adjustment unit 160, the first voltage Va is reduced according to the current value. As a result, compared with the behavior of the first embodiment, the first voltage Va and the second voltage Vb can be crossed at an earlier timing, so that the ON period of the transistor N2 can be extended.

  That is, the semiconductor device 11 has a function of driving the switch output stage so as to promote the increase of the battery discharge current I2d when the battery 20 is discharged. If such a configuration is adopted, it is possible to increase the duty of the switch output stage quickly by increasing the decrease rate of the adapter current I1. Therefore, the current discontinuous mode of the battery discharge current I2d can be quickly eliminated, and the transient response when the system current I0 rapidly increases can be improved.

<Application to notebook computers>
FIG. 14 is an external view of the notebook computer X1. The notebook personal computer X1 is an example of an electronic device X on which the charge / discharge control device 10 is mounted. However, the charge / discharge control device 10 can be suitably mounted on other electronic devices.

<Other variations>
The various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. For example, mutual replacement of a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The charge / discharge control device disclosed in the present specification includes a mobile personal computer (Ultrabook PC, notebook PC, ultramobile PC, tablet PC, etc.), a mobile phone (including a smartphone), a digital still camera, and a digital video camera. It can be used for all electronic devices having a rechargeable battery, such as portable game machines.

10 Charge / Discharge Control Device 11 Semiconductor Device (Switch Drive Device)
20 battery 30 host 100 first voltage generation circuit 111-113 differential amplifier 121-124 error amplifier 130 voltage dividing unit 131, 132 resistor 140 first voltage generation unit 150 charge / discharge switching unit 151 comparator 152 logic unit 153 inverter 154 P channel Type MOS field effect transistor 160 first voltage adjustment unit 200 second voltage generation circuit 300 comparison circuit 400 drive circuit 410, 420 drive unit 430 control unit 500 internal power supply circuit 600 zero cross detection circuit N1 to N3 N channel type MOS field effect transistor L1 Coil C1, C2 Capacitor R1, R2 Sense resistor Rx, Ry Resistor D1 Diode n1-n5 npn-type bipolar transistor p1-p7 pnp-type bipolar transistor CS0-CS3 Current source A P adapter (power supply)
SYS system (load)
X Electronic device X1 Laptop

Claims (8)

A switch output stage connected between the power source and load and the battery;
When the current supply from the power source to the load is insufficient, the switch output stage is stepped down to charge the battery from the power source, and when the current supply from the power source to the load is insufficient, A switch driving device for boosting the switch output stage to discharge from the battery to the load;
Have
The switch driving device includes:
A first voltage generation circuit for generating a first voltage according to a charge / discharge state of the battery;
A second voltage generation circuit for generating a second voltage having a slope waveform;
A comparison circuit that compares the first voltage with the second voltage to generate a pulse width modulation signal;
A drive circuit for driving the switch output stage according to the pulse width modulation signal;
A zero-crossing detection circuit for forcibly stopping the switch output stage by detecting that the battery current flowing through the battery has reached zero value;
Including
The first voltage generation circuit adjusts the first voltage according to a current value when the battery current starts to flow from the battery to the load when the battery is discharged, and the first voltage and the first voltage A charge / discharge control apparatus characterized by rapidly increasing the duty of the switch output stage by crossing two voltages at an earlier timing .   The switch drive device drives the switch output stage so that an input current supplied from the power source does not exceed an upper limit value when the battery is charged or discharged. Charge-discharge control apparatus as described in.   3. The switch output device according to claim 1, wherein the switch driving device drives the switch output stage so that a battery current flowing from the battery to the load does not exceed an upper limit value when the battery is discharged. The charging / discharging control apparatus of description.   The switch drive device drives the switch output stage so that a battery current flowing from the power source to the battery does not exceed an upper limit value when the battery is charged. The charge / discharge control apparatus as described in any one of Claims.   The said switch drive device drives the said switch output stage so that a battery voltage may not exceed an upper limit at the time of charge of the said battery, The Claim 1 characterized by the above-mentioned. Charge / discharge control device.   6. The switch driving device outputs an actual measured value of an input current supplied from the power source or an actual measured value of a battery current flowing from the battery to the load to the outside of the device. The charge / discharge control apparatus according to any one of the above. The switch output stage is
A half-bridge output circuit comprising a pair of upper and lower switch elements connected in series between the power source and the ground terminal;
An LC filter circuit connected between the half-bridge output circuit and the battery;
The charge / discharge control apparatus according to any one of claims 1 to 6 , further comprising: The charge / discharge control apparatus according to any one of claims 1 to 7 ,
A battery charged and discharged by the charge / discharge control device;
An electronic device comprising:

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