(發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式_說明) 一、發明所屬之技術領域 本發明係關於一種低電壓直流轉換器（DC-DC Converter)，尤指一種利用高準位觸發開關及低準位觸 發開關作為切換開關之多輸出直流轉換器。 二、先前技術 隨著電子產業之發達，消費型電子產品越來越普 及，尤其是目前最流行的可攜式電子產品（例如：數位 相機或數位攝影機（DV) >，通常這類電子產品在操作 時需要多種不同的電源，例如：隨機存取記憶體（RAM) 之操作電壓為2.5伏，微處理器之操作電壓為1.2伏〜1.8 伏，類比電路或萬用串列匯流排（USB )介面使用電壓 為5伏，這類電子產品通常亦需要不同的電壓來驅動各種 類型的小馬達（例如：數位相機的變焦鏡頭馬達或數位 攝影機中卡式錄放影機（VCR )部分的磁帶機馬達）。 目前的可攜式電子產品主要採用電池組來提供電 源，最常使用的電池即為鋰離子（LI)電池，其提供的 電壓範圍約為2.7伏〜4.2伏。當然，鋰離子電池亦可被2 組（2-Cell)的鹼性電池取代，係因為鹼性電池可提供2 伏〜5伏的輸入電壓。若上述可攜式電子產品利用具有輸 入電壓範圍廣之電池作為系統之輸入電壓，以作為各個 使用不同操作電壓之子系統的輸入電壓，則必須在此類 產品中設計一完整的電源糸統’亦即該完整的電源系統 必須包含複數個直流轉換器，以將電施電壓轉換為各個《 子系統所需要的操作電壓。 傳統的直流轉換器係利用切換式穩壓器來產生所需 要的轉換電壓。以壓降式轉換器（Step_DoWn converter) 為例，其所包含之電晶體開關係為互補對（例如：；^型 與P型金屬氧化半導體場效電晶體（MOSFET))。圖1 顯示降壓轉換器（Buck Converter )利用P型MOSFET12 作為高準位觸發開關以及利用N型M0SFET13作為低準 位觸發開關。 輸入電壓11端與P型M0SFET12之源極端相連接，輸 入電壓11用以提供操作電壓（VDD)給内部控制電路1〇， 内部控制電路10包含高準位開關驅動器14、低準位開關 驅動器15、下降時間（Tf)延遲電路16、上升時間（Tr) 延遲電路17、RS正反器18、能隙參考電壓源19、時脈及 斜波信號產生器20、比較器21以及誤差放大器23,其中， 此内部控制電路10可被封裝於一晶片中，以成為直流轉 換器。 誤差放大器23之一端連接至能隙參考電壓源19之輸 出端，誤差放大器23之另一端連接至輸出電壓26端。誤 差放大器23之輸出端與比較器21之反相輸入端相連接， 比較器21之正相輸入端與時脈及斜波信號產生器2〇之輸 出端相連接。時脈及斜波信號產生器20除了控制比較器 21之外，亦控制RS正反器18之動作。比較器21之輸出端 連接至RS正反器18之重置（Reset)端。RS正反器18之反 200427193 相輸出端（Qn端）分別連接至下降時間延遲電路16與上· 升時間延遲電路17。 下降時間延遲電路16與上升時間延遲電路17之輸出 端分別連接至高準位開關驅動器14之輸入端與低準位開 關驅動器15之輸入端。高準位開關驅動器14用以驅動P型 MOSFET12之閘極，低準位開關驅動器15用驅動N型 MOSFET13之閘極。在卩型MOSFET12與N型MOSFET13連 接處，係連接至所封裝之晶片的LX接腳，俾供藉由LX接 腳連接至一外部儲能電感25之其中一節點，以透過電感 25提供輸出電壓26。當然，通常在輸出電壓26端之前， 會利用一濾波電容27來進行濾波處理。 内部控制電路10中之該等元件的動作如下所述，當 高準位開關驅動器14係使得PSMOSFET12之閘極電位為 接地電位（低電位），且提供等於輸入電壓11之源閘極 電壓（VSG)，則P型MOSFET12導通。當高準位開關驅 動器14係使得？型旭08卩£丁12之閘極電位為接近輸入電壓 11 (高電位），且提供約等於零伏之源閘極電壓，則P型 MOSFET12關閉。 相同地，當低準位開關驅動器15使得N型MOSFET13 之閘極電位為操作電壓，且提供約等於輸入電壓11之閘 源極電壓（VGS)，則N型MOSFET13導通。當低準位開 關驅動器15使得N型MOSFET13之閘極電位為接地電 位，且提供約等於零伏之閘源極電壓，則N型MOSFET13 關閉。 下降時間延遲電路16與上升時間延遲電路17提供P " 型M0SFET12與N型M0SFET13反穿鑿 (Anti_Shoot-Through )保護。在低準位開關驅動器15關 閉N型MOSFET13與高準位開關驅動器14導通P型 M0SFET12期間，下降時間延遲電路16提供一極短的下緣 延遲（約50奈秒）。在高準位開關驅動器14關閉P型 MOSFET12與低準位開關驅動器15導通>1型]\108?丑丁13其 間，上升時間延遲電路17提供一極短的上緣延遲（約50 奈秒）。 然而，使用P型MOSFET12作為切換開關會產生一些 缺點，P型MOSFET12與N型MOSFET13在相同尺寸（W/L) 下，P型MOSFET12之導通電阻（rDS)比N型MOSFET13 之導通電阻高，係因在通道中P型MOSFET12之載子移動 率比N型MOSFET13之載子移動率低。 由於MOSFET之導通電阻會降低電源轉換效率，且 會在MOSFET中產生熱損失。又，當電池所提供之輸入電 壓低於2.5伏時，因高準位觸發P型MOSFET12需要3伏〜5 伏的操作電壓，因此將非常困難導通P型MOSFET12。故， 若使用P型MOSFET12作為高準位觸發開關，必將限制傳 統壓降式轉換器3伏〜5伏的操作範圍。 目前亦有一些利用N型MOSFET作為高準位處發開 關與低準位觸發開關之壓降式轉換器，其係利用靴帶電 路（Bootstrap Circuit)來提供電源給高準位開關驅動器。 此種靴帶電路允許使用N型MOSFET作為高準位觸發開 關，但當輸入電壓過低時（例如：2伏），則勒:帶電壓將 低到1·5伏而無法完全地導通高準位觸發開關。下述將詳' 加解說此類型之壓降式轉換器的動作。 圖2顯示Ν型MOSFET32,33作為高準位觸發開關與 低準位觸發開關之降壓穩壓器示意圖，其内部控制電路 30係封裝於一晶片中，靴帶電路包則在晶片外增加，靴 帶電路包括二極體28與電容29,其係串聯於輸入電壓31 與晶片之LX接腳。在二極體28與電容29之間的節點係與 晶片之BST接腳相連接，以提供N型MOSFET32所需之高 電壓（閘源極電壓）。高準位開關驅動器34之接地腳位 (VSS)貝1J連接至晶片之LX接腳。 降壓穩壓器之動作如下所述，在低準位觸發開關33 導通期間，晶片之LX接腳的電位為接地電位。電容29並 藉由二極體28充電至輸入電壓（+VIN)，其中，二極體 28之正端連接至輸入電壓31端。當高準位開關驅動器34(Explanation of the invention should state: the technical field, prior art, content, embodiments and drawings_description of the invention) 1. Technical field to which the invention belongs The present invention relates to a low-voltage DC converter (DC-DC Converter), In particular, a multi-output DC converter using a high-level trigger switch and a low-level trigger switch as a switching switch. 2. Previous technologies With the development of the electronics industry, consumer electronics are becoming more and more popular, especially the most popular portable electronic products (such as digital cameras or digital video cameras (DV) >), which are usually such electronic products. A variety of different power sources are required for operation, for example: the operating voltage of random access memory (RAM) is 2.5 volts, the operating voltage of microprocessors is 1.2 volts to 1.8 volts, analog circuits or universal serial buses (USB The interface uses a voltage of 5 volts. This type of electronic products usually also needs different voltages to drive various types of small motors (for example: zoom lens motors for digital cameras or tape drives for cassette recorders (VCR) in digital cameras). Motor). Current portable electronic products mainly use battery packs to provide power. The most commonly used battery is a lithium ion (LI) battery, which provides a voltage range of about 2.7 volts to 4.2 volts. Of course, lithium ion batteries Can also be replaced by 2 (2-Cell) alkaline batteries, because alkaline batteries can provide an input voltage of 2 volts to 5 volts. If the above-mentioned portable electronic products use A battery with a wide range of input voltages is used as the input voltage of the system as the input voltage of each subsystem using different operating voltages. A complete power supply system must be designed in such products, that is, the complete power supply system must include a plurality of A DC converter to convert the applied voltage to the operating voltage required by each subsystem. The traditional DC converter uses a switching regulator to generate the required conversion voltage. A step-down converter (Step_DoWn converter) as an example, the transistor contains a complementary pair (for example: ^ and P-type metal oxide semiconductor field-effect transistor (MOSFET)). Figure 1 shows that Buck Converter uses P The type MOSFET12 is used as a high level trigger switch and the N type M0SFET13 is used as a low level trigger switch. The input voltage 11 terminal is connected to the source terminal of the P type M0SFET12, and the input voltage 11 is used to provide an operating voltage (VDD) to the internal control circuit 1 〇, the internal control circuit 10 includes a high-level switch driver 14, a low-level switch driver 15, a fall time (Tf) delay circuit 16, and Time (Tr) delay circuit 17, RS flip-flop 18, bandgap reference voltage source 19, clock and ramp signal generator 20, comparator 21, and error amplifier 23, where the internal control circuit 10 can be packaged in In one chip, it becomes a DC converter. One end of the error amplifier 23 is connected to the output of the energy gap reference voltage source 19, and the other end of the error amplifier 23 is connected to the output voltage 26. The output of the error amplifier 23 and the comparator 21 The inverting input of the comparator 21 is connected, and the non-inverting input of the comparator 21 is connected to the output of the clock and ramp signal generator 20. The clock and ramp signal generator 20, in addition to controlling the comparator 21, The operation of the RS flip-flop 18 is also controlled. The output terminal of the comparator 21 is connected to the reset terminal of the RS flip-flop 18. The reverse of the RS flip-flop 18, 200427193 phase output terminal (Qn terminal) is connected to the fall time delay circuit 16 and the rise time delay circuit 17, respectively. The output terminals of the falling time delay circuit 16 and the rising time delay circuit 17 are connected to the input terminal of the high level switch driver 14 and the input terminal of the low level switch driver 15 respectively. The high-level switch driver 14 is used to drive the gate of the P-type MOSFET 12, and the low-level switch driver 15 is used to drive the gate of the N-type MOSFET 13. The connection between the 卩 -type MOSFET 12 and the N-type MOSFET 13 is connected to the LX pin of the packaged chip. The LX pin is connected to one of the nodes of an external energy storage inductor 25 through the LX pin to provide an output voltage through the inductor 25. 26. Of course, before the output voltage 26, a filtering capacitor 27 is usually used for filtering. The operations of these components in the internal control circuit 10 are described below. When the high-level switch driver 14 is such that the gate potential of the PSMOSFET 12 is a ground potential (low potential), and a source gate voltage (VSG) equal to the input voltage 11 is provided. ), The P-type MOSFET 12 is turned on. When the high level switch driver 14 is made? The gate potential of the type Asahi 08 卩 12 is close to the input voltage 11 (high potential) and provides a source gate voltage equal to about zero volts, then the P-type MOSFET12 is turned off. Similarly, when the low-level switch driver 15 causes the gate potential of the N-type MOSFET 13 to be an operating voltage and provides a gate-source voltage (VGS) approximately equal to the input voltage 11, the N-type MOSFET 13 is turned on. When the low-level switch driver 15 makes the gate potential of the N-type MOSFET 13 to the ground potential and provides a gate-source voltage equal to approximately zero volts, the N-type MOSFET 13 is turned off. The fall-time delay circuit 16 and the rise-time delay circuit 17 provide Anti-Shoot-Through protection of the P " type M0SFET12 and N-type M0SFET13. During the period when the low-level switch driver 15 turns off the N-type MOSFET 13 and the high-level switch driver 14 turns on the P-type MOSFET 12, the fall time delay circuit 16 provides a very short lower edge delay (about 50 nanoseconds). While the high-level switch driver 14 turns off the P-type MOSFET 12 and the low-level switch driver 15 turns on > type 1] \ 108? Ugding 13, the rise time delay circuit 17 provides a very short upper edge delay (about 50 nanoseconds) ). However, the use of P-type MOSFET12 as a switch has some disadvantages. P-type MOSFET12 and N-type MOSFET13 have the same on-resistance (rDS) than N-type MOSFET13 at the same size (W / L). Because the carrier mobility of the P-type MOSFET 12 in the channel is lower than the carrier mobility of the N-type MOSFET 13. Due to the on-resistance of the MOSFET, power conversion efficiency is reduced, and heat loss is generated in the MOSFET. In addition, when the input voltage provided by the battery is lower than 2.5 volts, it will be very difficult to turn on the P-type MOSFET 12 because the high-level triggering of the P-type MOSFET 12 requires an operating voltage of 3 volts to 5 volts. Therefore, if the P-type MOSFET12 is used as a high-level trigger switch, the operating range of the conventional voltage drop converter from 3V to 5V will be limited. At present, there are also some voltage drop converters that use N-type MOSFETs as high-level position switches and low-level trigger switches. They use a bootstrap circuit to provide power to high-level switch drivers. This type of shoelace circuit allows the use of N-type MOSFETs as high-level trigger switches, but when the input voltage is too low (for example: 2 volts), the band voltage will be as low as 1.5 volts and cannot fully turn on Micro Motion Bit trigger switch. The following will explain in detail the operation of this type of voltage drop converter. Figure 2 shows the schematic diagram of N-type MOSFETs 32 and 33 as step-down regulators for high-level trigger switches and low-level trigger switches. The internal control circuit 30 is packaged in a chip, and the bootband circuit package is added outside the chip. The shoelace circuit includes a diode 28 and a capacitor 29, which are connected in series with the input voltage 31 and the LX pin of the chip. The node between the diode 28 and the capacitor 29 is connected to the BST pin of the chip to provide the high voltage (gate-source voltage) required by the N-type MOSFET 32. The ground pin (VSS) of the high level switch driver 34 is connected to the LX pin of the chip. The operation of the step-down regulator is as follows. During the on-time of the low-level trigger switch 33, the potential of the LX pin of the chip is the ground potential. The capacitor 29 is charged to the input voltage (+ VIN) through the diode 28, wherein the positive terminal of the diode 28 is connected to the input voltage 31. When the high level switch driver 34
導通N型MOSFET32 (高準位觸發開關）時，晶片之LX 接腳將藉由N型MOSFET32之通道與輸入電壓31端相連 接’以使得晶片之LX接腳電壓與晶片之bSt接腳最後能 升南至幾乎等於二倍的輸入電壓（2 VIN)，俾供透過高 準位開關驅動器34與高準位觸發開關32之閘源極電壓 (約等於輸入電壓VIN)，以足夠的電壓導通]^型 MOSFET32 〇 上升時間延遲電路36,37用以提供N型MOSFET32 (高準位觸發開關）與N型MOSFET 33(低準位觸發開關） 反穿鑿保護，且上升時間延遲電路36,37並提供一極短上 緣延遲（約50奈秒）。 200427193 、 圖3顯示圖1之降壓穩壓器在穩定狀態期間的主要波》 形示意圖，時脈及斜波信號產生器2〇提供固定頻率之脈 衝時脈信號至RS正反器18之設定端（Set)。每一脈衝信 號Ik著斜波信號（即三角波信號）產生，亦即每一斜波 信號結束時將產生一個脈衝信號。時脈及斜波信號產生 器20所產生之每一脈衝信號觸發RS正反器18之設定端， 俾供RS正反器18之閃鎖電路輸出端（q)輸出高位邏輯 狀態。 當RS正反器18轉態，以使得其反相輸出端（Qn)輸 出低位邏輯狀態，則高準位開關驅動器15即時關閉 MOSFET13(低準位觸發開關）。經過一短暫的下緣延 遲時間（約50奈秒）後，高準位開關驅動器14將使得p型 MOSFET 12(高準位觸發開關）之閘極端電位為低電位， 俾供P型]V10SFET12。前述之動作，P型MOSFET12與N型 MOSFET13動作之間係利用一關閉後再導通之方式來達 成。 誤差放大器23之誤差放大電壓（VERR) 22將隨著所 輸入之電壓差而不同，亦即只有在輸出電壓26與能隙參 考電壓源19所提供之參考電壓（REF) 24不同時，誤差放 大器23才會輸出誤差放大電壓22。若誤差放大電壓22小 於參考電壓24時，則誤差放大器23之誤差放大電壓22係 為微小的正誤差電壓。 當另一新的切換週期開始時，時脈及斜波信號產生 為20產生固定斜率之斜波信號。當斜波信號之值小於誤 差放大器23之輸出電壓，則比較器21之輸出為低位邏輯 11 200427193 狀態且RS正反器18仍保持為設定（Set)狀態，並使得N« 型MOSFET 12導通，以對電感器25進行充電。 當斜波信號之值（大小）高於誤差放大器23之誤差 放大電壓22，則比較器21之輸出為高位邏輯狀態，以重 置RS正反器’俾供rs正反器is之反相輸出端（Qn)切換 其輸出’以輸出高位邏輯信號至高準位開關驅動器14。 此時’高準位開關驅動器14將使得1>型]^〇|517]5丁12之閘極 端的輸出轉變為高電位，以即時關閉卩型MOSFET12。 經過一短暫的上緣延遲時間後，高準位開關驅動器 15將使得N型MOSFET13之閘極端的電位為高電位，以導 通N型MOSFET13。其係再次利用一關閉後再導通之方式 來達成P型MOSFET12之關閉與導通n型MOSFET13。此 ¥ ’晶片之LX接腳成為低電位（因為n型MOSFET13導 通），以使得電感器25開始對負載端提供電流。 在穩定狀態期間’工作週期（D )(即p型MOSFET12 開始導通之時）係和輸入電壓（VIN ) 11與輸出電壓（VO ) 26之比值有關，其係可用一公式來表示：When the N-type MOSFET32 (high-level trigger switch) is turned on, the LX pin of the chip will be connected to the input voltage 31 terminal through the channel of the N-type MOSFET32, so that the voltage of the LX pin of the chip and the bSt pin of the chip can finally Rise south to almost double the input voltage (2 VIN), and supply the gate-source voltage (approximately equal to the input voltage VIN) through the high-level switch driver 34 and high-level trigger switch 32 (conducting with sufficient voltage) ^ Type MOSFET32 〇 Rise time delay circuits 36, 37 are used to provide N-type MOSFET32 (high-level trigger switch) and N-type MOSFET 33 (low-level trigger switch) anti-punch-through protection, and the rise time delay circuits 36, 37 provide A very short upper edge delay (about 50 nanoseconds). 200427193 、 Figure 3 shows the main wave of the buck regulator during steady state in Figure 1. Schematic diagram, clock and ramp signal generator 20 provides fixed frequency pulse clock signal to the setting of RS flip-flop 18 (Set). Each pulse signal Ik is generated with a ramp signal (ie, a triangular wave signal), that is, a pulse signal is generated at the end of each ramp signal. Each pulse signal generated by the clock and ramp signal generator 20 triggers the setting terminal of the RS flip-flop 18, and is used for the high-end logic state of the output terminal (q) of the flash lock circuit of the RS flip-flop 18. When the RS flip-flop 18 changes state so that its inverting output (Qn) outputs a low-level logic state, the high-level switch driver 15 immediately turns off the MOSFET 13 (low-level trigger switch). After a short lower edge delay time (approximately 50 nanoseconds), the high-level switch driver 14 will cause the gate extreme potential of the p-type MOSFET 12 (high-level trigger switch) to be a low potential for P-type] V10SFET12. The foregoing actions are achieved by turning off and then turning on the P-type MOSFET 12 and the N-type MOSFET 13. The error amplifier voltage (VERR) 22 of the error amplifier 23 will vary with the input voltage difference, that is, the error amplifier will only differ when the output voltage 26 and the reference voltage (REF) 24 provided by the energy gap reference voltage source 19 are different. 23 will output error amplification voltage 22. If the error amplification voltage 22 is smaller than the reference voltage 24, the error amplification voltage 22 of the error amplifier 23 is a small positive error voltage. When another new switching cycle is started, the clock and ramp signals are generated to generate a ramp signal with a fixed slope of 20. When the value of the ramp signal is less than the output voltage of the error amplifier 23, the output of the comparator 21 is in the low logic state 11 200427193 state and the RS flip-flop 18 remains in the set state, and the N «-type MOSFET 12 is turned on. To charge the inductor 25. When the value (magnitude) of the ramp signal is higher than the error amplification voltage 22 of the error amplifier 23, the output of the comparator 21 is in a high logic state to reset the RS flip-flop '俾 for the inverted output of the rs flip-flop is The terminal (Qn) switches its output to output a high-level logic signal to the high-level switch driver 14. At this time, the 'high-level switch driver 14 will make the output of the gate terminal of the 1 > type] ^ 0 | 517] 5 to 12 high to turn off the 卩 -type MOSFET 12 immediately. After a short upper edge delay time, the high-level switch driver 15 will make the potential of the gate terminal of the N-type MOSFET 13 high to turn on the N-type MOSFET 13. This is to turn off the P-MOSFET 12 and turn on the n-MOSFET 13 again by turning it off and then on again. The LX pin of this ¥ ′ chip becomes a low potential (because the n-type MOSFET 13 is turned on), so that the inductor 25 starts to supply current to the load terminal. During the steady state period, the duty cycle (D) (that is, when the p-type MOSFET 12 starts to conduct) is related to the ratio between the input voltage (VIN) 11 and the output voltage (VO) 26, which can be expressed by a formula:
D = VO/VIN 在圖1中的電路存在一回饋迴圈（Feedback Loop ) 關係，其係表示輸入電壓與輸出電壓之差異，並透過調 整工作週期（D)來使得輸出電壓26與參考電壓（REF) 接近。例如：在圖3中的T1時間點，假設輸入電壓丨1比先 前的電壓稍微降低，則輸出電壓26將依據上述之公式而 相對地降低。誤差放大器23在感測到輸出電壓26降低 後，誤差放大器23將增加其誤差放大電壓22。高的誤差 12 200427193 放大電壓22將產生一較好的工作週期，係因為其將取得” 較高的斜波信號之值，以獲得較高準位的誤差^大電壓 22。 在圖3中的T2與T3時間點，其工作週期之導通脈衝寬 度係比P型M0SFET12導通的時間長。當工作週期增加， 則輸出電壓26將隨之增加，誤差放大電壓22將逐漸減 少。由於誤差放大器23具有非常高的直流增益，因此誤 差放大器23之輸出最後將恢復為能隙參考電壓源丨9之輸 出。在另一新的穩定狀態週期中（例如：T5與T6時間點）， 其工作週期係比先A之工作週期長，此電路將調整為較 低的輸入電壓。 因此，如何提供較高轉換效率與輸入電壓範圍廣之 電源轉換裝置，已成為一亟需解決之課題。 三、發明内容 本發明之一目的係在提供一種多輸出直流轉換器， 俾能簡化開關驅動器之設計。 本發明之另一目的係在提供一種多輸出直流轉換 器’俾能提高電源轉換之效率。 本發明之又一目的係在提供一種多輸出直流轉換 器’俾能消除所使用之電源金氧半MOSFET之體積大小因 為達成上述目的，本發明多輸出直流轉換器主要包 括：一電源轉換電路，係接收一輸入電壓，並依據該輸 入電壓產生一第一調節電壓；一電荷倍增電路，係接收 13 200427193 該第一調節電壓，以I生一第二調節電壓；以及複數電-壓輸出電路，每一電壓輸出電路更包括一第一開關驅動 器、一第二開關驅動器、一第一電源切換開關以及一第 二電源切換開關，其中，該第一開關驅動器與該第二開 關驅動器分別接收該第一調節電壓與該第二調節電壓， 俾供藉由該第一調節電壓來控制該第一電源切換開關， 藉由該第二調節電壓來控制該第二電源切換開關，以輸 出複數輸出電壓。 四、實施方式 圖4顯示本發明之較佳實施例之電路示意圖，其主要 包含開關驅動器電源電路40以及複數個降壓穩壓器或升 壓轉換器，於本實施例中，係列舉第一降壓穩壓器7〇與 第二降壓穩壓器80來加以說明。開關驅動器電源電路40 包含升壓穩壓器（Boost Regulator ) 50與電荷倍增電路60 (即切換式電容電路），以分別提供一低準位電壓 (VDDL) 41 (例如：4伏〜5伏）與一高準位電壓（VDDH) 42 (例如：8伏〜1〇伏）。低準位電壓41與高準位電壓42 係用來推動多輸出直流轉換器中，作為高準位觸發開關 與低準位觸發開關之nsmosfet。 第一降壓穩壓器70具有一 N型M0SFET71、N型 MOSFET72以及控制邏輯單元75，其中，N型M0SFET71 作為高準位觸發開關，N型MOSFET72作為低準位觸發開 關。咼準位開關驅動器73依據電荷倍增電路60所提供之 高準位電壓42以及控制邏輯單元75之輸出來動作，低準D = VO / VIN The circuit in Figure 1 has a Feedback Loop relationship, which indicates the difference between the input voltage and the output voltage, and adjusts the duty cycle (D) to make the output voltage 26 and the reference voltage ( REF) close. For example, at time T1 in FIG. 3, assuming that the input voltage 丨 1 is slightly lower than the previous voltage, the output voltage 26 will be relatively reduced according to the above formula. After the error amplifier 23 senses a decrease in the output voltage 26, the error amplifier 23 will increase its error amplification voltage 22. High error 12 200427193 Amplifying the voltage 22 will produce a better duty cycle because it will obtain a "higher value of the ramp wave signal to obtain a higher level of error ^ large voltage 22." in Figure 3 At T2 and T3, the on-pulse width of the duty cycle is longer than the on-time of the P-type MOSFET 12. When the duty cycle increases, the output voltage 26 will increase and the error amplifier voltage 22 will gradually decrease. Since the error amplifier 23 has Very high DC gain, so the output of the error amplifier 23 will eventually return to the output of the bandgap reference voltage source 丨 9. In another new steady state period (for example: T5 and T6 time points), the duty cycle ratio is First, the working cycle of A is long, and this circuit will be adjusted to a lower input voltage. Therefore, how to provide a power conversion device with higher conversion efficiency and a wide input voltage range has become an urgent problem. III. SUMMARY OF THE INVENTION One object of the invention is to provide a multi-output DC converter, which can simplify the design of a switching driver. Another object of the present invention is to provide a multi-output DC converter. The converter 'can improve the efficiency of power conversion. Another object of the present invention is to provide a multi-output DC converter' which can eliminate the size of the power metal-oxide-semiconductor MOSFET used. Because the above purpose is achieved, the present invention has multiple outputs The DC converter mainly includes: a power conversion circuit that receives an input voltage and generates a first regulated voltage based on the input voltage; a charge multiplying circuit that receives 13 200427193 the first regulated voltage and generates a second by 1 Voltage regulation; and a plurality of electric-voltage output circuits, each voltage output circuit further includes a first switch driver, a second switch driver, a first power switch, and a second power switch, wherein the first switch The driver and the second switch driver receive the first regulated voltage and the second regulated voltage, respectively, to control the first power switching switch by the first regulated voltage, and control the first regulated voltage by the second regulated voltage. Two power-supply switching switches for outputting a plurality of output voltages. Fourth Embodiment FIG. 4 shows a preferred implementation of the present invention. The schematic circuit diagram mainly includes a switching driver power circuit 40 and a plurality of buck regulators or boost converters. In this embodiment, a series of first buck regulators 70 and second buck regulators are provided. The switch driver power circuit 40 includes a boost regulator (Boost Regulator) 50 and a charge multiplication circuit 60 (ie, a switched capacitor circuit) to provide a low level voltage (VDDL) 41 (for example: 4 volts to 5 volts) and a high-level voltage (VDDH) 42 (for example: 8 volts to 10 volts). The low-level voltage 41 and the high-level voltage 42 are used to drive a multi-output DC converter as The nsmosfet of the high-level trigger switch and the low-level trigger switch. The first buck regulator 70 has an N-type M0SFET71, an N-type MOSFET72, and a control logic unit 75, where the N-type M0SFET71 is used as a high-level trigger switch, N The type MOSFET 72 functions as a low level trigger switch.咼 The level switch driver 73 operates according to the high level voltage 42 provided by the charge multiplying circuit 60 and the output of the control logic unit 75, and the low level
14 200427193 位開關驅動器74依據升壓穩壓器50所提供之低準位電壓， 41以及控制邏輯單元75之輸出來動作，俾供分別控制n型 MOSFET71與72之動作，以提供輸出電壓76。有關如何利 用高準位觸發開關與低準位觸發開關之動作來提供輸出 電壓76,86，可參照習知圖1之動作說明。 第二降壓穩壓器80與第一降壓穩壓器70所包含之元 件類似，其係包含NSM0SFET 81 (作為高準位觸發開 關）、N型MOSFET 82 (作為低準位觸發開關）以及控制 邏輯單元85，高準位開關驅動器83依據高準位電壓42與 控制邏輯單元85之輸出來動作，低準位開關驅動器84依 據低準位電壓41與控制邏輯單元85之輸出來動作，俾供 分別控制N型MOSFET81與82之動作，以提供輸出電壓 86 ° 圖5顯示本發明較佳實施例之詳細電路示意圖，在圖 4中所顯不之升壓穩壓器50更包含輸入端電感51、蕭特基 —極體52、濾波電容53、N型MOSFET54、低準位開關驅 動器55、脈寬調變（pwm)控制電路56、比較器57、誤 差放大器58以及能隙參考電壓源59。輸入端電感51分別 連接輸入電壓端與蕭特基二極體52 (整流二極體）之一 端’蕭特基二極體52之另一端則與濾波電容53相連接。 誤差放大器58之輸入端分別連接參考電壓源（例 如· 2.5伏）與電壓感測電路（亦即分壓電路），俾供依 據電壓感测電路之分壓與參考電壓的差異值來進行放 大’以輸出一誤差放大電壓。比較器57具有一正相輸入 螭與一反相輸入端，正相輸入端接收一斜波信號，反相 15 200427193 輸入端接收誤差放大電壓，俾供比較器57對斜波信被與β 誤差放大電壓進行比較處理，以輸出一比較結果。脈寬 調變控制電路56並接收比較結果，且依據比較結果產生 一脈寬調變信號，俾供透過脈衝信號控制N型MOSFET54 之導通與關閉。 脈寬調變控制電路56在低準位電壓41 (1.5伏〜5伏） 時，具有啟動與產生脈寬調變信號至N型MOSFET54之能14 200427193 The bit switch driver 74 operates according to the low level voltage provided by the boost regulator 50, 41 and the output of the control logic unit 75, and is used to control the operations of the n-type MOSFETs 71 and 72 to provide the output voltage 76. For how to use the actions of the high-level trigger switch and the low-level trigger switch to provide the output voltages 76, 86, please refer to the conventional operation description in Figure 1. The second buck regulator 80 is similar to the components included in the first buck regulator 70. It includes NSM0SFET 81 (as a high-level trigger switch), N-type MOSFET 82 (as a low-level trigger switch), and The control logic unit 85, the high-level switch driver 83 operates according to the high-level voltage 42 and the output of the control logic unit 85, and the low-level switch driver 84 operates according to the low-level voltage 41 and the output of the control logic unit 85. For controlling the actions of N-type MOSFETs 81 and 82 to provide an output voltage of 86 °. Figure 5 shows a detailed circuit diagram of the preferred embodiment of the present invention. The boost regulator 50 shown in Figure 4 further includes an input inductor. 51. Schottky-pole body 52, filter capacitor 53, N-type MOSFET 54, low-level switch driver 55, pulse width modulation (pwm) control circuit 56, comparator 57, error amplifier 58, and bandgap reference voltage source 59 . The input terminal inductor 51 is respectively connected to the input voltage terminal and one terminal of the Schottky diode 52 (rectifying diode). The other terminal of the Schottky diode 52 is connected to the filter capacitor 53. The input terminal of the error amplifier 58 is respectively connected to a reference voltage source (for example, 2.5 volts) and a voltage sensing circuit (ie, a voltage dividing circuit), and is provided for amplification according to the difference between the voltage dividing voltage of the voltage sensing circuit and the reference voltage. 'To output an error amplified voltage. Comparator 57 has a non-inverting input 螭 and an inverting input. The non-inverting input receives a ramp signal, and the inverting 15 200427193 input receives the error amplification voltage. It is used by comparator 57 for the error of the ramp signal and β error. The voltage is amplified for comparison processing to output a comparison result. The pulse width modulation control circuit 56 receives the comparison result, and generates a pulse width modulation signal based on the comparison result, which is used to control the on and off of the N-type MOSFET 54 through the pulse signal. The pulse width modulation control circuit 56 has the ability to start and generate a pulse width modulation signal to the N-type MOSFET 54 at a low level voltage 41 (1.5 volts to 5 volts).
力，其中，N型MOSFET54在此係為一切換開關。當然， 在第一降壓穩壓器70、第二降壓穩壓器80以及升壓穩壓 器90之脈寬調變控制電路所產生之脈寬調變信號，亦用 來控制其高準位開關驅動器與低準位開關驅動器，以驅 動高準位觸發開關與低準位觸發開關之動作。In this case, the N-type MOSFET 54 is a switch. Of course, the pulse width modulation signals generated by the pulse width modulation control circuits of the first buck regulator 70, the second buck regulator 80, and the boost regulator 90 are also used to control the Micro Motion Position switch driver and low level switch driver are used to drive the action of high level trigger switch and low level trigger switch.
在啟始相位期間，低準位電壓41若為1.6伏，由於n 型MOSFET54具有較低的臨界電壓（vtn)，因此可以導 通N型MOSFET54。當升壓穩壓器5〇動作，低準位電壓4] 逐漸升起，直到升至4伏〜5伏為止。低準位電壓41亦可作 為内部電路之其他邏輯元件的操作電壓，例如：低準位 =關驅動器55在穩態期間係提供約4伏〜地的閘源極電 = _M〇SF則。其中，低 基二極體52之輸出端所提供。 電荷倍增電路61更包含内部切換矩陣、儲存電容62 =輸出電容63。儲存電容62週期性地被充電，並輸出 其所儲存之電荷至輸出電容63,俾供輸出高準位電壓 42’且該高準位電壓42幾乎等於2倍的低準位電壓 200427193 關電荷倍增電路60之詳細動作及其設計，可參照英特矽· 爾（Intersil)之產品ICL7660A的技術資料。 低準位電壓41與高準位電壓42除了提供給第一降壓 穩壓器70與第二降壓穩壓器80,亦可提供其他直流轉換 器使用（例如：升壓穩壓器90)，即其他直流轉換器所 包含的高準位與低準位閘驅動器皆與開關驅動器電源電 路40與電荷倍增電路60相連接，以接收低準位電壓41與 南準位電壓42，俾供閘驅動器能夠依據低準位電壓41與 高準位電壓42來切換MOSFET。 升壓穩麼器90包含N型MOSFET93、N型MOSFET92 以及輸入端電感91，其中，N型MOSFET93作為低準位觸 發開關，N型MOSFET92作為高準位觸發開關。高準位開 關駆動為94依據南準位電壓42來驅動N型MOSFET92，低 準位開關驅動器95依據低準位電壓41來驅動n型 MOSFET93，以提供一較高之輸出電壓96。輸出電壓％ 被二個電阻分壓，以回饋至誤差放大器。升壓穩壓器9〇 並藉由開關驅動器電源電路40所提供之2.$伏參考電壓來 輸出一穩定的5伏電壓。 目前的低壓功率型MOSFET若要達成高效率，在定電 流範圍（CCR)下，閘源極電壓必須遠高4伏，以具有較 小的導通電阻（Rds)。然而，低壓功率型M〇SFET之閘 極乳化層較薄，若提供過高的閘源極電壓，則容易破壞 此類型的低壓功率型MOSFET，使得這類型的M〇SFET電 晶體具有7伏之最大閘源極電壓限制，因此若要使低壓功 率型MOSFET可達到最高的效率，則閘源極電壓最佳為限 17 200427193 制在4伏〜6伏，故於本實施例中，所採用之n型MOSFET” 的閘源極電壓較佳為4伏至6伏。 當作為高準位觸發開關之N型MOSFET被閘源極電 壓導通時，閘源極電壓被限制為4伏至6伏。下表顯示輸 入電壓範圍為2伏〜5.5伏時所調節之低準位電壓與高準位 電壓。其中，低準位電壓等於[3·〇ν+0·5ν*νίη]，且低準 位電壓於任何輸入電壓下，其最大值限制為5伏。During the initial phase, if the low-level voltage 41 is 1.6 volts, the n-type MOSFET 54 can be turned on because the n-type MOSFET 54 has a lower threshold voltage (vtn). When the boost regulator 50 operates, the low-level voltage 4] gradually rises until it reaches 4 to 5 volts. The low level voltage 41 can also be used as the operating voltage of other logic elements in the internal circuit. For example, the low level = off driver 55 provides a gate-source voltage of about 4 volts to ground during steady state = _MOF. Among them, the output terminal of the low-base diode 52 is provided. The charge doubling circuit 61 further includes an internal switching matrix, and a storage capacitor 62 = an output capacitor 63. The storage capacitor 62 is periodically charged, and outputs its stored charge to the output capacitor 63, for outputting a high level voltage 42 ', and the high level voltage 42 is almost equal to a low level voltage 200427193. The detailed operation and design of the circuit 60 can refer to the technical data of Intersil's product ICL7660A. In addition to the low-level voltage 41 and the high-level voltage 42 provided to the first step-down regulator 70 and the second step-down regulator 80, other DC converters can also be provided (eg, step-up regulator 90) That is, the high-level and low-level gate drivers included in other DC converters are connected to the switching driver power circuit 40 and the charge multiplying circuit 60 to receive the low-level voltage 41 and the south-level voltage 42 for the gate. The driver can switch the MOSFET according to the low-level voltage 41 and the high-level voltage 42. The boost regulator 90 includes an N-type MOSFET 93, an N-type MOSFET 92, and an input terminal 91. The N-type MOSFET 93 serves as a low-level trigger switch and the N-type MOSFET 92 serves as a high-level trigger switch. The high level switch automatically drives the N-type MOSFET 92 according to the south level voltage 42 and the low level switch driver 95 drives the n-type MOSFET 93 according to the low level voltage 41 to provide a higher output voltage 96. The output voltage% is divided by two resistors to feed back to the error amplifier. The boost regulator 90 outputs a stable 5 volt voltage by using the 2. $ volt reference voltage provided by the switch driver power circuit 40. For current low-voltage power MOSFETs to achieve high efficiency, the gate-source voltage must be much higher than 4 volts in the constant current range (CCR) to have a small on-resistance (Rds). However, the gate emulsification layer of the low-voltage power MOSFET is thin. If an excessively high gate-source voltage is provided, this type of low-voltage power MOSFET is easily destroyed, making this type of MOSFET transistor with a voltage of 7 volts. The maximum gate-source voltage is limited, so if the low-voltage power MOSFET can achieve the highest efficiency, the optimal gate-source voltage is the limit. 17 200427193 is controlled at 4 volts to 6 volts. Therefore, in this embodiment, the The gate-source voltage of the “n-type MOSFET” is preferably 4 volts to 6 volts. When the N-type MOSFET as a high-level trigger switch is turned on by the gate-source voltage, the gate-source voltage is limited to 4 volts to 6 volts. The following table shows the low level voltage and high level voltage adjusted when the input voltage range is 2V ~ 5.5V. Among them, the low level voltage is equal to [3 · 〇ν + 0 · 5ν * νίη], and the low level The voltage is limited to a maximum of 5 volts at any input voltage.
200427193 動作，以提供多種不同的·輸出電壓，俾能提高電源轉換《 之效率與消除MOSFET之尺寸因素。 上述實施例僅係為了方便說明而舉例而已，本發明 所主張之權利範圍自應以申請專利範圍所述為準，而非 僅限於上述實施例。 五、圖式簡單說明 圖1係習知一降壓轉換器之電路示意圖。 圖2係習知另一降壓轉換器之電路示意圖。 圖3係習知降壓轉換器之主要波形示意圖。 圖4係本發明一較佳實施例之電路示意圖。 圖5係本發明一較佳實施例之詳細電路示意圖。 六、圖號說明 内。P控制電路 10,3〇輸入電壓11，31 P型金屬氧化半導體 12 場效電晶體 N型金屬氧化半導體 場效電晶體 高準位開關驅動器 低準位開關驅動器 下降時間延遲電路 RS正反器 時脈及斜波信號 13,32,33,54,71，72,81，82,92,93 14,34,73,83,94 15,35,55,74,84,95 16 上升時間延遲電路17,36,37 18,38能隙參考電壓源19,59 20 比較器 21，57 200427193 產生器 誤差放大電壓 22 誤差放大器 23,58 參考電壓 24 電感 25 輸出電壓 26,96 濾波電容 27,53 二極體 28 電容 29 開關驅動器電源電路 40 低準位電壓 41 高準位電壓 42 升壓穩壓器 50 輸入端電感 51,91 蕭特基二極體 52 脈寬調變控制電路 56 電荷倍增電路 60,61 儲存電容 62 輸出電容 63 第一降壓穩壓器 70 控制邏輯單元 75,85 第二降壓穩壓器 80 升壓穩壓器 90200427193 acts to provide a variety of different output voltages, which can improve the efficiency of power conversion and eliminate the MOSFET size factor. The above embodiments are merely examples for the convenience of description. The scope of the claimed rights of the present invention shall be based on the scope of the patent application, rather than being limited to the above embodiments. V. Brief Description of the Drawings Figure 1 is a circuit diagram of a conventional buck converter. FIG. 2 is a circuit diagram of another conventional buck converter. Figure 3 is a schematic diagram of the main waveforms of a conventional buck converter. FIG. 4 is a schematic circuit diagram of a preferred embodiment of the present invention. FIG. 5 is a detailed circuit diagram of a preferred embodiment of the present invention. Six, the description of the drawing number. P control circuit 10, 30 input voltage 11, 31 P-type metal oxide semiconductor 12 field effect transistor N-type metal oxide semiconductor field effect transistor high level switch driver low level switch driver fall time delay circuit RS flip-flop Pulse and ramp signal 13,32,33,54,71,72,81,82,92,93 14,34,73,83,94 15,35,55,74,84,95 16 Rise time delay circuit 17 , 36,37 18,38 Bandgap reference voltage source 19,59 20 Comparator 21,57 200427193 Generator error amplifier voltage 22 Error amplifier 23,58 Reference voltage 24 Inductor 25 Output voltage 26,96 Filter capacitor 27,53 Diode Body 28 Capacitor 29 Switch driver power circuit 40 Low level voltage 41 High level voltage 42 Boost regulator 50 Input inductor 51, 91 Schottky diode 52 Pulse width modulation control circuit 56 Charge multiplier circuit 60, 61 Storage capacitor 62 Output capacitor 63 First buck regulator 70 Control logic unit 75, 85 Second buck regulator 80 Boost regulator 90
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