CN113741608B - Linear voltage regulator circuit - Google Patents
Linear voltage regulator circuit Download PDFInfo
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- CN113741608B CN113741608B CN202111002680.7A CN202111002680A CN113741608B CN 113741608 B CN113741608 B CN 113741608B CN 202111002680 A CN202111002680 A CN 202111002680A CN 113741608 B CN113741608 B CN 113741608B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention discloses a linear voltage stabilizer circuit, which is added with a first current source, a second current source and a switch PMOS tube which are equal, wherein the output of an operational amplifier provides grid source voltage for the switch PMOS tube, the first current source and the second current source enable the switch PMOS tube to flow constant current, when the input voltage is lower and the linear voltage stabilizer circuit is in heavy load, the grid voltage of the switch PMOS tube is reduced due to overlarge current flowing through the drive PMOS tube, the switch PMOS tube is conducted, the output end of the operational amplifier is raised to the grid source voltage of the switch PMOS tube, and meanwhile, the grid voltage of the drive PMOS tube is not limited by the output of the operational amplifier, so that the output of the operational amplifier is not influenced by the grid voltage of the drive PMOS tube under the condition of low input voltage and heavy load, and the linear voltage stabilizer circuit can still output stable output voltage under the condition of low input voltage and heavy load.
Description
Technical Field
The present invention relates to semiconductor circuit technology, and more particularly, to a linear regulator circuit.
Background
As shown in fig. 1, the conventional linear regulator circuit includes an operational amplifier AMP, a driving MOS transistor Pm0, a zeroth voltage dividing resistor R0, and a first voltage dividing resistor R1.
The input voltage of the linear voltage regulator is VCC, the output voltage is VDD,
VREF is a reference voltage. Usually, the output voltage VDD needs to have a driving capability, and the width-to-length ratio of the driving MOS transistor Pm0 is usually:
neglecting channel modulation effects, where β = μ C ox W is the channel width of the driving MOS tube Pm0, L is the channel length of the driving MOS tube Pm0, ids is the source-drain current of the driving MOS tube Pm0, vgs _ Pm0 is the gate-source voltage of the driving PMOS tube Pm0, vth is the threshold voltage of the driving MOS tube Pm0, mu is the carrier mobility, C ox For mountain oxide layer electric capacity of unit area, when drive MOS pipe Pm0 was used at wide voltage range (if input voltage VCC is 1.35V ~ 5.5V), drive MOS pipe Pm0 was for providing enough big driving force (load current Iload) under the low-voltage, made fortune put operating condition normal and have certain gain, guaranteed output voltage's stability, the width length ratio size can get very big usually, can increase linear regulator circuit chip area like this, simultaneously under high voltage light load, for making fortune put work normally, circuit design can be more challenging.
Disclosure of Invention
The present invention provides a linear regulator circuit, which can still output a stable output voltage under the conditions of low input voltage and heavy load, so that the linear regulator circuit can output a stable output voltage in wider input voltage application.
In order to solve the technical problem, the linear voltage regulator circuit provided by the invention comprises an operational amplifier AMP, a driving PMOS tube Pm0, a zero voltage-dividing resistor R0, a first voltage-dividing resistor R1, a switching PMOS tube Psw, a first current source I1 and a second current source I2;
the source end of the driving PMOS tube Pm0 is connected with an input voltage VCC, the drain end of the driving PMOS tube Pm0 is grounded through a zeroth voltage-dividing resistor R0 and a first voltage-dividing resistor R1 which are connected in series, and the drain end of the driving PMOS tube Pm0 is used as an output voltage VDD output end of the linear voltage regulator circuit;
the source end and the drain end of the switch PMOS tube Psw are respectively connected with the output end of the operational amplifier AMP and the grid end of the drive PMOS tube Pm0, and the grid end of the switch PMOS tube Psw is grounded;
the negative input end of the operational amplifier AMP is connected with the reference voltage VREF, and the positive input end of the operational amplifier AMP is connected with a serial connection point VFB of the zero voltage-dividing resistor R0 and the first voltage-dividing resistor R1;
the first current source I1 is connected between the output end of the operational amplifier AMP and an input voltage VCC;
the second current source I2 is connected between the grid end of the driving PMOS tube Pm0 and the ground;
the currents of the first current source I1 and the second current source I2 are equal.
Preferably, the linear regulator circuit further comprises a loop compensation resistor Rz and a loop compensation capacitor Cc;
the loop compensation resistor Rz and the loop compensation capacitor Cc are connected in series between the gate and the drain of the driving PMOS tube Pm 0.
Preferably, the loop compensation resistor Rz is 100k omega-200 k omega;
the loop compensation capacitance Cc is 1 Pf to 10 Pf.
Preferably, the reference voltage VREF is provided by a bandgap reference circuit.
Preferably, a load capacitor Cload is connected between the drain terminal of the driving PMOS transistor Pm0 and the ground.
Preferably, the operational amplifier AMP, the first current source I1 and the second current source I2 form an operational amplifier circuit;
the operational amplifier circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a first NMOS (N-channel metal oxide semiconductor) tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a sixth NMOS tube N6;
the grid end and the drain end of the first PMOS pipe P1 are in short circuit with the grid end of the second PMOS pipe P2;
the drain end of the first PMOS tube P1 is connected with the drain end of the first NMOS tube N1;
the drain end of the second PMOS tube P2 is connected with the drain end of the second NMOS tube N2 and is used as the output end of the operational amplifier AMP;
the source ends of the first NMOS transistor N1 and the second NMOS transistor N2 are in short circuit with the drain end of the sixth NMOS transistor N6;
the gate end of the first NMOS tube N1 is used as the input positive end of the operational amplifier AMP;
the grid end of the second NMOS tube N2 is used as the input negative end of the operational amplifier AMP;
the grid end and the drain end of the third PMOS pipe P3 are in short circuit with the grid end of the fourth PMOS pipe P4;
the drain end of the third PMOS tube P3 is connected with the drain end of the fourth NMOS tube N4;
the drain end of the fourth PMOS tube P4 is used as the output end of the first current source I1 and is connected with the output end of the operational amplifier AMP;
the source ends of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are all connected with an input voltage VCC;
the grid end and the drain end of the third NMOS tube N3 are in short circuit with the grid ends of the fourth NMOS tube N4, the fifth NMOS tube N5 and the sixth NMOS tube N6 and are used for being connected with a reference current IREF;
the drain terminal of a fifth NMOS transistor N5 is used as the input terminal of the second current source I2 and is connected with the gate terminal of the driving PMOS transistor Pm 0;
the source ends of the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are grounded.
Preferably, the source terminal of the switching PMOS transistor Psw is connected to the output terminal of the operational amplifier AMP, and the drain terminal thereof is connected to the gate terminal of the driving PMOS transistor Pm 0.
The linear voltage regulator circuit is additionally provided with a first current source I1, a second current source I2 and a switching PMOS (P-channel metal oxide semiconductor) tube Psw which are equal, the output of an operational amplifier AMP provides a grid-source voltage Vgs _ Psw for the switching PMOS tube Psw, and the first current source I1 and the second current source I2 enable the switching PMOS tube Psw to flow through constant current. When the input voltage VCC is low and the linear regulator circuit is in a heavy load (the load current Iload is greater than 0.1A), because a large current flows through the driving PMOS tube Pm0, the gate voltage VN2 of the driving PMOS tube Pm0 is reduced, the switching PMOS tube Psw is conducted, the output end of the operational amplifier AMP is raised to the gate source voltage Vgs _ Psw of the switching PMOS tube Psw, and meanwhile, the gate voltage of the driving PMOS tube Pm0 is not limited by the output of the operational amplifier AMP, so that the output of the operational amplifier AMP is not influenced by the gate voltage of the driving PMOS tube Pm0 under the condition of low input voltage VCC and heavy load, the linear regulator circuit can still output the stable output voltage VDD under the condition of low input voltage VCC, the linear regulator circuit can output the stable output voltage VDD under the condition of wider input voltage VCC application, and when a wide voltage range is applied (such as 1.35V-5.5V), the linear regulator circuit can not need to increase the channel width-length ratio size of the driving PMOS tube Pm0 so as to provide enough driving capability under the low voltage VCC application, make the operational amplifier work state and have a certain gain and ensure the stable output voltage VDD, thereby saving the chip area of the linear regulator circuit.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a conventional linear regulator circuit;
FIG. 2 is a circuit diagram of a linear regulator according to an embodiment of the present invention;
FIG. 3 is an operational amplifier circuit of an embodiment of the linear regulator circuit of the present invention;
FIG. 4 is a diagram showing simulation results of a linear regulator circuit.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 2, the linear regulator circuit includes an operational amplifier AMP, a driving PMOS transistor Pm0, a zeroth voltage-dividing resistor R0, a first voltage-dividing resistor R1, a switching PMOS transistor Psw, a first current source I1, and a second current source I2;
the source end of the driving PMOS pipe Pm0 is connected with an input voltage VCC, the drain end of the driving PMOS pipe Pm0 is grounded through a zero voltage-dividing resistor R0 and a first voltage-dividing resistor R1 which are connected in series, and the drain end of the driving PMOS pipe Pm0 is used as the output end of an output voltage VDD of the linear voltage regulator circuit;
the source end and the drain end of the switch PMOS tube Psw are respectively connected with the output end of the operational amplifier AMP and the grid end of the drive PMOS tube Pm0, and the grid end of the switch PMOS tube Psw is grounded;
the negative input end of the operational amplifier AMP is connected with a reference voltage VREF, and the positive input end of the operational amplifier AMP is connected with a serial connection point VFB of the zero voltage-dividing resistor R0 and the first voltage-dividing resistor R1;
the first current source I1 is connected between the output end of the operational amplifier AMP and an input voltage VCC;
the second current source I2 is connected between the grid end of the driving PMOS tube Pm0 and the ground;
the currents of the first current source I1 and the second current source I2 are equal.
In the linear regulator circuit according to the first embodiment, the first current source I1, the second current source I2, and the switching PMOS transistor Psw are added in equal amounts, the output of the operational amplifier AMP provides the gate-source voltage Vgs _ Psw for the switching PMOS transistor Psw, and the first current source I1 and the second current source I2 make the switching PMOS transistor Psw flow the constant current. When the input voltage VCC is low and the linear regulator circuit is heavily loaded (the load current Iload is greater than 0.1A), since a large current flows through the PMOS transistor Pm0, the gate voltage VN2 decreases, the PMOS transistor Psw is turned on, the first current source I1 is equal to the second current source I2, the output terminal of the operational amplifier AMP is raised to the gate-source voltage Vgs _ Psw of the PMOS transistor Psw, and the gate voltage of the PMOS transistor Pm0 is not limited by the output of the operational amplifier AMP, so that the output of the operational amplifier AMP is not affected by the gate voltage of the PMOS transistor Pm0 at a low input voltage VCC, and the linear regulator circuit can still output a stable output voltage VDD at a low input voltage VCC and a heavy load, so that the linear regulator circuit can output the stable output voltage VDD at a wider input voltage VCC application, and when the linear regulator circuit is applied in a wide voltage range (e.g., 1.35V to 5.5V), it is not necessary to increase the channel width-length ratio dimension of the PMOS transistor Pm0, so that the linear regulator circuit can provide sufficient AMP at a low voltage VCC, and the linear regulator circuit can operate in a stable gain state and can ensure a certain operating gain of the linear regulator circuit, thereby saving a chip area and operating gain of the linear regulator circuit.
The linear regulator circuit of the first embodiment can operate in a wider voltage range. The simulation result is shown in fig. 4, in which VDD1P2 is the simulation result of the conventional linear regulator, VDD1P2_ content is the simulation result of the linear regulator of the first embodiment, the operating range of the linear regulator of the first embodiment can be increased by about 168mV, and the lowest input voltage VCC can be up to 1.34V.
Example two
Based on the first implementation, the linear regulator circuit further comprises a loop compensation resistor Rz and a loop compensation capacitor Cc;
the loop compensation resistor Rz and the loop compensation capacitor Cc are connected in series between the gate and the drain of the driving PMOS tube Pm 0.
Preferably, the loop compensation resistor Rz is 100k Ω -200 k Ω;
the loop compensation capacitance Cc is 1 Ρ to 10 Ρ.
Preferably, the reference voltage VREF is provided by a Bandgap reference (Bandgap reference) circuit.
Preferably, a load capacitor Cload is connected between the drain terminal of the driving PMOS transistor Pm0 and the ground.
EXAMPLE III
Based on the linear regulator circuit implemented as one, as shown in fig. 3, the operational amplifier AMP, the first current source I1 and the second current source I2 form an operational amplifier circuit;
the operational amplifier circuit comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a sixth NMOS tube N6;
the grid end and the drain end of the first PMOS pipe P1 are in short circuit with the grid end of the second PMOS pipe P2;
the drain end of the first PMOS tube P1 is connected with the drain end of the first NMOS tube N1;
the drain end of the second PMOS tube P2 is connected with the drain end of the second NMOS tube N2 and is used as the output end of the operational amplifier AMP;
the source ends of the first NMOS transistor N1 and the second NMOS transistor N2 are in short circuit with the drain end of the sixth NMOS transistor N6;
the gate end of the first NMOS tube N1 is used as the input positive end of the operational amplifier AMP;
the grid end of the second NMOS tube N2 is used as the input negative end of the operational amplifier AMP;
the grid end and the drain end of the third PMOS pipe P3 are in short circuit with the grid end of the fourth PMOS pipe P4;
the drain end of the third PMOS tube P3 is connected with the drain end of the fourth NMOS tube N4;
the drain end of the fourth PMOS tube P4 is used as the output end of the first current source I1 and is connected with the output end of the operational amplifier AMP;
the source ends of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are all connected with an input voltage VCC;
the grid end and the drain end of the third NMOS tube N3 are in short circuit with the grid ends of the fourth NMOS tube N4, the fifth NMOS tube N5 and the sixth NMOS tube N6 and are used for being connected with a reference current IREF;
the drain terminal of a fifth NMOS transistor N5 is used as the input terminal of the second current source I2 and is connected with the gate terminal of the driving PMOS transistor Pm 0;
the source ends of the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are grounded.
Preferably, the source terminal of the switching PMOS transistor Psw is connected to the output terminal of the operational amplifier AMP, and the drain terminal thereof is connected to the gate terminal of the driving PMOS transistor Pm 0.
And the source of the switching PMOS pipe Psw is connected with the output of the operational amplifier AMP, and the drain of the switching PMOS pipe Psw is connected with the grid of the driving PMOS pipe Pm 0.
And the third linear voltage regulator circuit is implemented, wherein the first current source I1 and the second current source I2 are respectively generated by the mirror image of a fourth PMOS tube P4 and a fifth NMOS tube N5 in the operational amplifier circuit. When Vgs _ P1+ Vds _ N1+ Vgs _ N6< VCC < Vgs _ Pm0+ Vgs _ Psw and the linear regulator circuit is heavily loaded (load current Iload is greater than 0.1A), vgs _ P1 is the gate-source voltage of the first PMOS transistor P1, vds _ N1 is the drain-source voltage of the first NMOS transistor N1, vgs _ N6 is the gate-source voltage of the sixth NMOS transistor N6, vgs _ Pm0 is the gate-source voltage of the driving PMOS transistor Pm0, vgs _ Psw is the gate-source voltage of the switching PMOS transistor Pm0, the driving PMOS transistor Pm0 flows a large current, the gate-source voltage Vgs _ Pm0 of the driving PMOS transistor Pm0 becomes large to make the gate-end voltage VN2 of the driving transistor Pm0 low (VN 2> Vdsat _ N5, vdsat _ N5 is the drain-source voltage of the fifth NMOS transistor N5), the PMOS transistor Psw is turned on, the first current source psi 1, the second current source I2 is AMP, the output amplifier is the gate-terminal voltage VOUT operational amplifier, and the linear regulator circuit is a constant current source operational amplifier circuit output voltage vfw = VOUT, and the linear regulator circuit has a normal operation gain and a constant voltage output Psw output; when VCC is larger than Vgs _ Pm0+ Vgs _ Psw and the linear voltage regulator circuit is in heavy load, the switch PMOS tube Psw is switched on, the voltage VOUT at the output end of the operational amplifier AMP is equal to the voltage VN2 at the gate end of the driving PMOS tube Pm0, at the moment, a feedback loop formed by the operational amplifier AMP, the driving PMOS tube Pm0 and the divider resistor works normally, and the linear voltage regulator outputs stable voltage.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A linear voltage stabilizer circuit is characterized by comprising an operational amplifier, a driving PMOS tube, a zero voltage-dividing resistor, a first voltage-dividing resistor, a switching PMOS tube, a first current source and a second current source;
the source end of the driving PMOS tube is connected with input voltage, the drain end of the driving PMOS tube is grounded through a zeroth voltage-dividing resistor and a first voltage-dividing resistor which are connected in series, and the drain end of the driving PMOS tube is used as an output voltage output end of the linear voltage stabilizer circuit;
the source end and the drain end of the switch PMOS tube are respectively connected with the output end of the operational amplifier and the grid end of the drive PMOS tube, and the grid end of the switch PMOS tube is grounded;
the negative input end of the operational amplifier is connected with a reference voltage, and the positive input end of the operational amplifier is connected with a serial connection point of a zero voltage-dividing resistor and a first voltage-dividing resistor;
the first current source is connected between the output end of the operational amplifier and the input voltage;
the second current source is connected between the grid end of the driving PMOS tube and the ground;
the currents of the first current source and the second current source are equal.
2. The linear regulator circuit according to claim 1,
the linear voltage regulator circuit also comprises a loop compensation resistor and a loop compensation capacitor;
and the loop compensation resistor and the loop compensation capacitor are connected between the grid and the drain of the driving PMOS tube in series.
3. The linear regulator circuit according to claim 2,
the loop compensation resistance is 100k omega-200 k omega;
the loop compensation capacitance is 1 Pf 10 Pf.
4. The linear regulator circuit according to claim 1,
the reference voltage is provided by a bandgap reference circuit.
5. The linear regulator circuit according to claim 1,
and a load capacitor is connected between the drain end of the driving PMOS tube and the ground.
6. The linear regulator circuit according to claim 1,
the operational amplifier, the first current source and the second current source form an operational amplifier circuit;
the operational amplifier circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;
the grid end and the drain end of the first PMOS tube are in short circuit with the grid end of the second PMOS tube;
the drain end of the first PMOS tube is connected with the drain end of the first NMOS tube;
the drain end of the second PMOS tube is connected with the drain end of the second NMOS tube and is used as the output end of the operational amplifier;
the source ends of the first NMOS tube and the second NMOS tube are in short circuit with the drain end of the sixth NMOS tube;
the grid end of the first NMOS tube is used as the input positive end of the operational amplifier;
the grid end of the second NMOS tube is used as the input negative end of the operational amplifier;
the grid end and the drain end of the third PMOS tube are in short circuit with the grid end of the fourth PMOS tube;
the drain end of the third PMOS tube is connected with the drain end of the fourth NMOS tube;
the drain terminal of the fourth PMOS tube is used as the output terminal of the first current source and is connected with the output terminal of the operational amplifier;
the source ends of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with input voltage;
the grid end and the drain end of the third NMOS tube are in short circuit with the grid ends of the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube and are used for being connected with reference current;
the drain end of the fifth NMOS tube is used as the input end of the second current source and is connected with the gate end of the driving PMOS tube;
the source ends of the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are grounded.
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| CN202111002680.7A CN113741608B (en) | 2021-08-30 | 2021-08-30 | Linear voltage regulator circuit |
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| WO2016082420A1 (en) * | 2014-11-24 | 2016-06-02 | 深圳市中兴微电子技术有限公司 | Low dropout linear voltage regulator |
| CN111367345A (en) * | 2020-05-26 | 2020-07-03 | 江苏长晶科技有限公司 | Compensation method for improving full load stability of low dropout linear regulator and circuit thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102130659B (en) * | 2011-01-20 | 2013-03-13 | 西安理工大学 | Circuit structure for reducing input offset voltage of two-stage operational amplifier |
| KR101409736B1 (en) * | 2012-09-05 | 2014-06-20 | 주식회사 실리콘웍스 | Low Dropout Circuit Enabling Controlled Start-up And Method For Controlling Thereof |
| CN106774575B (en) * | 2016-12-29 | 2019-05-31 | 北京兆易创新科技股份有限公司 | A kind of low pressure difference linear voltage regulator |
| TWI666538B (en) * | 2018-04-24 | 2019-07-21 | 瑞昱半導體股份有限公司 | Voltage regulator and voltage regulating method |
| CN109871060B (en) * | 2019-02-27 | 2021-04-06 | 上海华虹宏力半导体制造有限公司 | Linear voltage regulator circuit |
| CN113126690A (en) * | 2019-12-31 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | Low dropout regulator and control circuit thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016082420A1 (en) * | 2014-11-24 | 2016-06-02 | 深圳市中兴微电子技术有限公司 | Low dropout linear voltage regulator |
| CN111367345A (en) * | 2020-05-26 | 2020-07-03 | 江苏长晶科技有限公司 | Compensation method for improving full load stability of low dropout linear regulator and circuit thereof |
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