CN110350887B - Resistance-capacitance oscillator circuit and clock signal generating method - Google Patents

Resistance-capacitance oscillator circuit and clock signal generating method Download PDF

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CN110350887B
CN110350887B CN201810308530.0A CN201810308530A CN110350887B CN 110350887 B CN110350887 B CN 110350887B CN 201810308530 A CN201810308530 A CN 201810308530A CN 110350887 B CN110350887 B CN 110350887B
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circuit
coupled
comparator
electrode
pmos
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CN110350887A (en
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唐华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/1271—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the frequency being controlled by a control current, i.e. current controlled oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
    • H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

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  • Amplifiers (AREA)

Abstract

A method for generating a clock signal and a resistor-capacitor oscillator circuit, comprising: electric capacity charge-discharge circuit, resistance shunting circuit, comparator circuit and RS trigger circuit, electric capacity charge-discharge circuit includes: first charge-discharge circuit and second charge-discharge circuit, the comparator circuit includes: a first comparator, a second comparator, a first feedback loop, and a second feedback loop, the RS flip-flop circuit comprising: the first feedback loop is used for controlling the first comparator to close working current and outputting a low level signal when the second trigger circuit outputs the low level signal; and the second feedback loop is used for controlling the second comparator to close the working current and outputting a low level signal when the first trigger circuit outputs the low level signal. By applying the circuit, the power consumption of the oscillator circuit can be reduced.

Description

Resistance-capacitance oscillator circuit and clock signal generating method
Technical Field
The embodiment of the invention relates to the field of circuits, in particular to a resistance-capacitance oscillator circuit and a clock signal generation method.
Background
A Resistance Capacitance Oscillator (RC OSC) circuit is an OSC circuit with high implementation precision, and because its output frequency is only related to on-chip Resistance and Capacitance, the output frequency is less affected by temperature and power supply voltage than a ring Oscillator circuit, so that it is widely used.
The traditional RC OSC circuit consists of a resistance shunt circuit, a capacitance charge-discharge circuit, a comparator circuit and an RS trigger circuit, wherein the resistance shunt circuit and the capacitance charge-discharge circuit are respectively coupled with the comparator circuit and used for outputting signals to the comparator circuit, and the comparator circuit amplifies comparison results and outputs the amplified comparison results to the RS trigger circuit to trigger the RS trigger circuit to generate clock signals and feed the clock signals back to the capacitance charge-discharge circuit.
In the actual signal generation process, the conventional RC OSC circuit requires a large operating current, resulting in large power consumption. In all circuit configurations, the comparator circuit consumes the most power because of its quiescent current. For example, the average current of the entire RC OSC is 87uA, with the average current of the comparator circuit being 76uA.
Disclosure of Invention
The technical problem solved by the embodiment of the invention is how to reduce the power consumption of the resistance-capacitance oscillator circuit.
To solve the above technical problem, an embodiment of the present invention provides a rc oscillator circuit, including: electric capacity charge-discharge circuit, resistance shunting circuit, comparator circuit and RS trigger circuit, electric capacity charge-discharge circuit includes: first charge-discharge circuit and second charge-discharge circuit, the comparator circuit includes: first comparator, second comparator, first feedback loop and second feedback loop, RS flip-flop circuit includes: a first flip-flop circuit and a second flip-flop circuit, wherein: the first charging and discharging circuit is used for receiving an output signal of the first trigger circuit, generating a voltage signal and outputting the voltage signal to the first comparator; the second charging and discharging circuit is used for receiving the output signal of the second trigger circuit, generating a voltage signal and outputting the voltage signal to the second comparator; the resistance shunt circuit is used for sharing the current of the first charge-discharge circuit and the second charge-discharge circuit, generating a reference signal and outputting the reference signal to the first comparator circuit and the second comparator circuit; the first comparator is used for comparing output signals of the first charging and discharging circuit and the resistance shunt circuit and outputting a comparison result to the first trigger; the second comparator is used for comparing output signals of the second charge-discharge circuit and the resistance shunt circuit and outputting a comparison result to the second trigger; the first feedback loop is used for outputting a control signal to the driving end of the first comparator when the second trigger circuit outputs a low level signal, controlling the first comparator to close working current and outputting a low level signal; the second feedback loop is used for outputting a control signal to the driving end of the second comparator when the first trigger circuit outputs a low level signal, controlling the second comparator to close the working current and outputting a low level signal; the first trigger circuit is used for receiving output signals of the first comparator and the second trigger, generating a clock signal and outputting the clock signal; and the second trigger circuit is used for receiving the output signals of the second comparator and the first trigger, generating a clock signal and outputting the clock signal.
Optionally, the resistive shunt circuit includes: a resistor and a MOS tube.
Optionally, the first charging and discharging circuit includes: first PMOS pipe, third NMOS pipe and first electric capacity, second charge-discharge circuit includes: second PMOS pipe, first NMOS pipe, third NMOS pipe and second electric capacity, resistance shunt circuit includes: a first resistor and a second NMOS transistor, wherein: the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the first port of the first resistor are coupled with each other and then connected with a power supply voltage, the drain electrode of the first PMOS tube, the source electrode of the third PMOS tube, the first port of the first capacitor and the first input end of the first comparator are coupled with each other, and the grid electrode of the first PMOS tube, the grid electrode of the third PMOS tube and the output end of the first trigger are coupled with each other; the drain electrode of the second PMOS transistor, the drain electrode of the first NMOS transistor, the first port of the second capacitor, and the first input terminal of the second comparator are all coupled to each other, and the gate electrode of the second PMOS transistor, the gate electrode of the first NMOS transistor, and the output terminal of the second flip-flop are all coupled to each other; the drain electrode of the third PMOS tube, the source electrode of the first NMOS tube and the drain electrode of the third NMOS tube are all coupled with each other; the gate of the third NMOS transistor, the gate of the second NMOS transistor, the drain of the second NMOS transistor, the second port of the first resistor, the second input of the first comparator, and the second input of the second comparator are all coupled to each other, and the source of the third NMOS transistor, the second port of the first capacitor, the second port of the second capacitor, and the source of the second NMOS transistor are grounded after being coupled to each other.
Optionally, the first charging and discharging circuit includes: fourth PMOS pipe, fourth NMOS pipe, seventh PMOS pipe and third electric capacity, the second charge-discharge circuit includes: fifth PMOS pipe, fifth NMOS pipe, seventh PMOS pipe and fourth electric capacity, resistance shunt circuit includes: a second resistor and a sixth PMOS tube, wherein: a source electrode of the fourth PMOS transistor, a source electrode of the fifth PMOS transistor, and a drain electrode of the seventh PMOS transistor are all coupled to each other, a drain electrode of the fourth PMOS transistor, a first input terminal of the first comparator, a drain electrode of the fourth NMOS transistor, and a first port of the third capacitor are all coupled to each other, and a gate electrode of the fourth PMOS transistor, a gate electrode of the fourth NMOS transistor, and a first output terminal of the first trigger are all coupled to each other; a drain electrode of the fifth PMOS transistor, a first input end of the second comparator, a drain electrode of the fifth NMOS transistor, and a first port of the fourth capacitor are all coupled to each other, and a gate electrode of the fifth PMOS transistor, a gate electrode of the fifth NMOS transistor, and an output end of the second trigger are all coupled to each other; the source electrode of the fourth NMOS transistor, the source electrode of the fifth NMOS transistor, the second port of the third capacitor, the second port of the fourth capacitor and the second port of the second resistor are grounded after being coupled with each other; the grid electrode of the seventh PMOS tube is coupled with a current bias signal, and the source electrode of the seventh PMOS tube is coupled with the source electrode of the sixth PMOS tube and then connected with power supply voltage; the grid electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube, the first port of the second resistor, the second input end of the first comparator and the second input end of the second comparator are all coupled with each other.
Optionally, the comparator comprises: current mirror circuit, pull-up circuit, pull-down circuit, common source amplifier circuit, wherein: the current mirror circuit is used for receiving output signals of the capacitor charging and discharging circuit and the resistor shunt circuit and providing current sources for the pull-up circuit, the pull-down circuit and the common source amplifier circuit; the common source amplifier circuit is used for comparing and amplifying voltage signals and outputting the voltage signals to the RS trigger circuit; the pull-up circuit is used for receiving a control signal of the feedback loop and cutting off the working current; and the pull-down circuit is used for receiving the reverse control signal of the feedback loop when the pull-up circuit cuts off the working current and controlling the common source amplifier circuit to output a low-voltage signal.
Optionally, the current mirror circuit includes: ninth PMOS pipe, tenth PMOS pipe, eleventh PMOS pipe, sixth NMOS pipe and seventh NMOS pipe, wherein: the grid electrode of the ninth PMOS tube, the pull-up circuit and the common source amplifier circuit are coupled with each other and then are connected with a current bias signal, the source electrode of the ninth PMOS tube, the pull-up circuit and the common source amplifier circuit are coupled with each other and then are connected with a power supply voltage, and the drain electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are coupled with each other; a grid electrode of the tenth PMOS tube is a second input end of the comparator, and a drain electrode of the tenth PMOS tube, a grid electrode of the sixth NMOS tube, a drain electrode of the sixth NMOS tube and a grid electrode of the seventh NMOS tube are all coupled with each other; the grid electrode of the eleventh PMOS tube is a first input end of the comparator, and the drain electrode of the eleventh PMOS tube, the drain electrode of the seventh NMOS tube, the pull-down circuit and the common source amplifier circuit are all coupled with one another; and the source electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube, the pull-down circuit and the common source amplifier circuit are grounded after being coupled with each other.
Optionally, the common-source amplifier circuit comprises: twelfth PMOS pipe and eighth NMOS pipe, wherein: the source electrode of the twelfth PMOS tube, the source electrode of the ninth PMOS tube and the pull-up circuit are coupled with each other and then connected with a power supply voltage, the grid electrode of the twelfth PMOS tube, the grid electrode of the ninth PMOS tube and the pull-up circuit are coupled with each other and then connected with a bias current signal, and the drain electrode of the twelfth PMOS tube, the drain electrode of the eighth NMOS tube and the pull-down circuit are coupled with each other and then are output ends of the comparators; the grid electrode of the eighth NMOS transistor, the drain electrode of the eleventh PMOS transistor, the drain electrode of the seventh NMOS transistor and the pull-down circuit are all coupled with each other, and the source electrode of the eighth NMOS transistor, the source electrode of the seventh NMOS transistor, the source electrode of the sixth NMOS transistor and the pull-down circuit are grounded after being coupled with each other; the drain electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are all coupled with each other; a grid electrode of the tenth PMOS tube is a second input end of the comparator, and a drain electrode of the tenth PMOS tube, a grid electrode of the sixth NMOS tube, a drain electrode of the sixth NMOS tube and a grid electrode of the seventh NMOS tube are all coupled with each other; and the grid electrode of the eleventh PMOS tube is a first input end of the comparator.
Optionally, the pull-up circuit comprises: an eighth PMOS transistor, the pull-down circuit including: the first phase inverter, the second phase inverter, the ninth NMOS pipe and the tenth NMOS pipe, wherein: a grid electrode of the ninth PMOS tube, a drain electrode of the eighth PMOS tube and a grid electrode of the twelfth PMOS tube are coupled with each other and then are connected with a current bias signal, a source electrode of the ninth PMOS tube, a source electrode of the eighth PMOS tube and a source electrode of the twelfth PMOS tube are coupled with each other and then are connected with a power voltage, and a drain electrode of the ninth PMOS tube, a source electrode of the tenth PMOS tube and a source electrode of the eleventh PMOS tube are coupled with each other; a grid electrode of the tenth PMOS tube is a second input end of the comparator, and a drain electrode of the tenth PMOS tube, a grid electrode of the sixth NMOS tube, a drain electrode of the sixth NMOS tube and a grid electrode of the seventh NMOS tube are all coupled with each other; a grid electrode of the eleventh PMOS tube is a first input end of the comparator, and a drain electrode of the eleventh PMOS tube, a drain electrode of the seventh NMOS tube, a drain electrode of the ninth NMOS tube and a grid electrode of the eighth NMOS tube are all coupled with each other; the source electrode of the sixth NMOS transistor, the source electrode of the seventh NMOS transistor, the source electrode of the ninth NMOS transistor, the source electrode of the eighth NMOS transistor and the source electrode of the tenth NMOS transistor are grounded after being coupled with each other; the drain electrode of the twelfth PMOS tube, the drain electrode of the eighth NMOS tube and the drain electrode of the tenth NMOS tube are coupled with each other and then are output ends of the comparator; the grid electrode of the eighth PMOS tube is a driving end of the comparator, and is coupled with the grid electrode ENB of the ninth NMOS tube through a first phase inverter and is coupled with the grid electrode of the tenth NMOS tube through a second phase inverter.
Optionally, the feedback loop comprises: n inverters coupled to each other, wherein N is zero or a positive even number.
Optionally, the first feedback loop comprises: a third inverter and a fourth inverter, the second feedback loop comprising: a fifth inverter and a sixth inverter, the first flip-flop circuit comprising: a seventh inverter and a first nand gate, the second flip-flop circuit comprising: an eighth inverter and a second nand gate, wherein: an input end of the seventh inverter is coupled to the output end of the first comparator, and an output end of the seventh inverter is coupled to the first input end of the first nand gate; the second input end of the first nand gate is coupled to the output end of the second nand gate, and the output end of the first nand gate is the output end of the first trigger circuit and is coupled to the first input end of the second nand gate and the input end of the sixth inverter respectively; an input end of the eighth inverter is coupled to the output end of the second comparator, and an output end of the eighth inverter is coupled to the second input end of the second nand gate; the output end of the second nand gate is the output end of the second trigger circuit and is respectively coupled with the second input end of the first nand gate and the input end of the fourth inverter; the output end of the fourth inverter is coupled with the input end of the third inverter, and the output end of the third inverter is coupled with the driving end of the first comparator; an output end of the sixth inverter is coupled to an input end of the fifth inverter, and an output end of the fifth inverter is coupled to a driving end of the second comparator.
The embodiment of the invention provides a clock signal generation method, which adopts any one of the resistance-capacitance oscillator circuits to generate clock signals.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the resistance-capacitance oscillator circuit provided by the embodiment of the invention, through the feedback loop, the working current of the comparator can be closed based on the output signal of the RS trigger, the comparator is controlled to output low level, and the comparator can be closed within a period of time, so that the power consumption of the comparator circuit can be effectively reduced, and the power consumption of the whole oscillator circuit is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a rc oscillator circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an output signal of a RC oscillator circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a capacitor charging and discharging circuit and a resistor shunt circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another capacitor charging and discharging circuit and a resistor shunt circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a feedback loop and flip-flop circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a comparator according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a simulation result of power consumption of a rc oscillator circuit according to an embodiment of the present invention.
Detailed Description
In the existing product, the conventional RC OSC circuit is composed of a resistance shunt circuit, a capacitance charge-discharge circuit, a comparator circuit, and an RS flip-flop circuit, wherein the resistance shunt circuit and the capacitance charge-discharge circuit are respectively coupled to the comparator circuit for outputting a signal to the comparator circuit, and the comparator circuit amplifies a comparison result and outputs the amplified comparison result to the RS flip-flop circuit for triggering the RS flip-flop circuit to generate a clock signal, and feeding the clock signal back to the capacitance charge-discharge circuit. In the actual signal generation process, the conventional RC OSC circuit requires a large operating current, resulting in large power consumption. In all the component circuits, the comparator circuit consumes the largest power consumption because of the static current of the comparator circuit.
According to the resistance-capacitance oscillator circuit provided by the embodiment of the invention, through the feedback loop, the working current of the comparator can be closed based on the output signal of the RS trigger, the comparator is controlled to output low level, and the comparator can be closed within a period of time, so that the power consumption of the comparator circuit can be effectively reduced, and the power consumption of the whole oscillator circuit is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, an embodiment of the present invention provides a rc oscillator circuit, which may include: capacitance charge-discharge circuit 101, resistance shunt circuit 102, comparator circuit 103 and RS flip-flop circuit 104, wherein: the capacitance charging and discharging circuit 101 includes: a first charging and discharging circuit 1011 and a second charging and discharging circuit 1012, the comparator circuit 103 includes: a first comparator 1031, a second comparator 1032, a first feedback loop 1033, and a second feedback loop 1034, and the RS flip-flop circuit 104 includes: a first flip-flop circuit 1041 and a second flip-flop circuit 1042, wherein:
the first charging and discharging circuit 1011 is configured to receive an output signal of the first flip-flop circuit 1041, generate a voltage signal, and output the voltage signal to the first comparator 1031.
The second charging and discharging circuit 1012 is configured to receive an output signal of the second flip-flop circuit 1042, generate a voltage signal, and output the voltage signal to the second comparator 1032.
The resistance shunt circuit 102 is configured to share currents of the first charging and discharging circuit 1011 and the second charging and discharging circuit 1012, generate a reference signal, and output the reference signal to the first comparator circuit 1031 and the second comparator circuit 1032.
The first comparator 1031 is configured to compare output signals of the first charging and discharging circuit 1011 and the resistance shunt circuit 102, and output a comparison result to the first flip-flop 1041.
The second comparator 1032 is configured to compare the output signals of the second charging and discharging circuit 1012 and the resistance shunt circuit 102, and output a comparison result to the second flip-flop 1042.
The first feedback loop 1033 is configured to output a control signal to the driving terminal of the first comparator 1031 when the second flip-flop circuit 1042 outputs a low level signal, control the first comparator 1031 to close the working current, and output a low level signal.
The second feedback loop 1034 is configured to output a control signal to the driving terminal of the second comparator 1032 when the first flip-flop circuit 1041 outputs a low level signal, control the second comparator 1032 to turn off the working current, and output a low level signal.
The first flip-flop circuit 1041 is configured to receive output signals of the first comparator 1031 and the second flip-flop 1042, generate a clock signal, and output the clock signal.
The second flip-flop circuit 1042 is configured to receive the output signals of the second comparator 1032 and the first flip-flop 1041, generate a clock signal, and output the clock signal.
In particular implementations, the feedback loop, i.e., the first feedback loop 1033 or the second feedback loop 1034, may include: n inverters coupled to each other, wherein N is 0 or a positive even number.
In an embodiment of the present invention, the feedback loop includes 0 inverters, and an output signal of the first flip-flop circuit 1041 is directly input to a driving end of the second comparator 1032, and is used for controlling the second comparator 1032 to turn off an operating current and output a low level signal.
In another embodiment of the present invention, the feedback loop includes 0 inverters, and the output signal of the second flip-flop circuit 1042 is directly input to the driving terminal of the first comparator 1031, so as to control the first comparator 1031 to turn off the working current and output a low level signal.
In a specific implementation, the resistance shunt circuit 102 may be composed of a resistor and a MOS transistor. For example, the resistor and the PMOS tube are combined or the resistor and the NMOS tube are combined.
In a specific implementation, either one of the first comparator 1031 or the second comparator 1032 in the comparator circuit 103 may include: current mirror circuit, pull-up circuit, pull-down circuit, and common source amplifier circuit, wherein: the current mirror circuit is used for receiving output signals of the capacitor charging and discharging circuit and the resistor shunt circuit and providing current sources for the pull-up circuit, the pull-down circuit and the common source amplifier circuit. And the common source amplifier circuit is used for comparing and amplifying voltage signals and outputting the voltage signals to the RS trigger circuit. And the pull-up circuit is used for receiving the control signal of the feedback loop and cutting off the working current. And the pull-down circuit is used for receiving the reverse control signal of the feedback loop when the pull-up circuit cuts off the working current and controlling the common-source amplifier circuit to output a low-voltage signal.
In an embodiment of the present invention, the current mirror circuit includes: ninth PMOS pipe, tenth PMOS pipe, eleventh PMOS pipe, sixth NMOS pipe and seventh NMOS pipe, wherein:
the gate of the ninth PMOS tube, the pull-up circuit and the common source amplifier circuit are coupled with each other and then are connected with a current bias signal, the source of the ninth PMOS tube, the pull-up circuit and the common source amplifier circuit are coupled with each other and then are connected with a power supply voltage, and the drain of the ninth PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are coupled with each other.
The grid electrode of the tenth PMOS tube is a second input end of the comparator, and the drain electrode of the tenth PMOS tube, the grid electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are all coupled with each other.
The grid electrode of the eleventh PMOS tube is a first input end of the comparator, and the drain electrode of the eleventh PMOS tube, the drain electrode of the seventh NMOS tube, the pull-down circuit and the common source amplifier circuit are all coupled with each other.
And the source electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube, the pull-down circuit and the common source amplifier circuit are grounded after being coupled with each other.
In an embodiment of the present invention, the current mirror circuit includes: ninth PMOS pipe, tenth PMOS pipe, eleventh PMOS pipe, sixth NMOS pipe and seventh NMOS pipe, the common source amplifier circuit includes: a twelfth PMOS tube and an eighth NMOS tube, wherein:
and the source electrode of the twelfth PMOS tube, the source electrode of the ninth PMOS tube and the pull-up circuit are coupled with each other and then connected with a power supply voltage, the grid electrode of the twelfth PMOS tube, the grid electrode of the ninth PMOS tube and the pull-up circuit are coupled with each other and then connected with a bias current signal, and the drain electrode of the twelfth PMOS tube, the drain electrode of the eighth NMOS tube and the pull-down circuit are coupled with each other and then are output ends of the comparators.
The grid electrode of the eighth NMOS transistor, the drain electrode of the eleventh PMOS transistor, the drain electrode of the seventh NMOS transistor and the pull-down circuit are all coupled with each other, and the source electrode of the eighth PMOS transistor, the source electrode of the seventh NMOS transistor, the source electrode of the sixth NMOS transistor and the pull-down circuit are grounded after being coupled with each other.
The drain electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are all coupled with each other.
The grid electrode of the tenth PMOS tube is a second input end of the comparator, and the drain electrode of the tenth PMOS tube, the grid electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are all coupled with each other.
And the grid electrode of the eleventh PMOS tube is a first input end of the comparator.
With the above rc oscillator circuit, in the case of disconnecting the first feedback loop 1033 and the second feedback loop 1034:
through the capacitance charging and discharging circuit 101, a signal can be output to the comparator circuit 103 through capacitance charging or discharging, after the comparator circuit 103 compares a capacitance charging and discharging signal with a reference signal output by the resistance shunt circuit 102, the signal is output to the RS flip-flop circuit 104 to generate a clock signal, and the clock signal is fed back to the capacitance charging and discharging circuit 101 to be executed in a circulating manner, so that the RS flip-flop circuit 104 can generate the clock signal. The detailed working principle is as follows:
after the capacitor charging and discharging circuit 101 is charged quickly, because the voltage signal of the first input terminal a (abbreviated as point a) of the first comparator 1031 or the first input terminal B (abbreviated as point B) of the second comparator 1032 is higher than the reference signal output by the resistor shunt circuit 102, the output of the comparator circuit 103 is "1", which triggers the output of the RS flip-flop circuit to be "1", when the voltage signals of the two points A, B are discharged to the reference signal output by the resistor shunt circuit 102, the output of the comparator circuit 103 is "0", which triggers the output of the RS flip-flop circuit 104 to be "0", thereby generating the clock signal, because the charging currents of A, B are consistent, the duty ratio of the clock signal can be ensured to be 50%, and the output frequency is 1/RC, where R is a resistance value and C is a capacitance value.
An embodiment of the present invention provides a schematic diagram of an output signal of a rc oscillator circuit, as shown in fig. 2.
Fig. 2 shows a schematic diagram of output signals at points a and B, an output end Q (referred to as Q point) of the first flip-flop 1041, and an output end QB (referred to as QB point) of the second flip-flop 1042 when the first feedback loop 1033 and the second feedback loop 1034 are disconnected by using the above rc oscillator circuit, and it can be seen from fig. 2 that: the output signals of the point Q and the point QB are square wave signals, the output signals of the point a and the point B are periodic signals, and based on the signal waveforms output by the point a and the point B, the comparator can be divided into a comparison phase and a holding phase:
when the first comparator 1031 is in the hold stage, the second comparator 1032 is in the comparison state, the signal at the point a is "0", the signal at the point B is a slope greater than "0", the signal at the point Q is "1", and the signal at the point QB is "0";
when the second comparator 1032 is in the hold phase, the first comparator 1032 is in the comparison state, the B-point signal is "0", the a-point signal is a slope greater than "0", the Q-point signal is "0", and the QB-point signal is "1".
Based on the signal characteristics, it is possible to open the first feedback loop 1033 or the second feedback loop 1034, such that when the first comparator 1031 or the second comparator 1032 is in the hold stage, the QB point or Q point signal is used to turn off the quiescent current of the first comparator 1031 or the second comparator 1032 and pull down the quiescent current to "0", as follows:
when the Q-point signal is "0", the second feedback loop 1034 turns off the second comparator 1032 and pulls down the output of the second comparator 1032 to be "0", so that the second comparator 1032 is in a hold state;
when the QB point signal is "0", the first feedback loop 1033 turns off the first comparator 1031 and pulls down the output of the first comparator 1031 to "0", so that the first comparator 1031 is in a hold state.
Meanwhile, when the QB point and Q point signals are "1", opening the first and second feedback loops 1033 and 1034 does not affect the normal operation of the comparison stages of the first and second comparators 1031 and 1032, so that the RS flip-flop circuit 104 can normally output the clock signal.
By applying the resistance-capacitance oscillator circuit, under the condition that the normal output clock signal of the RS trigger circuit is not influenced, the first comparator is closed and the output of the first comparator is pulled down when the second trigger circuit outputs a low-voltage signal through the first feedback loop; through the second feedback loop, when the first trigger circuit outputs a low-voltage signal, the second comparator is closed, and the output of the second comparator is pulled down.
In order to make those skilled in the art better understand and implement the present invention, the embodiment of the present invention provides a schematic structural diagram of a charging and discharging circuit and a resistance shunt circuit, as shown in fig. 3.
Referring to fig. 3, the capacitance charging and discharging circuit 101 includes: first charge and discharge circuit and second charge and discharge circuit, wherein first charge and discharge circuit includes: first PMOS pipe TP1, third PMOS pipe TP3, third NMOS pipe TN3 and first electric capacity C1, the second charge-discharge circuit includes: a second PMOS transistor TP2, a first NMOS transistor TN1, a third NMOS transistor TN3, and a second capacitor C2, wherein the resistor shunt circuit 102 includes: first resistance R1 and second NMOS pipe TN2, wherein:
the source of TP1, the source of TP2, and the first port of R1 are coupled to each other and then connected to a power supply Voltage (VDD), the drain of TP1, the source of TP3, the first port of C1, and the first input a of the first comparator 1031 are all coupled to each other, and the gate of TP1, the gate of TP3, and the output Q of the first flip-flop 1041 are all coupled to each other.
The drain of the TP2, the drain of the TN1, the first port of the C2, and the first input B of the second comparator 1032 are all coupled to each other, and the gate of the TP2, the gate of the TN1, and the output QB of the second flip-flop 1042 are all coupled to each other.
The drain electrode of the TP3, the source electrode of the TN1 and the drain electrode of the TN3 are all coupled with each other.
The gate of the TN3, the gate of the TN2, the drain of the TN2, the second port of the R1, the second input terminal VREF _ CMP of the first comparator 1031, and the second input terminal VREF _ CMP of the second comparator 1032 are all coupled to each other, and the source of the TN3, the second port of the C1, the second port of the C2, and the source of the TN2 are all coupled to ground (VSS) after being coupled to each other.
The working principle of the charging and discharging circuit 101 and the resistance shunt circuit 102 can be referred to the description in the above embodiments, and is not described herein again.
In order to make those skilled in the art better understand and implement the present invention, the embodiment of the present invention provides another structural schematic diagram of the charge and discharge circuit and the resistance shunt circuit, as shown in fig. 4.
Referring to fig. 4, the capacitor charging and discharging circuit 101 includes: first charge and discharge circuit and second charge and discharge circuit, wherein first charge and discharge circuit includes: fourth PMOS pipe TP4, fourth NMOS pipe TN4, seventh PMOS pipe TP7 and third electric capacity C3, the second charge-discharge circuit includes: a fifth PMOS transistor TP5, a fifth NMOS transistor TN5, a seventh PMOS transistor TP7, and a fourth capacitor C4, wherein the resistor shunt circuit 102 includes: a second resistor R2 and a sixth PMOS transistor TP6, wherein:
the source of the TP4, the source of the TP5, and the drain of the TP7 are all coupled to each other, the drain of the TP4, the first input a of the first comparator 1031, the drain of the TN4, and the first port of the C3 are all coupled to each other, and the gate of the TP4, the gate of the TN4, and the first output Q of the first flip-flop 1041 are all coupled to each other.
The drain of the TP5, the first input B of the second comparator 1032, the drain of the TN5, and the first port of the C4 are all coupled to each other, and the gate of the TP5, the gate of the TN5, and the output QB of the second flip-flop 1042 are all coupled to each other.
And the source electrode of the TN4, the source electrode of the TN5, the second port of the C3, the second port of the C4 and the second port of the R2 are all coupled with each other and then grounded (VSS).
The gate of TP7 is coupled to a current BIAS signal (BIAS _ OSC), and the source of TP7 is coupled to the source of TP6 and then to a power supply Voltage (VDD).
The gate of the TP6, the drain of the TP6, the first port of the R2, the second input terminal VREF _ CMP of the first comparator 1031, and the second input terminal VREF _ CMP of the second comparator 1032 are all coupled to each other.
The working principle of the charging and discharging circuit 101 and the resistance shunt circuit 102 can be referred to the description in the above embodiments, and is not described herein again.
In order to make the present invention better understood and implemented by those skilled in the art, the embodiment of the present invention provides a schematic structural diagram of a feedback loop and a trigger circuit, as shown in fig. 5.
Referring to fig. 5, the first feedback loop 1033 includes: a third inverter G1 and a fourth inverter G2, the second feedback loop 1034 including: a fifth inverter G3 and a sixth inverter G4, and the first flip-flop circuit 1041 includes: a seventh inverter G5 and a first nand gate G6, the second flip-flop circuit 1042 includes: an eighth inverter G7 and a second nand gate G8, wherein:
an input of the G5 is coupled to an output of the first comparator 1031, and an output is coupled to a first input of the G6.
A second input terminal of the G6 is coupled to the output terminal of the G8, and an output terminal of the first trigger circuit 1041 is coupled to the first input terminal of the G8 and the input terminal of the G4 respectively.
An input of the G7 is coupled to an output of the second comparator 1032, and an output is coupled to a second input of the G8.
The output terminal of G8 is the output terminal of the second trigger circuit 1042, and is coupled to the second input terminal of G6 and the input terminal of G2, respectively.
An output terminal of the G2 is coupled to an input terminal of the G1, and an output terminal of the G1 is coupled to a driving terminal of the first comparator 1031.
An output of the G4 is coupled to an input of the G3, and an output of the G3 is coupled to a driving terminal of the second comparator 1032.
The working principle of the feedback loop and the trigger circuit can refer to the description in the above embodiments, and the description is omitted here.
The present invention is implemented to enable those skilled in the art to better understand and implement the present invention, and the embodiment of the present invention provides a schematic structural diagram of a comparator, as shown in fig. 6.
Referring to fig. 6, the comparator, i.e., the first comparator 1031 or the second comparator 1032, includes: current mirror circuit 10301, pull-up circuit 10302, pull-down circuit 10303, common source amplifier circuit 10304. The current mirror circuit 10301 includes: a ninth PMOS transistor TP9, a tenth PMOS transistor TP10, an eleventh PMOS transistor TP11, a sixth NMOS transistor TN6, and a seventh NMOS transistor TN7; the common source amplifier circuit 10304 includes: a twelfth PMOS tube TP12 and an eighth NMOS tube TN8; the pull-up circuit 10302 includes: an eighth PMOS transistor TP8; the pull-down circuit 10303 includes: a first inverter (not shown), a second inverter (not shown), a ninth NMOS transistor TN9, and a tenth NMOS transistor TN10, wherein:
the gate of TP9, the drain of TP8, and the gate of TP12 are all coupled to each other and then receive a current bias signal VBIASP, the source of TP9, the source of TP8, and the source of TP12 are all coupled to each other and then receive a power supply Voltage (VDD), and the drain of TP9, the source of TP10, and the source of TP11 are all coupled to each other.
A gate VIN of the TP10 is a second input terminal of the comparator, and a drain of the TP10, a gate of the TN6, a drain of the TN6, and a gate of the TN7 are all coupled to each other.
The gate VIP of the TP11 is a first input terminal of the comparator, and the drain of the TP11, the drain of the TN7, the drain of the TN9 and the gate of the TN8 are all coupled to each other.
And the source electrode of the TN6, the source electrode of the TN7, the source electrode of the TN9, the source electrode of the TN8 and the source electrode of the TN10 are all coupled with each other and then grounded (VSS).
And the drain of the TP12, the drain of the TN8 and the drain of the TN10 are all coupled with each other and then are output terminals VOUT of the comparator.
The gate EN of the TP8 is a driving end of the comparator, and is coupled to the gate ENB of the TN9 through a first inverter and is coupled to the gate ENB of the TN10 through a second inverter.
The working principle of the comparator can be referred to the description in the above embodiments, and is not described herein again.
In order to make those skilled in the art better understand and implement the present invention, the embodiment of the present invention provides a schematic diagram of simulation results of power consumption of a rc oscillator circuit, as shown in fig. 7.
Referring to fig. 7, using the above rc oscillator circuit, icomp is an operating current of the first comparator 1031, and the first comparator 1031 is in a hold state when QB point is "0" and a point a is "0", and Icomp is "0". When the first comparator 1031 is in the comparing state, the current is gradually turned on, and the QB point outputs the correct square wave clock signal at the same time.
Since half of the current of the comparator can be reduced in the operation process of the OSC, the power consumption of the comparator circuit can be reduced, and the power consumption of the RC OSC circuit can be further reduced.
The embodiment of the invention provides a clock signal generation method, which adopts any one of the resistance-capacitance oscillator circuits to generate clock signals.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (11)

1. A resistor-capacitor oscillator circuit, comprising: electric capacity charge-discharge circuit, resistance shunting circuit, comparator circuit and RS trigger circuit, electric capacity charge-discharge circuit includes: first charge-discharge circuit and second charge-discharge circuit, the comparator circuit includes: a first comparator, a second comparator, a first feedback loop, and a second feedback loop, the RS flip-flop circuit comprising: a first flip-flop circuit and a second flip-flop circuit, wherein:
the first charging and discharging circuit is used for receiving an output signal of the first trigger circuit, generating a voltage signal and outputting the voltage signal to the first comparator; the second charging and discharging circuit is used for receiving the output signal of the second trigger circuit, generating a voltage signal and outputting the voltage signal to the second comparator;
the resistance shunt circuit is used for sharing the current of the first charge-discharge circuit and the second charge-discharge circuit, generating a reference signal and outputting the reference signal to the first comparator circuit and the second comparator circuit;
the first comparator is used for comparing output signals of the first charging and discharging circuit and the resistance shunt circuit and outputting a comparison result to the first trigger; the second comparator is used for comparing output signals of the second charging and discharging circuit and the resistance shunt circuit and outputting a comparison result to the second trigger;
the first feedback loop is used for outputting a control signal to the driving end of the first comparator when the second trigger circuit outputs a low level signal, controlling the first comparator to close the working current and outputting a low level signal; the second feedback loop is used for outputting a control signal to the driving end of the second comparator when the first trigger circuit outputs a low level signal, controlling the second comparator to close the working current and outputting a low level signal;
the first trigger circuit is used for receiving output signals of the first comparator and the second trigger, generating a clock signal and outputting the clock signal; and the second trigger circuit is used for receiving the output signals of the second comparator and the first trigger, generating a clock signal and outputting the clock signal.
2. The rc oscillator circuit of claim 1, wherein the resistor shunt circuit comprises: a resistor and a MOS tube.
3. The rc oscillator circuit of claim 2, wherein the first charging and discharging circuit comprises: first PMOS pipe, third NMOS pipe and first electric capacity, second charge-discharge circuit includes: second PMOS pipe, first NMOS pipe, third NMOS pipe and second electric capacity, resistance shunt circuit includes: a first resistor and a second NMOS transistor, wherein: the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the first port of the first resistor are coupled with each other and then connected with a power supply voltage, the drain electrode of the first PMOS tube, the source electrode of the third PMOS tube, the first port of the first capacitor and the first input end of the first comparator are coupled with each other, and the grid electrode of the first PMOS tube, the grid electrode of the third PMOS tube and the output end of the first trigger are coupled with each other;
the drain electrode of the second PMOS transistor, the drain electrode of the first NMOS transistor, the first port of the second capacitor, and the first input terminal of the second comparator are all coupled to each other, and the gate electrode of the second PMOS transistor, the gate electrode of the first NMOS transistor, and the output terminal of the second flip-flop are all coupled to each other; the drain electrode of the third PMOS tube, the source electrode of the first NMOS tube and the drain electrode of the third NMOS tube are all coupled with each other;
the gate of the third NMOS transistor, the gate of the second NMOS transistor, the drain of the second NMOS transistor, the second port of the first resistor, the second input of the first comparator, and the second input of the second comparator are all coupled to each other, and the source of the third NMOS transistor, the second port of the first capacitor, the second port of the second capacitor, and the source of the second NMOS transistor are grounded after being coupled to each other.
4. The rc oscillator circuit of claim 2, wherein the first charging and discharging circuit comprises: fourth PMOS pipe, fourth NMOS pipe, seventh PMOS pipe and third electric capacity, the second charge-discharge circuit includes: fifth PMOS pipe, fifth NMOS pipe, seventh PMOS pipe and fourth electric capacity, resistance shunt circuit includes: second resistance and sixth PMOS pipe, wherein: a source electrode of the fourth PMOS transistor, a source electrode of the fifth PMOS transistor, and a drain electrode of the seventh PMOS transistor are all coupled to each other, a drain electrode of the fourth PMOS transistor, a first input terminal of the first comparator, a drain electrode of the fourth NMOS transistor, and a first port of the third capacitor are all coupled to each other, and a gate electrode of the fourth PMOS transistor, a gate electrode of the fourth NMOS transistor, and a first output terminal of the first trigger are all coupled to each other;
a drain electrode of the fifth PMOS transistor, a first input end of the second comparator, a drain electrode of the fifth NMOS transistor, and a first port of the fourth capacitor are all coupled to each other, and a gate electrode of the fifth PMOS transistor, a gate electrode of the fifth NMOS transistor, and an output end of the second trigger are all coupled to each other;
the source electrode of the fourth NMOS transistor, the source electrode of the fifth NMOS transistor, the second port of the third capacitor, the second port of the fourth capacitor and the second port of the second resistor are all coupled with each other and then grounded;
the grid electrode of the seventh PMOS tube is coupled with a current bias signal, and the source electrode of the seventh PMOS tube is coupled with the source electrode of the sixth PMOS tube and then connected with power supply voltage;
the grid electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube, the first port of the second resistor, the second input end of the first comparator and the second input end of the second comparator are all coupled with each other.
5. The rc oscillator circuit of claim 1, wherein the comparator comprises: current mirror circuit, pull-up circuit, pull-down circuit, common source amplifier circuit, wherein:
the current mirror circuit is used for receiving output signals of the capacitor charging and discharging circuit and the resistor shunt circuit and providing current sources for the pull-up circuit, the pull-down circuit and the common-source amplifier circuit;
the common source amplifier circuit is used for comparing and amplifying voltage signals and outputting the voltage signals to the RS trigger circuit;
the pull-up circuit is used for receiving a control signal of the feedback loop and cutting off the working current;
and the pull-down circuit is used for receiving the reverse control signal of the feedback loop when the pull-up circuit cuts off the working current and controlling the common-source amplifier circuit to output a low-voltage signal.
6. The RC oscillator circuit of claim 5, wherein the current mirror circuit comprises: a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, wherein:
the grid electrode of the ninth PMOS tube, the pull-up circuit and the common source amplifier circuit are coupled with each other and then are connected with a current bias signal, the source electrode of the ninth PMOS tube, the pull-up circuit and the common source amplifier circuit are coupled with each other and then are connected with a power supply voltage, and the drain electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are coupled with each other;
a grid electrode of the tenth PMOS tube is a second input end of the comparator, and a drain electrode of the tenth PMOS tube, a grid electrode of the sixth NMOS tube, a drain electrode of the sixth NMOS tube and a grid electrode of the seventh NMOS tube are all coupled with each other;
the grid electrode of the eleventh PMOS tube is a first input end of the comparator, and the drain electrode of the eleventh PMOS tube, the drain electrode of the seventh NMOS tube, the pull-down circuit and the common source amplifier circuit are all coupled with each other;
and the source electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube, the pull-down circuit and the common source amplifier circuit are grounded after being coupled with each other.
7. The resistor-capacitor oscillator circuit of claim 6, wherein the common source amplifier circuit comprises: a twelfth PMOS tube and an eighth NMOS tube, wherein:
the source electrode of the twelfth PMOS tube, the source electrode of the ninth PMOS tube and the pull-up circuit are coupled with each other and then connected with a power supply voltage, the grid electrode of the twelfth PMOS tube, the grid electrode of the ninth PMOS tube and the pull-up circuit are coupled with each other and then connected with a bias current signal, and the drain electrode of the twelfth PMOS tube, the drain electrode of the eighth NMOS tube and the pull-down circuit are coupled with each other and then are output ends of the comparators;
the grid electrode of the eighth NMOS transistor, the drain electrode of the eleventh PMOS transistor, the drain electrode of the seventh NMOS transistor and the pull-down circuit are all coupled with each other, and the source electrode of the eighth NMOS transistor, the source electrode of the seventh NMOS transistor, the source electrode of the sixth NMOS transistor and the pull-down circuit are grounded after being coupled with each other;
the drain electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are all coupled with each other;
a grid electrode of the tenth PMOS transistor is a second input end of the comparator, and a drain electrode of the tenth PMOS transistor, a grid electrode of the sixth NMOS transistor, a drain electrode of the sixth NMOS transistor, and a grid electrode of the seventh NMOS transistor are all coupled to each other;
and the grid electrode of the eleventh PMOS tube is a first input end of the comparator.
8. The RC oscillator circuit of claim 7, wherein the pull-up circuit comprises: an eighth PMOS transistor, the pull-down circuit comprising: the first phase inverter, the second phase inverter, the ninth NMOS pipe and the tenth NMOS pipe, wherein:
a grid electrode of the ninth PMOS tube, a drain electrode of the eighth PMOS tube and a grid electrode of the twelfth PMOS tube are coupled with each other and then are connected with a current bias signal, a source electrode of the ninth PMOS tube, a source electrode of the eighth PMOS tube and a source electrode of the twelfth PMOS tube are coupled with each other and then are connected with a power supply voltage, and a drain electrode of the ninth PMOS tube, a source electrode of the tenth PMOS tube and a source electrode of the eleventh PMOS tube are coupled with each other;
a grid electrode of the tenth PMOS transistor is a second input end of the comparator, and a drain electrode of the tenth PMOS transistor, a grid electrode of the sixth NMOS transistor, a drain electrode of the sixth NMOS transistor, and a grid electrode of the seventh NMOS transistor are all coupled to each other;
a grid electrode of the eleventh PMOS tube is a first input end of the comparator, and a drain electrode of the eleventh PMOS tube, a drain electrode of the seventh NMOS tube, a drain electrode of the ninth NMOS tube and a grid electrode of the eighth NMOS tube are all coupled with each other;
the source electrode of the sixth NMOS transistor, the source electrode of the seventh NMOS transistor, the source electrode of the ninth NMOS transistor, the source electrode of the eighth NMOS transistor and the source electrode of the tenth NMOS transistor are grounded after being coupled with each other;
the drain electrode of the twelfth PMOS tube, the drain electrode of the eighth NMOS tube and the drain electrode of the tenth NMOS tube are coupled with each other and then are output ends of the comparator;
the grid electrode of the eighth PMOS tube is a driving end of the comparator, and is coupled with the grid electrode ENB of the ninth NMOS tube through a first phase inverter and is coupled with the grid electrode of the tenth NMOS tube through a second phase inverter.
9. A rc oscillator circuit as claimed in any one of claims 1 to 8, wherein the feedback loop comprises: n inverters coupled to each other, wherein N is zero or a positive even number.
10. The rc oscillator circuit of claim 9, wherein the first feedback loop comprises: a third inverter and a fourth inverter, the second feedback loop comprising: a fifth inverter and a sixth inverter, the first flip-flop circuit comprising: a seventh inverter and a first nand gate, the second flip-flop circuit comprising: an eighth inverter and a second nand gate, wherein:
an input end of the seventh inverter is coupled to the output end of the first comparator, and an output end of the seventh inverter is coupled to the first input end of the first nand gate;
the second input end of the first nand gate is coupled to the output end of the second nand gate, and the output end of the first nand gate is the output end of the first flip-flop circuit and is coupled to the first input end of the second nand gate and the input end of the sixth inverter respectively;
an input end of the eighth inverter is coupled to the output end of the second comparator, and an output end of the eighth inverter is coupled to the second input end of the second nand gate;
the output end of the second nand gate is the output end of the second flip-flop circuit and is respectively coupled with the second input end of the first nand gate and the input end of the fourth inverter;
the output end of the fourth inverter is coupled with the input end of the third inverter, and the output end of the third inverter is coupled with the driving end of the first comparator;
an output end of the sixth inverter is coupled to an input end of the fifth inverter, and an output end of the fifth inverter is coupled to a driving end of the second comparator.
11. A method of generating a clock signal, using the rc oscillator circuit of any of claims 1 to 10 to generate the clock signal.
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