CN111200360B - Switch capacitor converter system based on lithium battery SOC uses - Google Patents

Switch capacitor converter system based on lithium battery SOC uses Download PDF

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CN111200360B
CN111200360B CN201811386301.7A CN201811386301A CN111200360B CN 111200360 B CN111200360 B CN 111200360B CN 201811386301 A CN201811386301 A CN 201811386301A CN 111200360 B CN111200360 B CN 111200360B
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tube
nmos tube
electrode
nmos
twenty
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CN111200360A (en
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杨建新
胡胜发
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Guangzhou Ankai Microelectronics Co.,Ltd.
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Anyka Guangzhou Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a switched capacitor converter system based on lithium battery SOC application, which comprises a voltage conversion proportion selection module, a VOUT generation module, a VOUT2 generation module, a VSSH generation module, a configuration output voltage module, an error amplifier, a VCO loop control module and a driving and switched capacitor power sub-circuit. The invention realizes wide-range voltage input, can efficiently configure the dual-mode gain topology, effectively avoids the dead zone circuit control condition of misconduction, greatly reduces the loss and finishes stable digital configurable voltage output. In addition, the VOUT generation module can ensure the stability of output during starting and transient change by introducing the LDO with the specific mismatch operational amplifier, and overcomes the defect that a control loop cannot regulate and control. The invention can be widely applied to converter structures.

Description

Switch capacitor converter system based on lithium battery SOC uses
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a switched capacitor converter system based on lithium battery SOC application.
Background
The lithium battery is a main energy source of the mobile device, the voltage range of the currently commonly used lithium battery is 2.9V-4.2V, and is normally 3.6V, however, the supply voltage applied by the processor and the SOC is often required to be as low as about 1V, and in order to solve the problem of voltage difference, the on-chip fully integrated voltage regulator is very important. Because the integration level of the inductance of the key element in the inductance type switching voltage converter is low, in the CMOS process, the existing process is difficult to manufacture a larger inductance to meet the requirement.
However, in the design of the present switched capacitor converter system for the SOC application based on the lithium battery, there are several problems as follows:
1. low power applications, require the provision of configurable output voltages. Increasing the endurance time of the mobile device is often a key point of attention, in order to prolong the service life of the battery and efficiently use energy, the power supply voltage of the internal module needs to be regulated and controlled in real time according to an application scene, for example, in order to achieve low power consumption in standby application, the digital core voltage of the SOC is 1.1V in normal operation, and a lower core voltage of-0.9V needs to be provided in standby. Therefore, the voltage conversion of the system-integrated switch capacitor converter needs to be configurable, and the voltage output is configured by a digital register, such as 1.1V or 0.9V output, and even more other voltage nodes.
2. When the power tubes in the topological structure are switched, the power tubes are likely to be conducted simultaneously, so that large current loss is easily caused at a moment, and the power tubes are also likely to be broken down. In order to improve the efficiency and stability, dead zone control for avoiding misconduction is introduced, and the defect that the delay of a non-overlapping circuit is fixed and cannot be adjusted is overcome.
3. Since the supply input is a lithium battery, the battery voltage range varies between 2.9V and 4.2V, and if only a single gain topology is used, a situation of low efficiency occurs at a part of the supply voltage.
4. When starting or when the load changes greatly, the error signal has the possibility of being in a limit value, and under the condition that the control loop is in a maladjustment state, a complex VCO loop control module is often required to be introduced, so that the complexity of the design is increased, but the risk of the loop being out of control still exists; therefore, the LDO is introduced during starting, a threshold voltage is provided for whether the LDO is started or not by setting specific mismatch of an internal operational amplifier, introduction of a comparator is omitted, complexity of a VCO loop control module is reduced, stability of output starting and transient change is guaranteed, and the condition that the VCO cannot be regulated is compensated.
5. The loop control of the switched capacitor converter controlled by a single clock signal is complex, when a compensation capacitor and a resistor are introduced to provide loop compensation, the transient response is poor under a certain switching frequency, and the conditions of large ripple and low efficiency exist; for SOC applications, such as high voltage sensitivity of the digital core, less ripple is required, and efficiency and transient response are improved as much as possible.
Disclosure of Invention
In order to solve the above technical problems, the present invention is directed to a switched capacitor converter system based on a lithium battery SOC application.
The technical scheme adopted by the invention is as follows:
a switched capacitor converter system based on lithium battery SOC application comprises a voltage conversion ratio selection module, a VOUT generation module, a VOUT2 generation module, a VSSH generation module, a configuration output voltage module, an error amplifier, a VCO loop control module and a driving and switched capacitor power sub-circuit, wherein the output end of the voltage conversion ratio selection module is connected with the first input end of the driving and switched capacitor power sub-circuit, the output end of the VOUT generation module is connected with the second input end of the driving and switched capacitor power sub-circuit, the output end of the VOUT2 generation module is connected with the third input end of the driving and switched capacitor power sub-circuit, the output end of the VSSH generation module is connected with the fourth input end of the driving and switched capacitor power sub-circuit, the output end of the configuration output voltage module is respectively connected with the positive input end of the error amplifier, the input end of the VOUT generation module and the input end of the VOUT2 generation module, the output end of the error amplifier is connected with the input end of the VCO loop control module, the output end of the VCO loop control module is connected with the fifth input end of the driving and switching capacitor power sub-circuit, and the first output end of the driving and switching capacitor power sub-circuit is connected with the negative input end of the error amplifier.
As a further improvement of the present invention, the output voltage configuration module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first capacitor, a first resistor, a second resistor, a third resistor, a first inverter, a second inverter, a third inverter, and a fourth inverter, wherein a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor, and a drain of the seventh NMOS transistor are all connected to a power supply terminal, a gate of the first PMOS transistor is connected to a gate of the second PMOS transistor, a drain of the first PMOS transistor, a drain of the third PMOS transistor, and a drain of the first NMOS transistor, and a drain of the second PMOS transistor is connected to a gate of the seventh NMOS transistor, a drain of the second NMOS transistor, and a drain of the eighth NMOS transistor, the source electrode of the first NMOS tube is respectively connected with the source electrode of the second NMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the first NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is respectively connected with the source electrode of the fifth NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the sixth NMOS tube, the grid electrode of the sixth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the ninth NMOS tube, the drain electrode of the second PMOS tube is further connected with the ground through a first capacitor, the grid electrode of the second NMOS tube is respectively connected with the source electrode of the seventh NMOS tube, the source electrode of the eighth NMOS tube and the drain electrode of the ninth NMOS tube, the output end of the first phase inverter is connected with the grid electrode of the eighth NMOS tube, the source electrode of the seventh NMOS tube is further connected with the source electrode of the fourth PMOS tube through a first resistor, and the source electrode of the fourth PMOS tube is further connected with the source electrode of the fifth NMOS tube through a second resistor, the source electrode of the fifth PMOS tube is further connected with the ground through a third resistor, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube, the output end of the fourth phase inverter is connected with the grid electrode of the fifth PMOS tube, the grid electrode of the fourth PMOS tube is respectively connected with the output end of the third phase inverter and the input end of the fourth phase inverter, the output end of the second phase inverter is connected with the input end of the third phase inverter, the drain electrode of the fifth PMOS tube is connected with the positive electrode input end of the error amplifier, and the drain electrode of the fourth NMOS tube, the source electrode of the third NMOS tube and the source electrode of the ninth NMOS tube are all connected with the ground.
As a further improvement of the present invention, the VOUT2 generation module includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a fifty-sixth NMOS transistor, a twelfth PMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, a second capacitor, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, and a twelfth inverter, a source of the sixth PMOS transistor and a source of the eighth PMOS transistor are both connected to a power supply terminal, a drain of the sixth PMOS transistor is connected to a drain of the tenth NMOS transistor and a gate of the eighth PMOS transistor, a source of the tenth NMOS transistor is connected to a drain of the eleventh NMOS transistor, and a gate of the sixth PMOS transistor is connected to a gate of the eleventh NMOS transistor, a gate of the eleventh PMOS transistor and a second capacitor, a fifth capacitor, a tenth inverter, a fifteenth inverter, a sixth, A gate of a seventh PMOS transistor, a gate of a thirteenth NMOS transistor, an output terminal of a sixth inverter, and an input terminal of a seventh inverter, wherein a source of the seventh PMOS transistor is connected to a power source, a drain of the seventh PMOS transistor is connected to a source of a twelfth NMOS transistor, a drain of the twelfth NMOS transistor is connected to a drain of the thirteenth NMOS transistor and a gate of the fourteenth NMOS transistor, a gate of the twelfth NMOS transistor is connected to a gate of the tenth NMOS transistor and an output terminal of the eighth inverter, a source of the thirteenth NMOS transistor is connected to a source of the fourteenth NMOS transistor, a source of the ninth PMOS transistor, a source of the twelfth PMOS transistor, and a third input terminal of the driving and switching capacitor power sub-circuit, a drain of the eighth PMOS transistor is connected to a drain of the fourteenth NMOS transistor, a drain of the eighth PMOS transistor is connected to a drain of the fifteenth NMOS transistor through a second capacitor, and a drain of the fifteenth NMOS transistor is connected to a drain of the ninth PMOS transistor, a drain of the fifteenth NMOS transistor, A grid electrode of a tenth PMOS tube is connected with a grid electrode of a fifty-sixth NMOS tube, a source electrode of the fifteenth NMOS tube and a source electrode of the sixteenth NMOS tube are both connected with the ground, a grid electrode of the fifteenth NMOS tube is respectively connected with a drain electrode of the sixteenth NMOS tube and a drain electrode of the tenth PMOS tube, a source electrode of the tenth PMOS tube is connected with a drain electrode of the eleventh PMOS tube, a source electrode of the seventeenth NMOS tube is connected with the ground, a drain electrode of the seventeenth NMOS tube is connected with a source electrode of the fifty-sixth NMOS tube, a grid electrode of the ninth PMOS tube is respectively connected with a drain electrode of the fifty-sixth NMOS tube and a drain electrode of the twelfth PMOS tube, a grid electrode of the sixteenth PMOS tube is respectively connected with a grid electrode of the eleventh PMOS tube, a grid electrode of the seventeenth NMOS tube and a grid electrode of the twelfth NMOS tube, the first path of clock signal is further connected with an input end of the sixth phase inverter through the fifth phase inverter, and an output end of the seventh phase, and the second path of clock signals sequentially passes through the ninth phase inverter, the tenth phase inverter, the eleventh phase inverter and the twelfth phase inverter and is further connected with the grid electrode of the twelfth PMOS tube, and the source electrode of the eleventh NMOS tube and the source electrode of the eleventh PMOS tube are both connected with the third input end of the driving and switched capacitor power sub-circuit.
As a further improvement of the present invention, the voltage conversion ratio selection module includes a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a fourth resistor, a fifth resistor, and a thirteenth inverter, wherein a source of the fourteenth PMOS transistor, a source of the fifteenth PMOS transistor, a source of the sixteenth PMOS transistor, a source of the seventeenth PMOS transistor, a source of the eighteenth PMOS transistor, a source of the nineteenth PMOS transistor, a source of the twentieth PMOS transistor, and a source of the twenty-first PMOS transistor are all connected to the power supply terminal, and a drain of the fourteenth PMOS transistor is further connected to a gate of the eighteenth NMOS transistor through the fourth resistor, the drain electrode of the eighteenth NMOS tube is respectively connected with the drain electrode of the fifteenth PMOS tube, the drain electrode of the sixteenth PMOS tube, the gate electrode of the seventeenth PMOS tube and the drain electrode of the eighteenth PMOS tube, the drain electrode of the nineteenth NMOS tube is respectively connected with the drain electrode of the seventeenth PMOS tube, the gate electrode of the eighteenth PMOS tube, the drain electrode of the nineteenth PMOS tube, the drain electrode of the twentieth PMOS tube and the gate electrode of the twenty-first PMOS tube, the drain electrode of the twenty-first PMOS tube is respectively connected with the drain electrode of the twenty-fifth NMOS tube, the drain electrode of the twenty-sixth NMOS tube and the first input end of the driving and switching capacitor power sub-circuit, the gate electrode of the eighteenth NMOS tube is connected with the gate electrode of the twentieth NMOS tube, the gate electrode of the eighteenth NMOS tube is further connected with the source electrode of the twenty-first NMOS tube through a fifth resistor, and the source electrode of the eighteenth NMOS tube is respectively connected with the source electrode of the nineteenth NMOS tube, the source electrode of the twenty-second NMOS tube is connected with the source electrode of the twentieth NMOS tube, the drain electrode of the twentieth NMOS tube and the source electrode of the twenty-first NMOS tube respectively, the grid electrode of the twenty-first NMOS tube is connected with the grid electrode of the twenty-second NMOS tube, the grid electrode of the twenty-third NMOS tube, the drain electrode of the twenty-fourth NMOS tube and the grid electrode of the twenty-sixth NMOS tube respectively, the grid electrode of the twenty-fourth NMOS tube is connected with the grid electrode of the twenty-fifth NMOS tube, the drain electrode of the twenty-second NMOS tube, the source electrode of the twenty-third NMOS tube, the source electrode of the twenty-fourth NMOS tube, the source electrode of the twenty-fifth NMOS tube and the source electrode of the twenty-sixth NMOS tube are all connected with the ground, the output end of the thirteenth phase inverter is connected with the grid electrode of the fifteenth PMOS tube and the grid electrode of the twenty-PMOS tube respectively, and the grid electrode of the nineteen.
As a further improvement of the present invention, the VOUT generation module includes a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirty-eleventh NMOS transistor, a thirty-second NMOS transistor, a thirty-third NMOS transistor, a thirty-fourth NMOS transistor, a thirty-fifth NMOS transistor, a fourth capacitor, a fifth capacitor, and a fourteenth inverter, a source of the twenty-second PMOS transistor, a source of the twenty-third PMOS transistor, a source of the twenty-fourth PMOS transistor, and a drain of the twenty-ninth NMOS transistor are all connected to a power supply terminal, a drain of the twenty-seventh NMOS transistor is connected to a drain of the twenty-second PMOS transistor, a gate of the twenty-third PMOS transistor, and a drain of the twenty-fourth PMOS transistor, respectively, a drain of the twenty-third PMOS transistor is connected to a drain of the twenty-eighth NMOS transistor and a gate of the twenty-ninth NMOS transistor, the drain electrode of the thirty-third NMOS tube is respectively connected with the source electrode of the twenty-seventh NMOS tube and the source electrode of the twenty-eighth NMOS tube, the drain electrode of the twenty-third PMOS tube is further connected with the source electrode of the thirty-third NMOS tube through a fifth capacitor, the gate electrode of the twenty-seventh NMOS tube is respectively connected with the gate electrode of the thirty-NMOS tube and the output end of the configuration output voltage module, the source electrode of the thirty-NMOS tube is respectively connected with the drain electrode of the thirty-NMOS tube, the source electrode of the thirty-eleventh NMOS tube and the source electrode of the thirty-second NMOS tube, the gate electrode of the thirty-eleventh NMOS tube is respectively connected with the gate electrode of the thirty-second NMOS tube, the gate electrode of the thirty-third NMOS tube and the gate electrode of the thirty-fourth NMOS tube, the drain electrode of the thirty-second NMOS tube is connected with the source electrode of the thirty-fifth NMOS tube, and the drain electrode of the thirty-fourth NMOS tube is connected with the source electrode of the thirty-fifth NMOS tube, the grid electrode of the thirty-fifth NMOS tube is connected with the output end of the fourteenth phase inverter, the source electrode of the twenty-ninth NMOS tube is further connected with the source electrode of the thirty-fifth NMOS tube through a fourth capacitor, and the source electrode of the twenty-ninth NMOS tube is respectively connected with the grid electrode of the twenty-eighth NMOS tube, the drain electrode of the thirty-fourth NMOS tube, the drain electrode of the thirty-fifth NMOS tube and the second input end of the driving and switching capacitor power sub-circuit.
As a further improvement of the present invention, the VCO loop control module includes a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, a thirty-sixth NMOS transistor, a sixth resistor, and a ring oscillator, wherein a source of the twenty-fifth PMOS transistor is connected to a source of the twenty-sixth PMOS transistor, a drain of the twenty-fifth PMOS transistor is connected to a gate of the twenty-fifth PMOS transistor, a gate of the twenty-sixth PMOS transistor, and a drain of the thirty-sixth NMOS transistor, respectively, a source of the thirty-sixth NMOS transistor is connected to ground through the sixth resistor, an output terminal of the error amplifier is connected to the gate of the thirty-sixth NMOS transistor, and a drain of the twenty-sixth PMOS transistor is connected to the ring oscillator.
As a further improvement of the present invention, the error amplifier includes a twenty-seventh PMOS transistor, a twenty-eighth PMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a forty-first NMOS transistor, a forty-second NMOS transistor, a forty-third NMOS transistor, a forty-fourth NMOS transistor, a forty-fifth NMOS transistor, and a forty-sixth NMOS transistor, wherein the source of the twenty-seventh PMOS transistor, the source of the twenty-eighth PMOS transistor, the drain of the thirty-ninth NMOS transistor, and the drain of the forty-fifth NMOS transistor are all connected to a power supply terminal, the drain of the twenty-seventh PMOS transistor is connected to the gate of the twenty-seventh PMOS transistor, the gate of the twenty-eighth PMOS transistor, and the drain of the thirty-seventh NMOS transistor, the drain of the twenty-eighth PMOS transistor is connected to the drain of the thirty-eighth NMOS transistor, the gate of the thirty-ninth NMOS transistor, and the drain of the forty-NMOS transistor, and the drain of the thirty-eighth NMOS transistor are connected to the drain of the thirty-seventh PMOS transistor, the source electrode of the forty-first NMOS transistor is connected with the source electrode of the forty-twelfth NMOS transistor, the grid electrode of the forty-first NMOS transistor is respectively connected with the grid electrode of the forty-second NMOS transistor, the grid electrode of the forty-third NMOS transistor, the grid electrode of the forty-fourth NMOS transistor and the grid electrode of the forty-sixth NMOS transistor, the source electrode of the thirty-ninth NMOS transistor is respectively connected with the gate electrode of the forty-fifth NMOS transistor and the drain electrode of the forty-fourth NMOS transistor, the source electrode of the forty-fifth NMOS transistor is respectively connected with the drain electrode of the forty-sixth NMOS transistor and the input end of the VCO loop control module, the grid of the thirty-seventh NMOS transistor is connected with the output end of the output voltage configuration module, the grid of the thirty-eighth NMOS transistor is connected with the first output end of the driving and switching capacitor power sub-circuit, the drain electrode of the forty-second NMOS transistor, the source electrode of the forty-third NMOS transistor, the source electrode of the forty-fourth NMOS transistor, the source electrode of the forty-sixth NMOS transistor and the source electrode of the forty-NMOS transistor are all connected with the ground.
As a further improvement of the present invention, the driving and switching capacitor power sub-circuit includes a twenty-ninth PMOS transistor, a thirty-sixth PMOS transistor, a thirty-third PMOS transistor, a thirty-fourth PMOS transistor, a forty-seventh NMOS transistor, a forty-eighth NMOS transistor, a forty-ninth NMOS transistor, a fifty-fifth NMOS transistor, a fifty-second NMOS transistor, a fifty-third NMOS transistor, a fifty-fourth NMOS transistor, a fifty-fifth NMOS transistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a first and gate, a second and gate, a third and gate, and a fifteenth inverter, wherein a source of the twenty-ninth PMOS transistor is connected to a power source, a drain of the twenty-ninth PMOS transistor is connected to a source of the seventeenth NMOS transistor, a drain of the twenty-ninth PMOS transistor is further connected to a forty-ninth PMOS transistor through the sixth capacitor, a drain of the forty-ninth NMOS transistor is connected to a source of the thirty-third PMOS transistor, the drain electrode of the forty-seventh NMOS transistor is respectively connected with the drain electrode of a forty-eighth NMOS transistor, the drain electrode of a fifty-first NMOS transistor, the source electrode of a fifty-second NMOS transistor, the drain electrode of a thirty-eleventh PMOS transistor and the drain electrode of a thirty-second PMOS transistor, the source electrode of the forty-eighth NMOS transistor is connected with the drain electrode of the thirty-fourth PMOS transistor, the source electrode of the forty-eighth NMOS transistor is further connected with the drain electrode of the fifty-NMOS transistor through a seventh capacitor, the source electrode of the thirty-PMOS transistor is connected with the power supply terminal, the drain electrode of the fifty-NMOS transistor is connected with the source electrode of the thirty-fourth PMOS transistor, the drain electrode of the thirty-third PMOS transistor is respectively connected with the source electrode of the fifty-first NMOS transistor and the source electrode of the fifty-fifth NMOS transistor, the drain electrode of the fifty-third PMOS transistor is further connected with the drain electrode of the fifty-third NMOS transistor through an eighth capacitor, the drain electrode of the third NMOS transistor is connected with the source electrode of the thirty-fourth PMOS transistor through a ninth capacitor, the drain electrode of the fifty-fourth NMOS tube is respectively connected with the drain electrode of the fifty-fifth NMOS tube and the source electrode of the thirty-second PMOS tube, the output end of the first AND gate is connected with the gate electrode of the fifty-first NMOS tube, the output end of the fifteenth inverter is connected with the first input end of the second AND gate, the output end of the second AND gate is connected with the gate electrode of the fifty-fifth NMOS tube, the output end of the third AND gate is connected with the gate electrode of the fifty-fourth NMOS tube, and the source electrode of the fifty-fourth NMOS tube, the source electrode of the fifty-third NMOS tube and the source electrode of the fifty-fourth NMOS tube are all connected with the ground.
The invention has the beneficial effects that:
the switched capacitor converter system based on the lithium battery SOC application realizes wide-range voltage input, can efficiently configure a dual-mode gain topology, effectively avoids dead zone circuit control conditions of misconduction, greatly reduces loss, and completes stable digital configurable voltage output. In addition, the VOUT generation module can ensure the stability of output during starting and transient change by introducing the LDO with the specific mismatch operational amplifier, and overcomes the defect that a control loop cannot regulate and control.
Furthermore, the invention also simplifies error signal generation and loop control, and drives the switched capacitor power sub-circuit unit module through the 15-phase clock control signal, thereby reducing ripple waves and improving efficiency.
Drawings
FIG. 1 is a schematic diagram of a switched capacitor converter system based on a lithium battery SOC application according to the present invention;
FIG. 2 is a schematic circuit diagram of a switched capacitor converter system configured with an output voltage module for a lithium battery SOC application according to the present invention;
FIG. 3 is a schematic circuit diagram of a VOUT2 generation module in a switched capacitor converter system based on lithium battery SOC applications according to the present invention;
FIG. 4 is a schematic circuit diagram of a voltage conversion ratio selection module in a switched capacitor converter system based on lithium battery SOC applications in accordance with the present invention;
FIG. 5 is a schematic circuit diagram of a VOUT generation module in a switched capacitor converter system for lithium battery SOC based applications in accordance with the present invention;
FIG. 6 is a schematic circuit diagram of a VCO loop control module in a switched capacitor converter system based on lithium battery SOC applications in accordance with the present invention;
FIG. 7 is a schematic circuit diagram of an error amplifier in a switched capacitor converter system based on lithium battery SOC applications in accordance with the present invention;
FIG. 8 is a schematic circuit diagram of the drive and switched capacitor power sub-circuits of a switched capacitor converter system based on lithium battery SOC applications in accordance with the present invention;
FIG. 9 is a schematic diagram of the dual mode configuration of the drive and switched capacitor power sub-circuits of a switched capacitor converter system based on lithium battery SOC applications in accordance with the present invention;
fig. 10 is a schematic illustration of the operating efficiency of the dual mode configuration of the drive and switched capacitor power sub-circuits in a switched capacitor converter system based on lithium battery SOC applications in accordance with the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the accompanying drawings:
referring to fig. 1, the present invention relates to a switched capacitor converter system based on SOC application of a lithium battery, and the system comprises a voltage conversion ratio selection module, a VOUT generation module, a VOUT2 generation module, a VSSH generation module, a configured output voltage module, an error amplifier, a VCO loop control module, and a driving and switched capacitor power sub-circuit, wherein an output terminal of the voltage conversion ratio selection module is connected to a first input terminal of the driving and switched capacitor power sub-circuit, an output terminal of the VOUT generation module is connected to a second input terminal of the driving and switched capacitor power sub-circuit, an output terminal of the VOUT2 generation module is connected to a third input terminal of the driving and switched capacitor power sub-circuit, an output terminal of the VSSH generation module is connected to a fourth input terminal of the driving and switched capacitor power sub-circuit, and output terminals of the configured output voltage module are respectively connected to a positive input terminal of the error amplifier, and, The input end of the VOUT generation module is connected with the input end of the VOUT2 generation module, the output end of the error amplifier is connected with the input end of the VCO loop control module, the output end of the VCO loop control module is connected with the fifth input end of the driving and switching capacitor power sub-circuit, and the first output end of the driving and switching capacitor power sub-circuit is connected with the negative input end of the error amplifier.
Referring to fig. 2, as a further preferred embodiment, the output voltage module includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N2, a fourth NMOS transistor N2, a fifth NMOS transistor N2, a sixth NMOS transistor N2, a seventh NMOS transistor N2, an eighth NMOS transistor N2, a ninth NMOS transistor N2, a first capacitor C2, a first resistor R2, a second resistor R2, a third resistor R2, a first inverter I2, a second inverter I2, a third inverter I2 and a fourth inverter I2, wherein a source of the first PMOS transistor P2, a source of the second PMOS transistor P2, a source of the third PMOS transistor P2, a source of the seventh PMOS transistor P2 and a drain of the first NMOS transistor P2 are connected to a gate of the first PMOS transistor P2, a drain of the first PMOS transistor P2 and a drain of the first power source of the first PMOS transistor P2, a drain of the first PMOS transistor P2, the drain of the second PMOS transistor P2 is connected to the gate of the seventh NMOS transistor N7, the drain of the second NMOS transistor N2 and the drain of the eighth NMOS transistor N8, the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and the drain of the third NMOS transistor N3, the gate of the first NMOS transistor N1 is connected to the gate of the fifth NMOS transistor N5, the drain of the fifth NMOS transistor N5 is connected to the source of the fifth NMOS transistor N5, the source of the fourth NMOS transistor N4 and the source of the sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6 is connected to the gate of the fourth NMOS transistor N4, the gate of the third NMOS transistor N3 and the gate of the ninth NMOS transistor N9, the drain of the second PMOS transistor P2 is further connected to ground through a first capacitor C1, the drain of the second PMOS transistor N53 is connected to the source of the seventh NMOS transistor N8427, the source of the seventh NMOS transistor N7, the drain of the eighth NMOS transistor N7 and the drain of the eighth NMOS transistor N8658, the source of the seventh NMOS transistor N7 is further connected to the source of the fourth PMOS transistor P4 through the first resistor R1, the source electrode of the fourth PMOS transistor P4 is further connected to the source electrode of the fifth PMOS transistor P5 through the second resistor R2, the source electrode of the fifth PMOS pipe P5 is further connected with the ground through a third resistor R3, the drain electrode of the fourth PMOS pipe P4 is connected with the drain electrode of the fifth PMOS pipe P5, the output end of the fourth inverter I4 is connected with the gate of a fifth PMOS tube P5, the gate of the fourth PMOS tube P4 is respectively connected with the output end of the third inverter I3 and the input end of the fourth inverter I4, the output end of the second inverter I2 is connected with the input end of a third inverter I3, the drain electrode of the fifth PMOS pipe P5 is connected with the positive input end of the error amplifier, the drain electrode of the fourth NMOS transistor N4, the source electrode of the third NMOS transistor N3 and the source electrode of the ninth NMOS transistor N9 are all connected with the ground.
In the embodiment, the switch is controlled by the selection signal VOUT _ SEL to selectively conduct the corresponding reference voltage; through the feedback of the operational amplifier, the output value follows the input VREF voltage value, and the output voltage is divided through a resistor to obtain a required reference voltage value; the select switch is turned on via the select signal VOUT _ SEL to configure the output voltage reference, and thus the voltage output. The ENABLE signal is an ENABLE signal, when the ENABLE signal is at a high level, the output voltage configuration module normally operates, when the ENABLE signal is at a low level, the eighth NMOS transistor N8 is turned on, the gate and the source of the seventh NMOS transistor N7 are pulled down to the ground through the voltage dividing resistor, the drain of the first PMOS transistor P1 is pulled up to the power supply terminal VDDIN through the third PMOS transistor P3, and the whole circuit does not operate.
Referring to fig. 3, as a further preferred embodiment, the VOUT2 generating module includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a fifty-sixth NMOS transistor N11, a twelfth PMOS transistor P11, a tenth NMOS transistor N11, an eleventh NMOS transistor N11, a twelfth NMOS transistor N11, a thirteenth NMOS transistor N11, a fourteenth NMOS transistor N11, a fifteenth NMOS transistor N11, a sixteenth NMOS transistor N11, a seventeenth NMOS transistor N11, a second capacitor C11, a third capacitor, a fifth inverter I11, a sixth inverter I11, a seventh inverter I11, an eighth inverter I11, a ninth inverter I11, a tenth inverter I11, an eleventh inverter I11, and a twelfth inverter I11, wherein the source of the sixth PMOS transistor P11 and the eighth drain of the eighth NMOS transistor P11 are connected to the drain of the source of the sixth PMOS transistor P11, the eighth PMOS transistor P11 and the drain of the eighth NMOS transistor P11, respectively, a source of the tenth NMOS transistor N10 is connected to a drain of an eleventh NMOS transistor N11, a gate of the sixth PMOS transistor P6 is connected to a gate of the eleventh NMOS transistor N11, a gate of the seventh PMOS transistor P7, a gate of the thirteenth NMOS transistor N13, an output of the sixth inverter I6 and an input of the seventh inverter I7, respectively, a source of the seventh PMOS transistor P7 is connected to a power source, a drain of the seventh PMOS transistor P7 is connected to a source of the twelfth NMOS transistor N12, a drain of the twelfth NMOS transistor N12 is connected to a drain of the thirteenth NMOS transistor N13 and a gate of the fourteenth NMOS transistor N14, a gate of the twelfth NMOS transistor N12 is connected to a gate of the tenth NMOS transistor N10 and an output of the eighth inverter I8, a source of the thirteenth NMOS transistor N13 is connected to a source of the fourteenth NMOS transistor N14, a source of the ninth NMOS transistor P2, a source of the twelfth NMOS transistor P9 6 and an input of the power switch P12, the source of the thirteenth NMOS transistor N13 is further connected to ground through a third capacitor, the drain of the eighth PMOS transistor P8 is connected to the drain of the fourteenth NMOS transistor N14, the drain of the eighth PMOS transistor P8 is further connected to the drain of the fifteenth NMOS transistor N15 through a second capacitor C2, the drain of the fifteenth NMOS transistor N15 is connected to the drain of the ninth PMOS transistor P9, the gate of the tenth PMOS transistor P10 and the gate of the fifty-sixth NMOS transistor N56, the source of the fifteenth NMOS transistor N15 and the source of the sixteenth NMOS transistor N16 are both connected to ground, the gate of the fifteenth NMOS transistor N15 is connected to the drain of the sixteenth NMOS transistor N16 and the drain of the tenth PMOS transistor P10, the source of the tenth PMOS transistor P10 is connected to the eleventh PMOS transistor P375, the drain of the seventeenth NMOS transistor N17 is connected to ground, the drain of the seventeenth NMOS transistor N17 is connected to the drain of the sixth NMOS transistor N56, the drain of the ninth NMOS transistor N599 and the ninth NMOS transistor N9, the gate of the sixteenth NMOS transistor N16 is connected to the gate of an eleventh PMOS transistor P11, the gate of a seventeenth NMOS transistor N17, and the gate of a twelfth PMOS transistor P12, the first path of clock signal is connected to the input terminal of a sixth inverter I6 through a fifth inverter I5, the output terminal of the seventh inverter I7 is connected to the input terminal of an eighth inverter I8, the second path of clock signal is connected to the gate of the twelfth PMOS transistor P12 through a ninth inverter I9, a tenth inverter I10, an eleventh inverter I11, and a twelfth inverter I12 in sequence, and the source of the eleventh NMOS transistor N11 and the source of the eleventh PMOS transistor P11 are both connected to the third input terminal of the driving and switching capacitor power sub-circuit.
In this embodiment, because the clock signal in the conventional dead-zone circuit passes through the non-overlapping generating circuit composed of the nor gate and the inverter to generate two paths of non-overlapping clock signals, the dead-zone time of the non-overlapping generating circuit is determined by the transmission delay of the inverter and the logic gate, for the non-overlapping circuit in which the number of the inverter and the logic gate is determined, the dead-zone time is determined by the transmission delay, the transmission delay is mainly determined by inherent factors such as the process, the influence of the actual process is large, the dead-zone time is too short, the misconduction can be caused, the short-circuit loss is generated, and the device is damaged; the dead time is too long, which affects the voltage conversion performance; in addition, the amplitude of the driving signal is VDDIN, the loss of the driving tube with larger amplitude is increased, and the efficiency is affected.
Therefore, in order to generate a proper dead time, the dead time is adjusted according to the working state of the circuit to avoid misconduction, the control of the power tube in the embodiment is determined by the signals A and B, and the dead time is determined by the delay of the inverter; the design of the lower power tube gets rid of the method of realizing dead time by using phase inverter delay, the conduction and the disconnection of the MOS tube are controlled by the voltage at the VCB point, the D and C control signals are provided, the loss of VOUT to the ground caused by error conduction is avoided, and the defect that the circuit performance is influenced by overlong dead time or break by using the transmission delay of the phase inverter is overcome.
The clock signals CLK1 and CLK2 are signals with the same phase, frequency and pulse width, the amplitudes of the signals are different, the high and low levels of CLK1 are VDDIN and VOUT, the high and low levels of CLK2 are VOUT and GND, the dead time of the signals A and B is determined by the transmission delay of an inverter, the amplitude of the dead time is determined by the level connected with the source ends of the left MOS transistor and the right MOS transistor, the amplitude is much smaller than that of the traditional signals, and the driving loss is reduced; when the CLK1 and the CLK2 signals are changed from low level to high level, the B signal is changed from high level to low level, the fourteenth NMOS tube N14 is turned off, the A signal is changed from high level to low level after dead time, the eighth PMOS tube P8 is turned on, and the error conduction in the switching time of the power tube is avoided. The fifteenth NMOS transistor N15 and the ninth PMOS transistor P9 are switched on and off depending on the voltage at the point VCB, when the D signal changes from high level to low level, the fifteenth NMOS transistor N15 is turned off, during which time the voltage across the second capacitor C2 begins to change, and VCB starts to rise slowly from GND to VOUT, so that the C signal changes from high level to low level, and the ninth PMOS transistor P9 begins to turn on, and starts the charging process. Similarly, when the CLK1 and the CLK2 change from high level to low level, the a signal changes from low level to high level, the eighth PMOS transistor P8 is turned off, and after the dead time, the B signal changes from low level to high level, and the fourteenth NMOS transistor N14 is turned on, thereby avoiding the simultaneous turn-on between the eighth PMOS transistor P8 and the fourteenth NMOS transistor N14 of the power transistors. At this time, the C signal is pulled high because the twelfth PMOS transistor P12 is turned on, and changes from low level to high level, the ninth PMOS transistor P9 is turned off, the voltage at the VCB point starts to drop, and the VOUT drops to GND, so that the D signal changes from low level to high level, and the fifteenth NMOS transistor N15 is turned on, and the discharging process starts. By controlling the conduction and the disconnection of the tenth PMOS pipe P10 and the fifty-sixth NMOS pipe N56 by using the voltage at the VCB point, the dead time can be properly adjusted according to the working state of the circuit, and the error conduction from VOUT to GND is avoided.
Referring to fig. 4, as a further preferred embodiment, the voltage conversion ratio selection module includes a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a twenty-first PMOS transistor P21, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, a twenty-second NMOS transistor N22, a twenty-third NMOS transistor N23, a twenty-fourth NMOS transistor N24, a twenty-fifth NMOS transistor N25, a twenty-sixth NMOS transistor N25, a fourth resistor R25, a fifth resistor R25, a thirteenth inverter I25, a source of the fourteenth PMOS transistor P25, a source of the fifteenth PMOS transistor P25, a source of the sixteenth PMOS transistor P25, a seventeenth source of the twenty-second PMOS transistor P25, a twenty-second source of the twenty-first PMOS transistor P25 and the twenty-second PMOS transistor P25 are all connected to a power supply terminal P25, the drain of the fourteenth PMOS transistor P14 is further connected to the gate of an eighteenth NMOS transistor N18 through a fourth resistor R4, the drain of the eighteenth NMOS transistor N18 is connected to the drain of the fifteenth PMOS transistor P15, the drain of the sixteenth PMOS transistor P16, the gate of the sixteenth PMOS transistor P16, the gate of the seventeenth PMOS transistor P17 and the drain of the eighteenth PMOS transistor P18, the drain of the nineteenth NMOS transistor N19 is connected to the drain of the seventeenth PMOS transistor P17, the gate of the eighteenth PMOS transistor P18, the gate of the nineteenth PMOS transistor P19, the drain of the nineteenth PMOS transistor P19, the drain of the twentieth PMOS transistor P20 and the gate of the twenty-first PMOS transistor P21, the drain of the twenty-first PMOS transistor P21 is connected to the drains of the fifteenth NMOS transistor N25, the drain of the twenty-sixth PMOS transistor N26, the first input terminal of the driving and switching capacitor power sub-circuit, and the eighteenth gate of the eighteenth NMOS transistor N18 are connected to the gate of the twenty-th PMOS transistor N20, the grid of the eighteenth NMOS transistor N18 is further connected with the source of the twenty-first NMOS transistor N21 through a fifth resistor R5, the source of the eighteenth NMOS transistor N18 is connected with the source of the nineteenth NMOS transistor N19 and the drain of the twenty-third NMOS transistor N23, the source of the twenty-second NMOS transistor N22 is connected with the source of the twentieth NMOS transistor N20, the drain of the twentieth NMOS transistor N20 and the source of the twenty-first NMOS transistor N21, the grid of the twenty-first NMOS transistor N21 is connected with the grid of the twenty-second NMOS transistor N22, the grid of the twenty-third NMOS transistor N23, the drain of the twenty-fourth NMOS transistor N24 and the grid of the twenty-sixth NMOS transistor N26, the grid of the twenty-fourth NMOS transistor N24 is connected with the grid of the twenty-fifth NMOS transistor N25, the drain of the twenty-second NMOS transistor N22, the source of the twenty-third NMOS transistor N23, the twenty-fourth NMOS transistor N375, the twenty-second NMOS transistor N26 and the source of the twenty-fifth NMOS transistor N57323 are connected with the twenty-second NMOS transistor N4624, the output end of the thirteenth inverter I13 is respectively connected to the gate of the fifteenth PMOS transistor P15 and the gate of the twentieth PMOS transistor P20, and the gate of the nineteenth NMOS transistor N19 is connected to the output end of the configuration output voltage module.
Referring to fig. 8, in a further preferred embodiment, the driving AND switching capacitor power sub-circuit includes a twenty-ninth PMOS transistor P29, a thirty-ninth PMOS transistor P30, a thirty-eleventh PMOS transistor P31, a thirty-second PMOS transistor P32, a thirty-third PMOS transistor P33, a thirty-fourth PMOS transistor P34, a forty-seventh NMOS transistor N47, a forty-eighth NMOS transistor N48, a forty-ninth NMOS transistor N49, a fifty-NMOS transistor N50, a fifty-first NMOS transistor N51, a fifty-second NMOS transistor N52, a fifty-third NMOS transistor N53, a fifty-fourth NMOS transistor N53, a fifty-fifth NMOS transistor N53, a sixth capacitor C53, a seventh capacitor C53, an eighth capacitor C53, a ninth capacitor C53, a first AND 53, a second AND 53, a third AND 53 AND a fifteenth inverter I53, wherein the drain of the twenty-ninth PMOS transistor P53 is connected to the source of the twenty-ninth PMOS transistor P53, AND the twenty-ninth NMOS transistor P53 are further connected to the drain of the twenty-ninth NMOS transistor P53, AND the twenty-ninth capacitor P53, the drain of the twenty-ninth NMOS transistor P53 is connected to the twenty-ninth transistor P53, the drain of the forty-ninth NMOS transistor N49 is connected to the source of the thirty-third PMOS transistor P33, the drain of the forty-seventh NMOS transistor N47 is connected to the drain of the forty-eighth NMOS transistor N48, the drain of the fifty-first NMOS transistor N51, the source of the fifty-second NMOS transistor N52, the drain of the thirty-eleventh PMOS transistor P31, and the drain of the thirty-second PMOS transistor P32, the source of the forty-eighth NMOS transistor N48 is connected to the drain of the thirty-fourth PMOS transistor P30, the source of the forty-eighth NMOS transistor N48 is connected to the drain of the fifty-NMOS transistor N50 through a seventh capacitor C7, the source of the thirty-eighth PMOS transistor P30 is connected to the power supply terminal, the drain of the thirty-NMOS transistor N50 is connected to the source of the thirty-fourth PMOS transistor P34, the drain of the thirty-third PMOS transistor P33 is connected to the drain of the fifty-NMOS transistor N51 and the source of the fifth NMOS transistor N55, and the thirty-third NMOS transistor P53 is connected to the drain of the thirty-eighth PMOS transistor P32, the drain of the fifty-third NMOS transistor N53 is connected to the source of the thirty-first PMOS transistor P31, the drain of the thirty-fourth PMOS transistor P34 is further connected to the drain of the fifty-fourth NMOS transistor N54 through a ninth capacitor C9, the drains of the fifty-fourth NMOS transistor N54 are respectively connected to the drain of the fifty-fifth NMOS transistor N55 AND the source of the thirty-second PMOS transistor P32, the output terminal of the first AND gate AND1 is connected to the gate of the fifty-first NMOS transistor N51, the output terminal of the fifteenth inverter is connected to the first input terminal of the second AND gate AND2, the output terminal of the second AND gate AND2 is connected to the gate of the fifty-fifth NMOS transistor N55, the output terminal of the third AND gate AND3 is connected to the gate of the fourth NMOS transistor N54, AND the source of the fifth NMOS transistor N50, the source of the third NMOS transistor N53 AND the source of the fifty-fourth NMOS transistor N54 are all connected to ground.
The input voltage of a common lithium battery ranges from 2.9V to 4.2V, a switched capacitor converter is adopted for voltage conversion, and when a fixed output of about 1V needs to be obtained, a traditional design usually only uses a certain single capacitor array, such as a 1/3 voltage conversion gain capacitor array, but the efficiency is extremely low in certain voltage ranges; therefore, in order to solve the problem of low overall efficiency in the power supply range of the lithium battery, the dual-mode topology structure is adopted in the embodiment, the voltage conversion proportion selection module is used for judging the condition of input voltage, outputting the mode conversion state, and automatically modifying the gain of the capacitor array during voltage conversion, for example, the gain topology of the capacitor array is 2/5 when the voltage is 2.9V-3.6V; the capacitor array gain is 1/3 when the voltage is 3.6V-4.2V.
In this embodiment, the battery input terminal VDDIN passes through the fourteenth PMOS transistor P14, ENABLE signal is enabled, and is connected to the fourth resistor R4 and the fifth resistor R5 that divide the voltage, and the divided voltage value is used as the input of the comparator, and by introducing the seventeenth PMOS transistor P17 and the eighteenth PMOS transistor P18 and setting the width-to-length ratio of the seventeenth PMOS transistor P17 to the eighteenth PMOS transistor P18 to be greater than that of the sixteenth PMOS transistor P16 and the nineteenth PMOS transistor P19 of the pair transistor, the internal positive feedback coefficient is greater than negative feedback, so as to obtain the comparator with hysteresis, thereby avoiding the situation that the input voltage has unique turning point when rising and falling, causing oscillation and instability. And the ENABLE is added, so that low-power consumption application of the system is guaranteed.
The comparison result of the input voltage is output at high and low levels, and when the input voltage is lower than 3.7V, VCR is 0 (low level); when the input voltage is not lower than 3.7V, VCR is 1 (high level); the comparison result is transmitted to the capacitance gain array controller as shown in fig. 8. With reference to the charge and discharge paths of the capacitor array topology shown in fig. 8 and the control signal operating waveform diagrams shown in fig. 9 and fig. 10, the following analysis can be specifically performed:
VDDIN is not lower than 3.7V, VCR is 1, the voltage conversion gain is 1/3, when CLKH, CLKM, CLKL _ B are low, the twenty-ninth PMOS transistor P29, the thirty-fourth PMOS transistor P30, the thirty-third PMOS transistor P33, the thirty-fourth PMOS transistor P34, the thirty-eleventh PMOS transistor P31, and the thirty-second PMOS transistor P32 are turned on, VDDIN charges the sixth capacitor C6, the eighth capacitor C8, the seventh capacitor C7, and the ninth capacitor C9 through the route (i), after the charging is completed, CLKH, CLKM, CLKL _ B become high, the twenty-ninth PMOS transistor P29, the thirty-fourth PMOS transistor P30, the thirty-third PMOS transistor P33, the thirty-fourth PMOS transistor P34, the thirty-eleventh PMOS transistor P31, the thirty-second PMOS transistor 32, the thirty-fourth PMOS transistor P862, the thirty-fourth PMOS transistor P8653, the thirty-fourth NMOS transistor P828653, the thirty-fourth PMOS transistor P368653, the thirty-fourth NMOS transistor P368653, the thirty-fourth PMOS transistor P53, the thirty-NMOS 368653, the thirty-fourth NMOS 368653, the thirty-NMOS 368627, and the thirty-fourth PMOS transistor P, the capacitor discharges VOUT through a second route, thereby completing charging and discharging in a period and maintaining the stability of output voltage. When VDDIN is lower than 3.7V, VCR is 0, the voltage conversion gain is 2/5, when CLKH, CLKM, CLKL _ B are low, the twenty-ninth PMOS transistor P29, the thirty-fourth PMOS transistor P30, the thirty-third PMOS transistor P33, the thirty-fourth PMOS transistor P34, the thirty-eleventh PMOS transistor P31 and the thirty-second PMOS transistor P32 are turned on, VDDIN charges the sixth capacitor C6, the eighth capacitor C8, the seventh capacitor C7 and the ninth capacitor C9 through the route (i), after the charging is completed, when CLKH, CLKM, CLKL _ B are high, the twenty-ninth PMOS transistor P29, the thirty-fourth PMOS transistor P34, the thirty-eleventh PMOS transistor P31 and the thirty-second PMOS transistor 32, the thirty-fourth PMOS transistor P33, the thirty-fourth PMOS transistor P34, the thirty-fourth PMOS transistor P31 and the thirty-fourth PMOS transistor P8653, the thirty-fourth NMOS transistor P828653, the thirty-fourth PMOS transistor P8653, the forty NMOS 368653 and the forty-fourth NMOS transistor N868653, 368653, the thirty-fourth PMOS transistor N368653, the thirty-fourth NMOS 33, and the thirty-fourth PMOS transistor P33 are turned off, the capacitor discharges VOUT through a route III, and charging and discharging are completed in one period, so that the purpose of voltage conversion is achieved; the efficiency diagram in the whole battery input voltage range reflects and adopts a dual-mode topological structure, so that the condition that some input voltages are low in efficiency under the condition of single capacitor array gain is avoided, and the whole efficiency is improved.
Referring to fig. 5, as a further preferred embodiment, the VOUT generation module includes a twenty-second PMOS transistor P22, a twenty-third PMOS transistor P23, a twenty-fourth PMOS transistor P24, a twenty-seventh NMOS transistor N27, a twenty-eighth NMOS transistor N28, a twenty-ninth NMOS transistor N29, a thirty-eighth NMOS transistor N30, a thirty-eleventh NMOS transistor N31, a thirty-second NMOS transistor N32, a thirty-third NMOS transistor N33, a thirty-fourth NMOS transistor N9, a thirty-fifth NMOS transistor N35, a fourth capacitor C4, a fifth capacitor C5 and a fourteenth inverter I14, wherein the source of the twenty-second PMOS transistor P22, the source of the twenty-third PMOS transistor P23, the source of the twenty-fourth PMOS transistor P24 and the drain of the twenty-ninth NMOS transistor N29 are connected to the power source terminals, the drain of the twenty-seventh NMOS transistor N29 is connected to the gate of the twenty-second PMOS transistor P29, the twenty-fourth PMOS transistor P29 and the twenty-eighth drain of the twenty-fourth NMOS transistor P29, the twenty-fifth NMOS transistor P29, the drain of the twenty-fifth NMOS transistor P29 are connected to the drain of the drain 29, the drain of the PMOS transistor P29, the twenty-eighth transistor P29, the drain of the twenty-fourth PMOS transistor P29 The drain of the thirty-third NMOS transistor N33 is connected to the source of a twenty-seventh NMOS transistor N27 and the source of a twenty-eighth NMOS transistor N28, respectively, the drain of the twenty-third PMOS transistor P23 is further connected to the source of a thirty-third NMOS transistor N33 through a fifth capacitor C5, the gate of the twenty-seventh NMOS transistor N27 is connected to the gate of the thirty-NMOS transistor N30 and the output terminal of the configuration output voltage module, the source of the thirty-NMOS transistor N30 is connected to the drain of the thirty-NMOS transistor N30, the source of the thirty-eleventh NMOS transistor N31 and the source of the thirty-second NMOS transistor N32, the gate of the thirty-eleventh NMOS transistor N31 is connected to the gate of the thirty-second NMOS transistor N32, the gate of the thirty-third NMOS transistor N33 and the gate of the thirty-fourth NMOS transistor N34, respectively, the gate and the drain of the thirty-second NMOS transistor N32 are connected to the source of the thirty-NMOS transistor N33, the thirty-fourth NMOS transistor N34 and the source of the thirty-fourth NMOS transistor N34, the drain of the thirty-second NMOS transistor N32 is connected to the source of the thirty-fifth NMOS transistor N35, the gate of the thirty-fifth NMOS transistor N35 is connected to the output of the fourteenth inverter I14, the source of the twenty-ninth NMOS transistor N29 is further connected to the source of the thirty-fifth NMOS transistor N35 via a fourth capacitor C4, and the source of the twenty-ninth NMOS transistor N29 is connected to the gate of the twenty-eighth NMOS transistor N28, the drain of the thirty-fourth NMOS transistor N34, the drain of the thirty-fifth NMOS transistor N35, and the second input of the driving and switching capacitor power sub-circuit, respectively.
In order to avoid the disadvantage that the output of the conventional switched capacitor converter is unstable when the conventional switched capacitor converter is started or the load is greatly changed, the VOUT generating module not only supplies power for the driving and internal devices of the switched capacitor power sub-circuit, but also is connected to the output, and when the output of the switched capacitor converter is unstable, the VOUT generating module supplies power for the output. The VOUT generation module is an LDO that incorporates a specific mismatch op-amp, whose mismatched OFFSET magnitude provides a threshold for whether to start the module.
In the embodiment of the invention, under the condition that the sizes of single tubes of a twenty-seventh NMOS tube N27 and a twenty-eighth NMOS tube N28 are the same, mismatched OFFSET amplitude values are obtained by mismatching the number of the tubes of the twenty-seventh NMOS tube N27 and the twenty-eighth NMOS tube N28, so that the output voltage deviates from VREF by a certain amplitude and can be assumed as VO _ MIN, in the power-up stage, VOUT < VO _ MIN is output by a system, a VOUT generation module supplies power for output, when the output of SC DC-DC (switched capacitor converter) is greater than VO _ MIN, the VOUT generation module maintains the static working state, a switched capacitor converter supplies power for a load, once the load is greatly changed, a control loop of the switched capacitor converter is in a limit regulation condition or a runaway condition or cannot meet the stable output of the load, and when the load voltage is lower than the VO _ MIN immediately, the system switches to supply, the stability of output is guaranteed.
Referring to fig. 6, further as a preferred embodiment, the VCO loop control module includes a twenty-fifth PMOS transistor P25, a twenty-sixth PMOS transistor P26, a thirty-sixth NMOS transistor N36, a sixth resistor R6 and a ring oscillator, a source of the twenty-fifth PMOS transistor P25 is connected to a source of the twenty-sixth PMOS transistor P26, a drain of the twenty-fifth PMOS transistor P25 is connected to a gate of the twenty-fifth PMOS transistor P25, a gate of the twenty-sixth PMOS transistor P26 and a drain of the thirty-sixth NMOS transistor N36, respectively, a source of the thirty-sixth NMOS transistor N36 is further connected to ground through the sixth resistor R6, an output end of the error amplifier is connected to a gate of the thirty-sixth NMOS transistor N36, and a drain of the twenty-sixth PMOS transistor P26 is connected to the ring oscillator.
Referring to fig. 7, as a further preferred embodiment, the error amplifier includes a twenty-seventh PMOS transistor P27, a twenty-eighth PMOS transistor P28, a thirty-seventh NMOS transistor N37, a thirty-eighth NMOS transistor N38, a thirty-ninth NMOS transistor N39, a forty-NMOS transistor N40, a forty-first NMOS transistor N41, a forty-second NMOS transistor N42, a forty-third NMOS transistor N43, a forty-fourth NMOS transistor N44, a forty-fifth NMOS transistor N45 and a forty-sixth NMOS transistor N46, the source of the twenty-seventh PMOS transistor P27, the source of the twenty-eighth PMOS transistor P28, the drain of the thirty-ninth NMOS transistor N39 and the drain of the forty-fifth NMOS transistor N45 are all connected to the power supply terminal, the drain of the twenty-seventh PMOS transistor P27 is respectively connected to the gate of the twenty-seventh PMOS transistor P27, the drain of the twenty-eighth PMOS transistor P28 and the drain of the thirty-seventh NMOS transistor N37, the twenty-eighth PMOS transistor P8653 and the thirty-eighth NMOS transistor N8653 are respectively connected to the thirty-ninth NMOS transistor N8653 and the thirty-ninth NMOS transistor N8653, the drains of the forty-third NMOS transistor N43 are respectively connected to the source of a thirty-seventh NMOS transistor N37 and the source of a thirty-eighth NMOS transistor N38, the source of the forty-first NMOS transistor N41 is connected to the source of a forty-twelfth NMOS transistor N41, the gate of the forty-first NMOS transistor N41 is respectively connected to the gate of a forty-second NMOS transistor N42, the gate of a forty-third NMOS transistor N43, the gate of a forty-fourth NMOS transistor N44 and the gate of a forty-sixth NMOS transistor N46, the source of the thirty-ninth NMOS transistor N39 is respectively connected to the gate of a forty-fifth NMOS transistor N45 and the drain of a forty-fourth NMOS transistor N44, the source of the forty-fifth NMOS transistor N45 is respectively connected to the drain of a forty-sixth NMOS transistor N46 and the input terminal of the VCO loop control module, the gate of the thirty-seventh NMOS transistor N37 is connected to the output terminal of the configuration output voltage module, and the gate of the thirty-eighth NMOS transistor N38 is connected to the power circuit and the first switch, the drain electrode of the forty-second NMOS transistor N42, the source electrode of the forty-third NMOS transistor N43, the source electrode of the forty-fourth NMOS transistor N44, the source electrode of the forty-sixth NMOS transistor N46 and the source electrode of the forty-NMOS transistor N40 are all connected with the ground.
In this embodiment, an output voltage feedback is compared with a reference voltage, the output voltage feedback enters an error signal amplifier, an error signal VCtrl controls a thirty-sixth NMOS transistor N36, the voltage change of the error signal is converted into a current change through a sixth resistor R6, the frequency of an output clock signal is changed by regulating and controlling the working current of a ring oscillator through current, the ring oscillator outputs clock signals of 15 phases, the phase shift is 24 °, and 15 switched capacitor power sub-circuits are respectively controlled through a driving circuit. In the embodiment, the feedback signal and the reference voltage are input into the amplification stage through the difference, the amplified error signal passes through the two-stage source follower, the output voltage is clamped at about 2V, the error signal output clamping effect is achieved, the error amplifier does not need a compensating capacitor and resistor, and loop control is simplified. The error signal is changed into the current signal by voltage signal through the sixteenth NMOS pipe N36 and the sixth resistance R6, through twenty-sixth PMOS pipe P26 and twenty-fifth POMS pipe of mirror image pipe, be connected to ring oscillator, the error signal changes the frequency variation of output clock into, 15 clock signal of output phase interval 24, through drive circuit, control 15 switched capacitor power level circuit's voltage conversion, the stable output load voltage, the ripple has been reduced, and the efficiency is improved.
From the above, the invention realizes wide-range voltage input, can efficiently configure the dual-mode gain topology, effectively avoids the dead zone circuit control condition of misconduction, greatly reduces the loss, and completes stable digital configurable voltage output. In addition, the VOUT generation module can ensure the stability of output during starting and transient change by introducing the LDO with the specific mismatch operational amplifier, and overcomes the defect that a control loop cannot regulate and control. Furthermore, the invention also simplifies error signal generation and loop control, and drives the switched capacitor power sub-circuit unit module through the 15-phase clock control signal, thereby reducing ripple waves and improving efficiency.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (7)

1. A switch capacitor converter system based on lithium battery SOC uses which characterized in that: the voltage conversion circuit comprises a voltage conversion proportion selection module, a VOUT generation module, a VOUT2 generation module, a VSSH generation module, a configuration output voltage module, an error amplifier, a VCO loop control module and a driving and switching capacitor power sub-circuit, wherein the output end of the voltage conversion proportion selection module is connected with the first input end of the driving and switching capacitor power sub-circuit, the output end of the VOUT generation module is connected with the second input end of the driving and switching capacitor power sub-circuit, the output end of the VOUT2 generation module is connected with the third input end of the driving and switching capacitor power sub-circuit, the output end of the VSSH generation module is connected with the fourth input end of the driving and switching capacitor power sub-circuit, the output end of the configuration output voltage module is respectively connected with the positive input end of the error amplifier, the input end of the VOUT generation module and the input end of the VOUT2 generation module, and the output end of the error amplifier is connected with, the output end of the VCO loop control module is connected with the fifth input end of the driving and switching capacitor power sub-circuit, and the first output end of the driving and switching capacitor power sub-circuit is connected with the negative input end of the error amplifier;
the configuration output voltage module is used for controlling the switch to select the conducted reference voltage according to the selection signal;
the VOUT2 generation module is used for adjusting dead time according to the working state of the switch capacitor converter system;
the VOUT generation module is used for providing power supply for the driving and switched capacitor power sub-circuit; the voltage conversion proportion selection module comprises a fourteenth PMOS (P-channel metal oxide semiconductor) tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a fourth resistor, a fifth resistor and a thirteenth phase inverter, wherein a source electrode of the fourteenth PMOS tube, a source electrode of the fifteenth PMOS tube, a source electrode of the sixteenth PMOS tube, a source electrode of the seventeenth PMOS tube, a source electrode of the eighteenth PMOS tube, a source electrode of the nineteenth PMOS tube, a source electrode of the twentieth PMOS tube and a source electrode of the twenty-first PMOS tube are all connected with a power supply end, a drain electrode of the fourteenth PMOS tube is further connected with a grid electrode of the eighteenth NMOS tube through the fourth resistor, and a drain electrode of the eighteenth NMOS, The drain electrode of the nineteenth NMOS tube is respectively connected with the drain electrode of the seventeenth PMOS tube, the gate electrode of the eighteenth PMOS tube, the gate electrode of the nineteenth PMOS tube, the drain electrode of the twentieth PMOS tube and the gate electrode of the twenty-first PMOS tube, the drain electrode of the twenty-first PMOS tube is respectively connected with the drain electrode of the twenty-fifth NMOS tube, the drain electrode of the twenty-sixth NMOS tube and the first input end of the driving and switching capacitance power sub-circuit, the gate electrode of the eighteenth NMOS tube is connected with the gate electrode of the twentieth NMOS tube, the gate electrode of the eighteenth NMOS tube is further connected with the source electrode of the twenty-first NMOS tube through a fifth resistor, the source electrode of the eighteenth NMOS tube is respectively connected with the source electrode of the nineteenth NMOS tube and the drain electrode of the twenty-third NMOS tube, and the source electrodes of the twenty-second NMOS tube and the twenty-third NMOS tube are respectively connected with the source electrode of the twentieth NMOS tube, The drain electrode of the twenty-first NMOS tube is connected with the source electrode of the twenty-first NMOS tube, the grid electrode of the twenty-first NMOS tube is respectively connected with the grid electrode of the twenty-second NMOS tube, the grid electrode of the twenty-third NMOS tube, the drain electrode of the twenty-fourth NMOS tube and the grid electrode of the twenty-sixth NMOS tube, the grid electrode of the twenty-fourth NMOS tube is connected with the grid electrode of the twenty-fifth NMOS tube, the drain electrode of the twenty-second NMOS tube, the source electrode of the twenty-third NMOS tube, the source electrode of the twenty-fourth NMOS tube, the source electrode of the twenty-fifth NMOS tube and the source electrode of the twenty-sixth NMOS tube are all connected with the ground, the output end of the thirteenth phase inverter is respectively connected with the grid electrode of the fifteenth PMOS tube and the grid electrode of the twenty-PMOS tube, and the grid electrode of the nineteenth NMOS tube is connected with.
2. The switched capacitor converter system of claim 1 for lithium battery SOC applications, wherein: the output voltage configuration module comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a first capacitor, a first resistor, a second resistor, a third resistor, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube and the drain electrode of the seventh NMOS tube are all connected with a power supply end, the grid electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube, the drain electrode of the first PMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is respectively connected with the grid electrode of the seventh NMOS tube, the drain electrode of the second NMOS tube and the drain electrode of the eighth NMOS tube, the source electrode of the first PMOS tube is respectively connected with the drain electrode of the third NMOS tube, the grid electrode of the first NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is respectively connected with the source electrode of the fifth NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the sixth NMOS tube, the grid electrode of the sixth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the ninth NMOS tube, the drain electrode of the second PMOS tube is further connected with the ground through a first capacitor, the grid electrode of the second NMOS tube is respectively connected with the source electrode of the seventh NMOS tube, the source electrode of the eighth NMOS tube and the drain electrode of the ninth NMOS tube, the output end of the first phase inverter is connected with the grid electrode of the eighth NMOS tube, the source electrode of the seventh NMOS tube is further connected with the source electrode of the fourth PMOS tube through a first resistor, the source electrode of the fourth PMOS tube is further connected with the source electrode of the fifth PMOS tube through a second resistor, and the source electrode of the fifth PMOS tube is further connected with the ground through a third resistor, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube, the output end of the fourth phase inverter is connected with the grid electrode of the fifth PMOS tube, the grid electrode of the fourth PMOS tube is respectively connected with the output end of the third phase inverter and the input end of the fourth phase inverter, the output end of the second phase inverter is connected with the input end of the third phase inverter, the drain electrode of the fifth PMOS tube is connected with the positive input end of the error amplifier, and the drain electrode of the fourth NMOS tube, the source electrode of the third NMOS tube and the source electrode of the ninth NMOS tube are all connected with the ground.
3. The switched capacitor converter system of claim 1 for lithium battery SOC applications, wherein: the VOUT2 generation module comprises a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a fifty-sixth NMOS tube, a twelfth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, a second capacitor, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter and a twelfth inverter, wherein a source electrode of the sixth PMOS tube and a source electrode of the eighth PMOS tube are both connected with power supply ends, a drain electrode of the sixth PMOS tube is respectively connected with a drain electrode of the tenth NMOS tube and a gate electrode of the eighth PMOS tube, a source electrode of the tenth NMOS tube is connected with a drain electrode of the eleventh NMOS tube, and a gate electrode of the sixth PMOS tube is respectively connected with a gate electrode of the eleventh NMOS tube, a gate electrode of the seventh PMOS tube, a gate electrode of the eleventh NMOS tube, a gate electrode of the thirteenth NMOS tube, a source electrode of, A grid electrode of a thirteenth NMOS tube, an output end of a sixth inverter and an input end of a seventh inverter are connected, a source electrode of the seventh PMOS tube is connected with a power supply end, a drain electrode of the seventh PMOS tube is connected with a source electrode of a twelfth NMOS tube, a drain electrode of the twelfth NMOS tube is respectively connected with a drain electrode of the thirteenth NMOS tube and a grid electrode of a fourteenth NMOS tube, a grid electrode of the twelfth NMOS tube is respectively connected with a grid electrode of a tenth NMOS tube and an output end of the eighth inverter, a source electrode of the thirteenth NMOS tube is respectively connected with a source electrode of a fourteenth NMOS tube, a source electrode of a ninth PMOS tube, a source electrode of the twelfth PMOS tube and a third input end of the driving and switching capacitance power sub-circuit, a drain electrode of the eighth PMOS tube is connected with a drain electrode of the fourteenth NMOS tube, a drain electrode of the eighth PMOS tube is further connected with a drain electrode of a fifteenth NMOS tube through a second capacitor, and a drain electrode of the fifteenth NMOS tube is respectively connected with a drain electrode of the ninth PMOS, A grid electrode of a tenth PMOS tube is connected with a grid electrode of a fifty-sixth NMOS tube, a source electrode of the fifteenth NMOS tube and a source electrode of the sixteenth NMOS tube are both connected with the ground, a grid electrode of the fifteenth NMOS tube is respectively connected with a drain electrode of the sixteenth NMOS tube and a drain electrode of the tenth PMOS tube, a source electrode of the tenth PMOS tube is connected with a drain electrode of the eleventh PMOS tube, a source electrode of the seventeenth NMOS tube is connected with the ground, a drain electrode of the seventeenth NMOS tube is connected with a source electrode of the fifty-sixth NMOS tube, a grid electrode of the ninth PMOS tube is respectively connected with a drain electrode of the fifty-sixth NMOS tube and a drain electrode of the twelfth PMOS tube, a grid electrode of the sixteenth PMOS tube is respectively connected with a grid electrode of the eleventh PMOS tube, a grid electrode of the seventeenth NMOS tube and a grid electrode of the twelfth NMOS tube, the first path of clock signal is further connected with an input end of the sixth phase inverter through the fifth phase inverter, and an output end of the seventh phase, and the second path of clock signals sequentially passes through the ninth phase inverter, the tenth phase inverter, the eleventh phase inverter and the twelfth phase inverter and is further connected with the grid electrode of the twelfth PMOS tube, and the source electrode of the eleventh NMOS tube and the source electrode of the eleventh PMOS tube are both connected with the third input end of the driving and switched capacitor power sub-circuit.
4. The switched capacitor converter system of claim 1 for lithium battery SOC applications, wherein: the VOUT generating module comprises a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirty-eleventh NMOS tube, a thirty-second NMOS tube, a thirty-third NMOS tube, a thirty-fourth NMOS tube, a thirty-fifth NMOS tube, a fourth capacitor, a fifth capacitor and a fourteenth inverter, wherein the source electrode of the twenty-second PMOS tube, the source electrode of the twenty-third PMOS tube, the source electrode of the twenty-fourth PMOS tube and the drain electrode of the twenty-ninth NMOS tube are all connected with a power supply end, the drain electrode of the twenty-seventh NMOS tube is respectively connected with the drain electrode of the twenty-second PMOS tube, the gate electrode of the twenty-third PMOS tube and the drain electrode of the twenty-fourth PMOS tube, the drain electrode of the twenty-third PMOS tube is respectively connected with the drain electrode of the twenty-eighth NMOS tube and the gate electrode of the twenty-ninth NMOS tube, and the drain electrode of the thirty-third NMOS tube is respectively connected with the source electrode of the twenty-eighth NMOS, the drain electrode of the twenty-third PMOS tube is further connected with the source electrode of a thirty-third NMOS tube through a fifth capacitor, the gate electrode of the twenty-seventh NMOS tube is respectively connected with the gate electrode of the thirty-NMOS tube and the output end of the configuration output voltage module, the source electrode of the thirty-NMOS tube is respectively connected with the drain electrode of the thirty-NMOS tube, the source electrode of the thirty-eleventh NMOS tube and the source electrode of the thirty-second NMOS tube, the gate electrode of the thirty-eleventh NMOS tube is respectively connected with the gate electrode of the thirty-second NMOS tube, the gate electrode of the thirty-third NMOS tube and the gate electrode of the thirty-fourth NMOS tube, the gate electrode and the drain electrode of the thirty-second NMOS tube are respectively connected with the gate electrode and the source electrode of the thirty-third NMOS tube and the gate electrode and the source electrode of the thirty-fourth NMOS tube, the drain electrode of the thirty-second NMOS tube is connected with the source electrode of the thirty-fifth NMOS tube, the gate electrode of the thirty-fifth NMOS tube is connected with the output end of the fourteenth inverter, and the source electrode of the twenty-ninth, and the source electrode of the twenty-ninth NMOS tube is respectively connected with the grid electrode of the twenty-eighth NMOS tube, the drain electrode of the thirty-fourth NMOS tube, the drain electrode of the thirty-fifth NMOS tube and the second input end of the driving and switching capacitor power sub-circuit.
5. The switched capacitor converter system of claim 1 for lithium battery SOC applications, wherein: the VCO loop control module comprises a twenty-fifth PMOS (P-channel metal oxide semiconductor) tube, a twenty-sixth PMOS tube, a thirty-sixth NMOS (N-channel metal oxide semiconductor) tube, a sixth resistor and a ring oscillator, wherein a source electrode of the twenty-fifth PMOS tube is connected with a source electrode of the twenty-sixth PMOS tube, a drain electrode of the twenty-fifth PMOS tube is respectively connected with a grid electrode of the twenty-fifth PMOS tube, a grid electrode of the twenty-sixth PMOS tube and a drain electrode of the thirty-sixth NMOS tube, a source electrode of the thirty-sixth NMOS tube is further connected with the ground through the sixth resistor, an output end of the error amplifier is connected with a grid electrode of the thirty-sixth NMOS tube, and a drain electrode of the twenty-sixth PMOS tube is connected with the ring oscillator.
6. The switched capacitor converter system of claim 1 for lithium battery SOC applications, wherein: the error amplifier comprises a twenty-seventh PMOS tube, a twenty-eighth PMOS tube, a thirty-seventh NMOS tube, a thirty-eighth NMOS tube, a thirty-ninth NMOS tube, a forty-first NMOS tube, a forty-second NMOS tube, a forty-third NMOS tube, a forty-fourth NMOS tube, a forty-fifth NMOS tube and a forty-sixth NMOS tube, wherein a source electrode of the twenty-seventh PMOS tube, a source electrode of the twenty-eighth PMOS tube, a drain electrode of the thirty-ninth NMOS tube and a drain electrode of the forty-fifth NMOS tube are all connected to a power supply end, a drain electrode of the twenty-seventh PMOS tube is respectively connected to a gate electrode of the twenty-seventh PMOS tube, a gate electrode of the twenty-eighth PMOS tube and a drain electrode of the thirty-seventh NMOS tube, a drain electrode of the twenty-eighth PMOS tube is respectively connected to a drain electrode of the thirty-eighth NMOS tube, a gate electrode of the thirty-ninth NMOS tube and a drain electrode of the forty-NMOS tube, and a drain electrode of the thirty-eighth NMOS tube is respectively connected to a drain electrode of the thirty-seventh PMOS tube, the source electrode of the forty-first NMOS transistor is connected with the source electrode of the forty-twelfth NMOS transistor, the grid electrode of the forty-first NMOS transistor is respectively connected with the grid electrode of the forty-second NMOS transistor, the grid electrode of the forty-third NMOS transistor, the grid electrode of the forty-fourth NMOS transistor and the grid electrode of the forty-sixth NMOS transistor, the source electrode of the thirty-ninth NMOS transistor is respectively connected with the gate electrode of the forty-fifth NMOS transistor and the drain electrode of the forty-fourth NMOS transistor, the source electrode of the forty-fifth NMOS transistor is respectively connected with the drain electrode of the forty-sixth NMOS transistor and the input end of the VCO loop control module, the grid of the thirty-seventh NMOS transistor is connected with the output end of the output voltage configuration module, the grid of the thirty-eighth NMOS transistor is connected with the first output end of the driving and switching capacitor power sub-circuit, the drain electrode of the forty-second NMOS transistor, the source electrode of the forty-third NMOS transistor, the source electrode of the forty-fourth NMOS transistor, the source electrode of the forty-sixth NMOS transistor and the source electrode of the forty-NMOS transistor are all connected with the ground.
7. The switched capacitor converter system of claim 1 for lithium battery SOC applications, wherein: the driving and switching capacitor power sub-circuit comprises a twenty-ninth PMOS tube, a thirty-sixth PMOS tube, a thirty-first PMOS tube, a thirty-second PMOS tube, a thirty-third PMOS tube, a thirty-fourth PMOS tube, a forty-seventh NMOS tube, a forty-eighth NMOS tube, a forty-ninth NMOS tube, a fifty-first NMOS tube, a fifty-second NMOS tube, a fifty-third NMOS tube, a fifty-fourth NMOS tube, a fifty-fifth NMOS tube, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a first AND gate, a second AND gate, a third AND gate and a fifteenth inverter, wherein the source electrode of the twenty-ninth PMOS tube is connected with a power supply end, the drain electrode of the twenty-ninth PMOS tube is connected with the source electrode of the forty-seventh NMOS tube, the drain electrode of the twenty-ninth PMOS tube is further connected with the drain electrode of the forty-ninth NMOS tube through the sixth capacitor, and the drain electrode of the forty-ninth NMOS tube is connected with the source electrode of the thirty-third PMOS tube, the drain electrode of the forty-seventh NMOS transistor is respectively connected with the drain electrode of a forty-eighth NMOS transistor, the drain electrode of a fifty-first NMOS transistor, the source electrode of a fifty-second NMOS transistor, the drain electrode of a thirty-eleventh PMOS transistor and the drain electrode of a thirty-second PMOS transistor, the source electrode of the forty-eighth NMOS transistor is connected with the drain electrode of the thirty-fourth PMOS transistor, the source electrode of the forty-eighth NMOS transistor is further connected with the drain electrode of the fifty-NMOS transistor through a seventh capacitor, the source electrode of the thirty-PMOS transistor is connected with the power supply terminal, the drain electrode of the fifty-NMOS transistor is connected with the source electrode of the thirty-fourth PMOS transistor, the drain electrode of the thirty-third PMOS transistor is respectively connected with the source electrode of the fifty-first NMOS transistor and the source electrode of the fifty-fifth NMOS transistor, the drain electrode of the fifty-third PMOS transistor is further connected with the drain electrode of the fifty-third NMOS transistor through an eighth capacitor, the drain electrode of the third NMOS transistor is connected with the source electrode of the thirty-fourth PMOS transistor through a ninth capacitor, the drain electrode of the fifty-fourth NMOS tube is respectively connected with the drain electrode of the fifty-fifth NMOS tube and the source electrode of the thirty-second PMOS tube, the output end of the first AND gate is connected with the gate electrode of the fifty-first NMOS tube, the output end of the fifteenth inverter is connected with the first input end of the second AND gate, the output end of the second AND gate is connected with the gate electrode of the fifty-fifth NMOS tube, the output end of the third AND gate is connected with the gate electrode of the fifty-fourth NMOS tube, and the source electrode of the fifty-fourth NMOS tube, the source electrode of the fifty-third NMOS tube and the source electrode of the fifty-fourth NMOS tube are all connected with the ground.
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