WO2018047448A1

WO2018047448A1 - Signal generation circuit

Info

Publication number: WO2018047448A1
Application number: PCT/JP2017/023965
Authority: WO
Inventors: 小林　敦; 剛松崎
Original assignee: 株式会社デンソー
Priority date: 2016-09-09
Filing date: 2017-06-29
Publication date: 2018-03-15
Also published as: JP2018042430A

Abstract

A signal generation circuit (1) is provided with a signal generation unit (3) that generates two rectangular wave signals that are used in a charge pump circuit (2), and have dead times that vary in a complementary manner and indicate when both rectangular wave signals are off, the signal generation unit (3) generating the two rectangular wave signals having a fixed frequency and having a prescribed duty such that the odd-order harmonic peak is higher than the even-order harmonic peak. The signal generation unit is provided with a dead-time varying unit (4) for cyclically varying the dead times, while the average duty of the two rectangular wave signals is maintained to be at a prescribed duty.

Description

Signal generation circuit

Cross-reference of related applications

This application is based on Japanese Patent Application No. 2016-176663 filed on September 9, 2016, the contents of which are incorporated herein by reference.

The present disclosure relates to a signal generation circuit that generates two rectangular wave signals that change in a complementary manner and have a dead time at which both indicate off.

A signal generation circuit that generates a general rectangular wave signal is designed so that the duty of the generated rectangular wave signal is 50% or a value close to it because of the simplicity of the circuit and the small number of elements. There are many. It is known that the peak of the odd-order harmonic component is relatively high and the peak of the even-order harmonic component is relatively low in the rectangular wave signal having a duty of about 50%. For this reason, when the generated rectangular wave signal is used in a charge pump circuit or the like that needs to be designed with a high driving capability, there arises a problem that odd-order harmonics cannot meet the standards for emission noise. There is a fear.

Patent Document 1 discloses a technique for reducing noise by measuring and feeding back noise externally and performing duty control (PWM control) according to the noise measurement result.

JP 2012-110060 A

When a rectangular wave signal is used in a charge pump circuit, the duty of the rectangular wave signal is fixed at about 50%, and PWM control with variable duty as in the technique described in Patent Document 1 cannot be applied. Therefore, in order to satisfy such a noise standard, it is necessary to separately provide noise countermeasure parts such as an external capacitor and a filter, but this increases the physique and cost of the apparatus.

An object of the present disclosure is to provide a signal generation circuit that can reduce noise of harmonic components without using noise countermeasure components such as a filter and an external capacitor.

In the first aspect of the present disclosure, the signal generation circuit generates two rectangular wave signals that are used in the charge pump circuit and change in a complementary manner and have a dead time at which both of them indicate off. A signal generation unit is provided. The signal generation unit generates two rectangular wave signals having a predetermined duty so that the frequency is constant and the peak of odd harmonics is higher than the peak of even harmonics. The signal generation unit includes a dead time changing unit that periodically changes the dead time while maintaining the average duty of the two rectangular wave signals to be a predetermined duty.

When the dead time of the two rectangular wave signals changes periodically, the duty of at least one of the two rectangular wave signals changes periodically. As a result, the harmonic component contained in at least one of the two rectangular wave signals is diffused, and as a result, the peak of the odd-order harmonic component can be kept low, and the standard regarding emission noise can be satisfied. Further, the signal generation circuit has a configuration suitable for use in a charge pump circuit because the frequency of the rectangular wave signal is constant and the average duty is maintained at a predetermined duty. Therefore, according to the above configuration, it is possible to obtain an excellent effect that noise of harmonic components can be reduced without using a noise countermeasure component circuit scale such as a filter or an external capacitor.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a diagram schematically illustrating a configuration of a signal generation circuit and a charge pump circuit according to an embodiment. FIG. 2 is a diagram schematically illustrating a specific configuration example of the signal generation circuit. FIG. 3 is a timing chart schematically showing the waveform of the signal and voltage of each part. FIG. 4 is a timing chart schematically showing signal and voltage waveforms of each part when the dead time is periodically changed. FIG. 5 is a timing chart showing the waveform of the clock signal in the upper stage and the duty of the clock signal in the lower stage. FIG. 6 is a diagram illustrating frequency distribution in the signal generation circuit and the charge pump circuit. FIG. 7 is a diagram illustrating a result of simulating circuit operation.

Hereinafter, an embodiment will be described with reference to the drawings.
As shown in FIG. 1, the signal generation circuit 1 generates clock signals CLK1 and CLK2 corresponding to rectangular wave signals using a clock signal CLK given from the outside. In this case, the clock signals CLK1 and CLK2 are used in the charge pump circuit 2, and as shown in FIG. 3, the clock signals CLK1 and CLK2 change in a complementary manner and have a dead time in which both become off levels. In this case, the high level of the clock signals CLK1 and CLK2 is the power supply voltage VDD (for example, 5V) of the circuit, and the low level is the reference potential GND (for example, 0V) of the circuit.

The signal generation unit 3 included in the signal generation circuit 1 generates two rectangular wave signals having a constant frequency of, for example, 10 kHz and a duty of 50% (= 0.5). Then, the signal generator 3 outputs, as the clock signals CLK1 and CLK2, the two rectangular wave signals that are generated, the dead duty of which is periodically changed while maintaining the average duty at 50%. Such a function of changing the dead time is realized by the dead time changing unit 4.

The charge pump circuit 2 is provided, for example, in an electronic control device mounted on a vehicle, and boosts and outputs the power supply voltage VDD by about twice. The output voltage Vo output via the output power line Lo of the charge pump circuit 1 is supplied to a load circuit (not shown). In the present embodiment, the signal generation circuit 1 and the charge pump circuit 2 are configured as a semiconductor integrated circuit, that is, an IC. Note that the capacitors C1 and C2 included in the charge pump circuit 2 may have a so-called external configuration provided outside the IC.

Switches S1 and S2 are connected in series in this order between the input power supply line Li to which the power supply voltage VDD is applied and the output power supply line Lo. Switches S3 and S4 are connected in series in this order between the input power line Li and the ground line Lg to which the reference potential GND is applied. A capacitor C1 is connected between the interconnection node N1 of the switches S1 and S2 and the interconnection node N2 of the switches S3 and S4. A capacitor C2 is connected between the output power supply line Lo and the ground line Lg.

The switches S1 to S4 are constituted by semiconductor switching elements such as MOS transistors, for example. A clock signal CLK2 is supplied to the conduction control terminal (for example, a gate) of the switch S1, and a clock signal CLK1 is supplied to the conduction control terminals of the switches S2 and S3. A signal obtained by inverting the clock signal CLK1 is supplied to the conduction control terminal of the switch S4 via the inverter circuit 5.

The switches S1 to S4 are turned on when the signal applied to the conduction control terminal is at a high level and turned off when the signal is at a low level. Accordingly, the switch S1 is turned on when the clock signal CLK2 is at a high level and turned off when the clock signal CLK2 is at a low level. The switches S2 and S3 are turned on when the clock signal CLK1 is at a high level and turned off when the clock signal CLK1 is at a low level. The switch S4 is turned on when the clock signal CLK1 is at a low level and turned off when the clock signal CLK1 is at a high level.

That is, the switches S1 and S4 and the switches S2 and S3 are turned on and off in a complementary manner. As the switches S1 to S4 are turned on / off in this manner, the capacitor C1 is charged / discharged. As a result, the boost operation by the charge pump circuit 1 is realized. At this time, the potentials of the two nodes N1 and N2 change according to the clock signals CLK1 and CLK2, and thus become emission noise sources.

As a specific configuration of the signal generation circuit 1 that generates the clock signals CLK1 and CLK2, for example, a configuration as shown in FIG. 2 can be adopted. In this case, the signal generation circuit 1 includes

inverter circuits

11 and 12, an RC filter circuit 13, a switching unit 14, an AND circuit 15, and a NOR circuit 16.

A clock signal CLK is supplied to one input terminal of each of the AND circuit 15 and the NOR circuit 16. A delayed clock signal F is supplied to the other input terminal of each of the AND circuit 15 and the NOR circuit 16. The signal output from the AND circuit 15 is the clock signal CLK1. The signal output from the NOR circuit 16 is the clock signal CLK2.

The delayed clock signal F is a signal obtained by delaying the clock signal CLK by a predetermined delay time, and is generated as follows. That is, the clock signal CLK is inverted by the inverter circuit 11, the inverted signal is input to the RC filter circuit 13, and a signal obtained by inverting the output of the RC filter circuit 13 by the inverter circuit 12 is the delayed clock signal F.

Here, the RC filter circuit 13 is configured to switch its time constant. The time constant of the RC filter circuit 13 is switched by a switching unit 14 including a counter. The delay time of the delayed clock signal F is switched according to the switching of the time constant of the RC filter circuit 13.

In this case, the RC filter circuit 13 includes a plurality of resistors Ra connected in series between the input / output terminals, a plurality of switches Sa connected in parallel to each of the resistors Ra, and between the output terminal and the ground line Lg. And a connected capacitor Ca. The switch Sa is turned on / off according to a switching signal given from the switching unit 14. According to such a configuration, the number of resistors Ra connected between the input / output terminals can be changed according to the on / off state of the switch Sa, whereby the time constant of the RC filter circuit 13 can be switched.

As shown in FIG. 3, the clock signals CLK1 and CLK2 generated by the signal generation circuit 1 having the above configuration have a dead time Td in which both change in a complementary manner and become low level. In FIG. 3, for convenience of explanation, the dead time Td is slightly exaggerated, but the actual dead time Td is much shorter than one cycle of the clock signals CLK1 and CLK2.

In this case, the dead time Td of the clock signals CLK1 and CLK2 is determined according to the delay time of the delayed clock signal F with respect to the clock signal CLK. Therefore, the dead time Td can be changed by switching the time constant of the RC filter 13.

As shown in FIG. 4, when the dead time Td is changed periodically, for example, every period, the duty of the clock signals CLK1 and CLK2 and the signals of the nodes N1 and N2 that become noise sources (hereinafter referred to as noise) are accordingly generated. The duty of the source signal also changes. In FIG. 4, the dead time and the change range of the duty are exaggerated for easy understanding.

In FIG. 4, the dead time Td is changed in three stages: Td (small), Td (medium), and Td (large). The value of the dead time Td has a relationship of “Td (small) <Td (medium) <Td (large)”. As shown in FIG. 4, when the dead time Td is the smallest Td (small), the signal duty of the nodes N1 and N2 is the largest, and when the dead time Td is the largest Td (large), the nodes n1 and N2 The signal duty is the smallest. That is, in the above configuration, the duty of the signals at the nodes N1 and N2 increases as the dead time Td of the clock signals CLK1 and CLK2 decreases, and the duty of the signals at the nodes N1 and N2 decreases as the dead time Td increases. Yes.

The signal generation circuit 1 according to the present embodiment periodically switches the dead time Td of the clock signals CLK1 and CLK2 by periodically switching the time constant of the RC filter circuit 13. However, in this case, the dead time Td is switched while maintaining the average duty of the clock signals CLK1, CLK2, and hence the noise source signal at 50%. In the present embodiment, the switching is performed for each cycle of the clock signals CLK1 and CLK2.

In this case, as shown in FIG. 5, the duty of the clock signals CLK1 and CLK2 gradually increases and starts decreasing when reaching the upper limit, gradually decreases and then increases again when reaching the lower limit. In addition, the dead time Td is changed so as to change with regularity. Specifically, the dead time Td is changed so that the duty of the clock signals CLK1 and CLK2 changes like a sine wave. In this way, it is possible to periodically change the duty of each of the signals while maintaining the average duty of the clock signals CLK1, CLK2 and the noise source signal at 50%. As described above, the frequencies of the clock signals CLK1 and CLK2 are made constant.

Here, if the duty ratios of the clock signals CLK1 and CLK2 change too much, there is a risk that the boosting efficiency of the charge pump circuit 2 will be reduced and the output voltage Vo will be fluctuated, and the boosting operation cannot be performed normally. There is also a fear. Therefore, in this case, the dead time Td is switched so that the upper and lower limits of the duty of the clock signals CLK1 and CLK2 are within a range in which the charge pump circuit 2 can perform the desired operation.

As described above, in the signal generation circuit 1, the duty of the clock signals CLK1 and CLK2 is changed according to the change of the dead time Td, but the average duty is maintained at 50% to the last. . That is, the signal generation circuit 1 of the present embodiment does not perform PWM control that changes the duty in order to control the state of the control target to a target state.

According to this embodiment described above, the following effects can be obtained.
The signal generation circuit 1 periodically changes the dead time Td while maintaining the average duty of the clock signals CLK1 and CLK2 used in the charge pump circuit 2 to be 50%. As the dead times of the clock signals CLK1 and CLK2 change periodically, the duty of the clock signals CLK1 and CLK2 and thus the noise source signal changes periodically. Thereby, the harmonic components contained in the clock signals CLK1 and CLK2 and the noise source signal are diffused.

As a result, as is clear from FIG. 6 showing the spectrum (frequency distribution) in the present embodiment, the peak of the odd-order harmonic component can be suppressed to be lower than that of the conventional technique that does not change the dead time Td. For this reason, the spectrum envelope does not exceed the standard line, and the standard regarding emission noise can be satisfied. In FIG. 6, for comparison with the present embodiment, the spectrum in the prior art in which the dead time Td is not changed is indicated by a dotted line. Incidentally, in this case, the peak of the even-order harmonic component is slightly higher than that of the prior art, but the peak of the even-order harmonic component is originally low, so the standard for emission noise is also applied to the even-order harmonic component. You can be satisfied enough.

As described above, according to the present embodiment, it is possible to obtain an excellent effect that noise of harmonic components can be reduced without using a noise countermeasure component circuit scale such as a filter or an external capacitor. Such an effect obtained by the present embodiment is also apparent from FIG. 7 showing the result of simulating the circuit operation.

In this simulation, the upper limit of the duty of the clock signals CLK1 and CLK2 is set to 53% and the lower limit is set to 47%. In this case, the dead time Td is changed so that the duty changes by 1% for each cycle of the clock signals CLK1 and CLK2. Furthermore, in this case, the frequency of the clock signals CLK1 and CLK2 is 10 kHz.

As shown in FIG. 7, according to the present embodiment, the peak of the odd-order harmonic component is low over almost the entire frequency band as compared with the conventional technique in which the duty of the clock signal is fixed to 50%. In particular, in the AM band, it can be seen that a reduction effect of about 5 dB is obtained. The noise reduction effect in the AM band is very beneficial when the signal generation circuit 1 and the charge pump circuit 2 are used in an in-vehicle application that requires consideration for radio noise.

In the signal generation circuit 1, the frequencies of the two clock signals CLK1 and CLK2 are constant and the average duty is maintained at 50%. Therefore, the charge pump circuit 2 can perform the same operation as that of the prior art in which the duty of the clock signal is fixed to 50%. That is, according to the present embodiment, it is possible to reduce the noise of harmonic components without impairing the original operation of the charge pump circuit 2.

(Other embodiments)
The present disclosure is not limited to the embodiments described above and illustrated in the drawings, and can be arbitrarily modified, combined, or expanded without departing from the scope of the present disclosure.

In the above-described embodiment, the change in the dead time Td is performed for each cycle of the clock signals CLK1 and CLK2. However, the present invention is not limited to this, and may be performed for every plurality of cycles of the clock signals CLK1 and CLK2, for example. However, it may be changed irregularly.

The average duty of the clock signals CLK1 and CLK2 only needs to be such that the peak value of the odd-order harmonic is larger than the peak value of the even-order harmonic, for example, a value slightly larger than 50% or slightly smaller. It may be a value (a value of about 50%). Even with such an average duty, the noise reduction effect of the harmonic component according to the present embodiment can be obtained.

The method of changing the dead time Td is not limited to the one in which the duty of the clock signals CLK1 and CLK2 changes gently and regularly, or the one in which the duty of the clock signals CLK1 and CLK2 changes abruptly. It may be changed irregularly.

In the above embodiment, both the dead time Td between the falling edge of the clock signal CLK1 and the rising edge of the clock signal CLK2 and the dead time between the falling edge of the clock signal CLK2 and the rising edge of the clock signal CLK1 are changed. Thus, the duty of both the clock signals CLK1 and CLK2 is changed. However, the dead time may be changed so that the duty of at least one of the clock signals CLK1 and CLK2 is changed. Even in this case, the harmonic component contained in at least one of the clock signals CLK1 and CLK2 is diffused, so that the effect of reducing harmonic noise can be obtained.

Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims

A signal generation circuit (1) used for the charge pump circuit (2), which generates two rectangular wave signals having a dead time that changes in a complementary manner and has a level indicating both off,
A signal generator (3) for generating the two rectangular wave signals having a predetermined duty such that the frequency is constant and the peak of the odd harmonic is higher than the peak of the even harmonic;
The signal generation circuit includes a dead time changing unit (4) that periodically changes the dead time while maintaining an average duty of the two rectangular wave signals to be the predetermined duty.
The signal generation circuit according to claim 1, wherein the dead time changing unit changes the dead time within a range in which the charge pump circuit can perform a desired operation.
3. The signal generation circuit according to claim 1, wherein the dead time changing unit changes the dead time for each period of the rectangular wave signal.
The signal generation circuit according to any one of claims 1 to 3, wherein the predetermined duty is 0.5.